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 * Copyright 2020 Google Inc.
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
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 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
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#ifndef __ARCH_RISCV_SE_WORKLOAD_HH__
#define __ARCH_RISCV_SE_WORKLOAD_HH__

#include "arch/riscv/reg_abi.hh"
#include "arch/riscv/regs/int.hh"
#include "arch/riscv/remote_gdb.hh"
#include "params/RiscvSEWorkload.hh"
#include "sim/se_workload.hh"
#include "sim/syscall_abi.hh"

namespace gem5
{

namespace RiscvISA
{

class SEWorkload : public gem5::SEWorkload
{
  public:
    PARAMS(RiscvSEWorkload);

    SEWorkload(const Params &p, Addr page_shift) :
        gem5::SEWorkload(p, page_shift)
    {}

    void
    setSystem(System *sys) override
    {
        gem5::SEWorkload::setSystem(sys);
        gdb = BaseRemoteGDB::build<RemoteGDB>(
                params().remote_gdb_port, system);
    }

    loader::Arch getArch() const override { return loader::Riscv64; }

    using SyscallABI64 = RegABI64;
    using SyscallABI32 = RegABI32;
};

} // namespace RiscvISA

namespace guest_abi
{

template <>
struct Result<RiscvISA::SEWorkload::SyscallABI64, SyscallReturn>
{
    static void
    store(ThreadContext *tc, const SyscallReturn &ret)
    {
        if (ret.successful()) {
            // no error
            tc->setReg(RiscvISA::ReturnValueReg, ret.returnValue());
        } else {
            // got an error, return details
            tc->setReg(RiscvISA::ReturnValueReg, ret.encodedValue());
        }
    }
};

template <>
struct Result<RiscvISA::SEWorkload::SyscallABI32, SyscallReturn>
{
    static void
    store(ThreadContext *tc, const SyscallReturn &ret)
    {
        if (ret.successful()) {
            // no error
            tc->setReg(RiscvISA::ReturnValueReg, sext<32>(ret.returnValue()));
        } else {
            // got an error, return details
            tc->setReg(RiscvISA::ReturnValueReg, sext<32>(ret.encodedValue()));
        }
    }
};

} // namespace guest_abi
} // namespace gem5

#endif // __ARCH_RISCV_SE_WORKLOAD_HH__