# Copyright (c) 2020 ARM Limited
# Copyright (c) 2003-2005 The Regents of The University of Michigan
# Copyright (c) 2013 Advanced Micro Devices, Inc.
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from m5.params import *

# Set of boolean static instruction properties.
#
# Notes:
# - The IsInteger and IsFloating flags are based on the class of registers
# accessed by the instruction.  Although most instructions will have exactly
# one of these two flags set, it is possible for an instruction to have
# neither (e.g., direct unconditional branches, memory barriers) or both
# (e.g., an FP/int conversion).
# - If IsControl is set, then exactly one of IsDirectControl or IsIndirect
# Control will be set, and exactly one of IsCondControl or IsUncondControl
# will be set.


class StaticInstFlags(Enum):
    wrapper_name = "StaticInstFlags"
    wrapper_is_struct = True
    enum_name = "Flags"

    vals = [
        "IsNop",  # Is a no-op (no effect at all).
        "IsInteger",  # References integer regs.
        "IsFloating",  # References FP regs.
        "IsVector",  # References Vector regs.
        "IsVectorElem",  # References Vector reg elems.
        "IsMatrix",  # References Matrix regs.
        "IsLoad",  # Reads from memory (load or prefetch).
        "IsStore",  # Writes to memory.
        "IsAtomic",  # Does atomic RMW to memory.
        "IsStoreConditional",  # Store conditional instruction.
        "IsInstPrefetch",  # Instruction-cache prefetch.
        "IsDataPrefetch",  # Data-cache prefetch.
        "IsControl",  # Control transfer instruction.
        "IsDirectControl",  # PC relative control transfer.
        "IsIndirectControl",  # Register indirect control transfer.
        "IsCondControl",  # Conditional control transfer.
        "IsUncondControl",  # Unconditional control transfer.
        "IsCall",  # Subroutine call.
        "IsReturn",  # Subroutine return.
        "IsSerializing",  # Serializes pipeline: won't execute until all
        # older instructions have committed.
        "IsSerializeBefore",
        "IsSerializeAfter",
        "IsWriteBarrier",  # Is a write barrier
        "IsReadBarrier",  # Is a read barrier
        "IsNonSpeculative",  # Should not be executed speculatively
        "IsQuiesce",  # Is a quiesce instruction
        "IsUnverifiable",  # Can't be verified by a checker
        "IsSyscall",  # Causes a system call to be emulated in syscall
        # emulation mode.
        # Flags for microcode
        "IsMacroop",  # Is a macroop containing microops
        "IsMicroop",  # Is a microop
        "IsDelayedCommit",  # This microop doesn't commit right away
        "IsLastMicroop",  # This microop ends a microop sequence
        "IsFirstMicroop",  # This microop begins a microop sequence
        "IsSquashAfter",  # Squash all uncommitted state after executed
        # hardware transactional memory
        "IsHtmStart",  # Starts a HTM transaction
        "IsHtmStop",  # Stops (commits) a HTM transaction
        "IsHtmCancel",  # Explicitely aborts a HTM transaction
    ]