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# Copyright (c) 2016 Advanced Micro Devices, Inc.
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#
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# modification, are permitted provided that the following conditions are met:
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# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
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# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
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# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from this
# software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# POSSIBILITY OF SUCH DAMAGE.
from m5.params import *
class GPUStaticInstFlags(Enum):
wrapper_name = "GPUStaticInstFlags"
wrapper_is_struct = True
enum_name = "Flags"
vals = [
# Op types
"ALU", # ALU op
"Branch", # Branch instruction
"CondBranch", # Conditinal Branch instruction
"Nop", # No-op (no effect at all)
"Return", # Subroutine return instruction
"EndOfKernel", # Kernel termination instruction
"KernelLaunch", # Kernel launch inst
"UnconditionalJump", #
"SpecialOp", # Special op
"Waitcnt", # Is a waitcnt instruction
"Sleep", # Is a sleep instruction
# Memory ops
"MemBarrier", # Barrier instruction
"MemSync", # Synchronizing instruction
"MemoryRef", # References memory (load, store, or atomic)
"Flat", # Flat memory op
"FlatGlobal", # Global memory op
"Load", # Reads from memory
"Store", # Writes to memory
# Atomic ops
"AtomicReturn", # Atomic instruction that returns data
"AtomicNoReturn", # Atomic instruction that doesn't return data
# Instruction attributes
"Scalar", # A scalar (not vector) operation
"ReadsSCC", # The instruction reads SCC
"WritesSCC", # The instruction writes SCC
"ReadsVCC", # The instruction reads VCC
"WritesVCC", # The instruction writes VCC
"ReadsEXEC", # The instruction reads Exec Mask
"WritesEXEC", # The instruction writes Exec Mask
"ReadsMode", # The instruction reads Mode register
"WritesMode", # The instruction writes Mode register
"IgnoreExec", # The instruction ignores the Exec Mask
"IsSDWA", # The instruction is a SDWA instruction
"IsDPP", # The instruction is a DPP instruction
# Atomic OP types
"AtomicAnd",
"AtomicOr",
"AtomicXor",
"AtomicCAS",
"AtomicExch",
"AtomicAdd",
"AtomicSub",
"AtomicInc",
"AtomicDec",
"AtomicMax",
"AtomicMin",
# Segment access flags
"ArgSegment", # Accesses the arg segment
"GlobalSegment", # Accesses global memory
"GroupSegment", # Accesses local memory (LDS), aka shared memory
"KernArgSegment", # Accesses the kernel argument segment
"PrivateSegment", # Accesses the private segment
"ReadOnlySegment", # Accesses read only memory
"SpillSegment", # Accesses the spill segment
"NoSegment", # Does not have an associated segment
# Coherence flags
"GloballyCoherent", # Coherent with other work-items on same device
"SystemCoherent", # Coherent with a different device, or the host
# Floating-point flags
"F16", # F16 operation
"F32", # F32 operation
"F64", # F64 operation
# MAC, MAD, FMA
"FMA", # FMA
"MAC", # MAC
"MAD", # MAD
]