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from m5.SimObject import *
from m5.params import *
from m5.proxy import *

from m5.objects.Tlm import TlmTargetSocket
from m5.objects.AbstractMemory import *


class DRAMSys(AbstractMemory):
    type = "DRAMSys"
    cxx_class = "gem5::memory::DRAMSys"
    cxx_header = "mem/dramsys.hh"
    tlm = TlmTargetSocket(32, "TLM target port")

    configuration = Param.String("Path to the DRAMSys configuration")
    resource_directory = Param.String("Path to the DRAMSys resource directory")
    recordable = Param.Bool(True, "Whether DRAMSys should record a trace file")