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# Copyright (c) 2013 Amin Farmahini-Farahani
# Copyright (c) 2015 University of Kaiserslautern
# Copyright (c) 2015 The University of Bologna
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from m5.params import *
from m5.proxy import *
from m5.objects.QoSMemCtrl import *

# Enum for memory scheduling algorithms, currently First-Come
# First-Served and a First-Row Hit then First-Come First-Served
class MemSched(Enum):
    vals = ["fcfs", "frfcfs"]


# MemCtrl is a single-channel single-ported Memory controller model
# that aims to model the most important system-level performance
# effects of a memory controller, interfacing with media specific
# interfaces
class MemCtrl(QoSMemCtrl):
    type = "MemCtrl"
    cxx_header = "mem/mem_ctrl.hh"
    cxx_class = "gem5::memory::MemCtrl"

    # single-ported on the system interface side, instantiate with a
    # bus in front of the controller for multiple ports
    port = ResponsePort("This port responds to memory requests")

    # Interface to memory media
    dram = Param.MemInterface(
        "Memory interface, can be a DRAMor an NVM interface "
    )

    # read and write buffer depths are set in the interface
    # the controller will read these values when instantiated

    # threshold in percent for when to forcefully trigger writes and
    # start emptying the write buffer
    write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")

    # threshold in percentage for when to start writes if the read
    # queue is empty
    write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")

    # minimum write bursts to schedule before switching back to reads
    min_writes_per_switch = Param.Unsigned(
        16, "Minimum write bursts before switching to reads"
    )

    # minimum read bursts to schedule before switching back to writes
    min_reads_per_switch = Param.Unsigned(
        16, "Minimum read bursts before switching to writes"
    )

    # scheduler, address map and page policy
    mem_sched_policy = Param.MemSched("frfcfs", "Memory scheduling policy")

    # pipeline latency of the controller and PHY, split into a
    # frontend part and a backend part, with reads and writes serviced
    # by the queues only seeing the frontend contribution, and reads
    # serviced by the memory seeing the sum of the two
    static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
    static_backend_latency = Param.Latency("10ns", "Static backend latency")

    command_window = Param.Latency("10ns", "Static backend latency")
    disable_sanity_check = Param.Bool(False, "Disable port resp Q size check")