# Copyright (c) 2006-2007 The Regents of The University of Michigan
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import m5
from m5.objects import *

nb_cores = 4
cpus = [AtomicSimpleCPU(cpu_id=i) for i in range(nb_cores)]

import ruby_config

ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)

# system simulated
system = System(
    cpu=cpus,
    physmem=ruby_memory,
    membus=SystemXBar(),
    clk_domain=SrcClockDomain(clock="1GHz"),
)

# Create a seperate clock domain for components that should run at
# CPUs frequency
system.cpu.clk_domain = SrcClockDomain(clock="2GHz")

# add L1 caches
for cpu in cpus:
    cpu.connectBus(system.membus)
    # All cpus are associated with cpu_clk_domain
    cpu.clk_domain = system.cpu_clk_domain

# connect memory to membus
system.physmem.port = system.membus.mem_side_ports

# Connect the system port for loading of binaries etc
system.system_port = system.membus.cpu_side_ports

# -----------------------
# run simulation
# -----------------------

root = Root(full_system=False, system=system)
root.system.mem_mode = "atomic"