tree 84a36fc49ac6cd9ec612d4e6aa676ef0c5aab114
parent 7cdf8c00f891628f82a50945a5598d44f20c0ed5
author Giacomo Travaglini <giacomo.travaglini@arm.com> 1611766652 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> 1616619089 +0000

system: Fix PCI Mem range for VExpress_GEM5_VX DTS

This is addressing an issue raised in the mailing list [1]
where setting up a PCI mem bar for an ethernet device
resulted into an overlap of memory ranges:

fatal: system.iobus has two ports responding within range
[0x80000000:0x80020000]:
        system.realview.ethernet.pio
        system.iobridge.cpu_side_port

The reason for this is the following:

The PCI mem range in the DTB is using 0x40000000 (3rd word) as a
starting address in the PCI domain, which is linked to 0x40000000 in the
host domain.

<0x02000000 0x0 0x40000000  0x0 0x40000000  0x0 0x40000000>;

However the current mapping scheme works with simple fixed translation
So address 0x40000000 in the PCI domain will be mapped to 0x40000000 +
0x40000000 = 0x80000000, which is where DRAM starts

This is aligning with DTB autogeneration, which is setting up a
PCI mem range starting at PCI address = 0 [2]

[1]: https://www.mail-archive.com/gem5-users@gem5.org/msg18941.html
[2]: https://github.com/gem5/gem5/blob/v20.1.0.0/src/dev/arm/RealView.py#L161

Change-Id: I4538511453cfd5143fb4613a080780dc86b2244c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39915
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>