)]}' { "log": [ { "commit": "af72b9ba580546ac12ce05bfaac3fd53fa8699f4", "tree": "0526a54b749ec0ab15c3196e9579093dba639170", "parents": [ "587159069a1127e0f0d93df8229f993dce7a0937" ], "author": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Mon Jul 10 14:13:09 2023 -0700" }, "committer": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Mon Jul 10 14:14:22 2023 -0700" }, "message": "misc: Update RELEASE-NOTES.md for v23.0.0.1 hotfix\n\nChange-Id: Ieced7f693a8cbef586324dfe7ce826da16d9a3c3\n" }, { "commit": "587159069a1127e0f0d93df8229f993dce7a0937", "tree": "423bfa0cc934749f3d2cef10c9598c2be9d68daf", "parents": [ "556955b7c9e8b4ce6e8d289244b69efd1641adb2" ], "author": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Mon Jul 10 14:08:27 2023 -0700" }, "committer": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Mon Jul 10 14:08:27 2023 -0700" }, "message": "misc: Update version to v23.0.0.1\n\nChange-Id: I3bbcfd4dd9798149b37d4a2824fe63652e29786c\n" }, { "commit": "556955b7c9e8b4ce6e8d289244b69efd1641adb2", "tree": "69b334848d454fb8084117bf1f85b2e81dc7a3cf", "parents": [ "8295e84360a9cdab034b8d5f78fdf0826d5510c2" ], "author": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Mon Jul 10 13:42:47 2023 -0700" }, "committer": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Mon Jul 10 13:42:47 2023 -0700" }, "message": "gpu-compute: Add missing include in dispatcher.cc\n\nDue to some cherry-picking onto the release-staging branch, there was a\nmissing \"sim/sim_exit.hh\" include in \"src/gpu-compute/dispatcher.cc\".\nThis was causing compilation errors.\n\nThis is being added to the v23.0.0 release as a hotfix.\n\nChange-Id: I1043ecf5c41ad6afc0e91311b196f4801646002f\nIssue-on: https://gem5.atlassian.net/browse/GEM5-1332\n" }, { "commit": "8295e84360a9cdab034b8d5f78fdf0826d5510c2", "tree": "9ee8c8f66699f9a451d81e057d1b1cdf93880499", "parents": [ "dd7780c0b250747cb98db41e76bbd7ebd184e7ff" ], "author": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Tue May 09 15:39:23 2023 -0700" }, "committer": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Mon Jul 10 13:39:52 2023 -0700" }, "message": "dev: Fix Linux specific includes to be portable\n\nThis allows for compilation in non-linux systems (e.g., Mac OS).\n\nChange-Id: Ib6c9406baf42db8caaad335ebc670c1905584ea2\n" }, { "commit": "dd7780c0b250747cb98db41e76bbd7ebd184e7ff", "tree": "2f365ec1511503a713e153fa05ddebb3ee9b9143", "parents": [ "fbaa164b6a7275760066b62fb863501c67dd2ffe" ], "author": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Tue May 09 15:30:45 2023 -0700" }, "committer": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Mon Jul 10 13:39:52 2023 -0700" }, "message": "dev-amdgpu: Add missing \u0027overrides\u0027\n\nThis causes warnings/errors in some compilers.\n\nChange-Id: I36a3548943c030d2578c2f581c8985c12eaeb0ae\n" }, { "commit": "fbaa164b6a7275760066b62fb863501c67dd2ffe", "tree": "f93d995027c6a3e59e9c9f07e3e34796f3eafd96", "parents": [ "1db206b9d371b14cb9150e37aef444d1d59db025" ], "author": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Tue May 09 15:30:11 2023 -0700" }, "committer": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Mon Jul 10 13:39:52 2023 -0700" }, "message": "gpu-compute: Remove use of \u0027std::random_shuffle\u0027\n\nThis was deprecated in C++14 and removed in C++17. This has been\nreplaced with std::random. This has been implemented to ensure\nreproducible results despite (pseudo)random behavior.\n\nChange-Id: Idd52bc997547c7f8c1be88f6130adff8a37b4116\n" }, { "commit": "1db206b9d371b14cb9150e37aef444d1d59db025", "tree": "380bf659950b7caf6b5489978410212f973a6346", "parents": [ "e03395b386672d56d8b03f0acaf7cb6d282c9a67", "20ee3b97622be2cc448de31d84dd5f29109e0ada" ], "author": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Fri Jul 07 19:25:10 2023 -0700" }, "committer": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Fri Jul 07 19:25:10 2023 -0700" }, "message": "misc: Merge branch \u0027release-staging-v23-0\u0027 into stable\n\nChange-Id: Ie2012ea0ae86401181cf02de3e22401e406a18e6\n" }, { "commit": "20ee3b97622be2cc448de31d84dd5f29109e0ada", "tree": "da4ff3f693f4b3f8f52917d77e65c656b73bce5a", "parents": [ "e377e15c07e439b696a4a09b0179fd4553d11d0a" ], "author": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Fri Jul 07 18:21:44 2023 -0700" }, "committer": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Fri Jul 07 18:21:44 2023 -0700" }, "message": "stdlib: Remove simulator.py beta warnings\n\nThis component is no longer in a beta state\n\nChange-Id: I8e309771aaa03197cf1738ad0af57c253ad58ecd\n" }, { "commit": "e377e15c07e439b696a4a09b0179fd4553d11d0a", "tree": "a0adf02eac2ca34b9998f50c2762d19644b70593", "parents": [ "387fc6964e27d085acaf15628045734875b7a0eb" ], "author": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Thu Jun 15 16:08:49 2023 -0700" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Sat Jul 08 00:31:31 2023 +0000" }, "message": "misc: Update gem5 version to v23.0.0.0\n\nChange-Id: Ie14b35a62a152e3d78b16bcd4c92ec9a790f1396\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71724\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\n" }, { "commit": "387fc6964e27d085acaf15628045734875b7a0eb", "tree": "8139225930483424a23e4719d9aefba5a965028f", "parents": [ "578eaead472f6bceea3876cbc85a0120a6055c9b" ], "author": { "name": "Matthew Poremba", "email": "matthew.poremba@amd.com", "time": "Thu Jul 06 08:13:01 2023 -0700" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Fri Jul 07 21:22:45 2023 +0000" }, "message": "gpu-compute,configs: Make sim exits conditional\n\nThe unconditional exit event when a kernel completes that was added in\nc644eae2ddd34cf449a9c4476730bd29703c4dd7 is causing scripts that do not\nignore unknown exit events to end simulation prematurely. One such\nscript is the apu_se.py script used in SE mode GPU simulation. Make this\nexit conditional to the parameter being set to a valid value to avoid\nthis problem.\n\nChange-Id: I1d2c082291fdbcf27390913ffdffb963ec8080dd\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/72098\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nMaintainer: Matt Sinclair \u003cmattdsinclair@gmail.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nReviewed-by: Matt Sinclair \u003cmattdsinclair@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n(cherry picked from commit 3756af8ed91f0860dcfb0a7111478212980e37ae)\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/72138\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\n" }, { "commit": "578eaead472f6bceea3876cbc85a0120a6055c9b", "tree": "bfc59b1eb39ae162a35ab1f803409da9c111e1ac", "parents": [ "6c997b633fb5759bd45ff947626c5228e2c67539" ], "author": { "name": "Matthew Poremba", "email": "matthew.poremba@amd.com", "time": "Wed Jun 28 14:49:48 2023 -0500" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Fri Jul 07 21:22:30 2023 +0000" }, "message": "dev-amdgpu: Perform frame writes atomically\n\nThe PCI read/write functions are atomic functions in gem5, meaning they\nexpect a response with a latency value on the same simulation Tick. For\nreads to a PCI device, the response must also include a data value read\nfrom the device.\n\nThe AMDGPU device has a PCI BAR which mirrors the frame buffer memory.\nCurrently reads are done atomically, but writes are sent to a DMA device\nwithout waiting for a write completion ACK. As a result, it is possible\nthat writes can be queued in the DMA device long enough that another\nread for a queued address arrives. This happens very deterministically\nwith the AtomicSimpleCPU and causes GPUFS to break with that CPU.\n\nThis change makes writes to the frame BAR atomic the same as reads. This\navoids that problem and as a result the AtomicSimpleCPU can now load the\ndriver for GPUFS simulations.\n\nChange-Id: I9a8e8b172712c78b667ebcec81a0c5d0060234db\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71898\nMaintainer: Matt Sinclair \u003cmattdsinclair@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Matt Sinclair \u003cmattdsinclair@gmail.com\u003e\nMaintainer: Matthew Poremba \u003cmatthew.poremba@amd.com\u003e\nReviewed-by: Matthew Poremba \u003cmatthew.poremba@amd.com\u003e\n(cherry picked from commit 079fc47dc202ffe7c77e1e94bb1d5e0ee38d1816)\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/72079\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\n" }, { "commit": "6c997b633fb5759bd45ff947626c5228e2c67539", "tree": "20fe0d923c55e87f97b90dec69bfdb59e2997c13", "parents": [ "8d1722478160edc64f5069efccfaf2aaa8213208" ], "author": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Fri Jul 07 08:46:16 2023 -0700" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Fri Jul 07 21:22:26 2023 +0000" }, "message": "scons: Remove -Werror for the gem5 v23.0 release\n\nWhile gem5 compiles on all our supported compilers, removing the -Werror\nflag on the stable branch ensures that, as new compilers are released\nwith stricter warnings, gem5 remains compilable.\n\nChange-Id: Ie32a5c526a17cc584bce3b71d27b8f052caf612b\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/72178\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "8d1722478160edc64f5069efccfaf2aaa8213208", "tree": "de347a4e81949a9a309c532987698a630f635b05", "parents": [ "818c2d15a229ef87e310a1dd1180980787fff3cc" ], "author": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Mon Jul 03 13:03:05 2023 -0700" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Fri Jul 07 21:22:22 2023 +0000" }, "message": "stdlib,tests: Fix download_check.py\n\nThis was causing the Weekly tests to fail. The removing of the download\ndirectory should only happen at the end. Prior to this patch it was\ndeleted and then referenced, which caused problems.\n\nChange-Id: I134782e89a13f5c3cd5c1912ad53a701d0413d16\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/72159\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "818c2d15a229ef87e310a1dd1180980787fff3cc", "tree": "2c6599540fc16abf47dbbee79d411f61b064f573", "parents": [ "4cf6695bc7bceb1505625380f0519b5a361378eb" ], "author": { "name": "Matthew Poremba", "email": "matthew.poremba@amd.com", "time": "Thu Jun 29 16:48:48 2023 -0700" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Fri Jul 07 21:22:02 2023 +0000" }, "message": "configs: Create base GPUFS vega config and atomic config\n\nMove the Vega KVM script code to a common base file and add scripts for\nKVM and atomic. Since atomic is now possible in GPUFS this gives a way\nto run it without editing the current scripts.\n\nChange-Id: I094bc4d4df856563535c28c1f6d6cc045d6734cd\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71939\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Matt Sinclair \u003cmattdsinclair@gmail.com\u003e\nMaintainer: Matt Sinclair \u003cmattdsinclair@gmail.com\u003e\n(cherry picked from commit 05ffa354268301821518fd430d069cd23049527d)\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/72078\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\n" }, { "commit": "4cf6695bc7bceb1505625380f0519b5a361378eb", "tree": "fd0087848a3809833297dd092751bca5384b598a", "parents": [ "04b4a4705a2c0bb937172169e3634e1b3352c779" ], "author": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Sun Jun 18 14:58:24 2023 -0400" }, "committer": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Fri Jul 07 13:05:51 2023 -0700" }, "message": "misc: Add release notes for v23.0\n\nChange-Id: I003f170339e69a445586fe0486a1db595a10683f\nSigned-off-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n" }, { "commit": "04b4a4705a2c0bb937172169e3634e1b3352c779", "tree": "5533391c73ac61d789ea2cdf2d15cf94464dd66d", "parents": [ "d54b8f8475495213f5c2e69aadd7886c69bcd53c" ], "author": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Mon Jul 03 10:03:57 2023 -0700" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Fri Jul 07 19:51:59 2023 +0000" }, "message": "stdlib: Change default gem5-resources DB collection\n\nThis was set to \"test_collection\", which was used during development.\nChanging to \"resources\".\n\nChange-Id: I52c83c6b73f3a227fbb05dc321a4bc38210ad71c\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/72158\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\n" }, { "commit": "e03395b386672d56d8b03f0acaf7cb6d282c9a67", "tree": "a94534683160a1dc72fdb264acdf12247018f5e4", "parents": [ "b271367a357cbb390084884e809235d6d62b9cf5" ], "author": { "name": "Melissa Jost", "email": "melissakjost@gmail.com", "time": "Thu Jul 06 16:16:12 2023 -0700" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Fri Jul 07 14:44:51 2023 +0000" }, "message": "misc: Check for Change-Id in GitHub Actions\n\nThis adds a check to our continous integration tests that ensures\nthat every single commit in a pull request has a Change-Id, and\ninstructs you to add one if that check fails. This ensures all\ncommits on GitHub are still compatible with Gerrit.\n\nChange-Id: I3fd753da5ab3ca6d6334a8e0eb574433aa1ca589\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/72118\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\n" }, { "commit": "b271367a357cbb390084884e809235d6d62b9cf5", "tree": "a394f32f90d5eecf3e0397e109c50b80e91318e0", "parents": [ "55cecfc3e8fb2bdddfd96a850b0fdaca9bcdd0b3" ], "author": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Tue Jun 27 09:25:31 2023 -0700" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Tue Jun 27 21:18:26 2023 +0000" }, "message": "misc: Adjust compiler tests and CI tests\n\nThis adds a job level timeout for the compiler tests, allows\nthem to run weekly instead of daily, adds a workflow\ndispatch option, and changes the\n\u0027latests-compilers-all-gem5-builds\u0027 jobs to run only the .opt\nvariant. It also adds a ready for review option\nto the CI tests to run when someone converts a draft\npull request.\n\nChange-Id: Id32b5f7da90745d18de2e550bd48d32ba45fb4d9\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71725\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "d54b8f8475495213f5c2e69aadd7886c69bcd53c", "tree": "c6135a407d0cc01b84944e368c083b7b51335347", "parents": [ "b182b15f93621206c87c6c760cdfc1f5df1877cf" ], "author": { "name": "Adrià Armejach", "email": "adria.armejach@bsc.es", "time": "Wed Jun 07 17:01:03 2023 +0200" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Fri Jun 16 16:44:49 2023 +0000" }, "message": "arch-riscv: fix load reserved store conditional\n\n * According to the manual, load reservations must be cleared on a\n failed or a successful SC attempt.\n * A load reservation can be arbitrarily large. The current\n implementation was reserving something different than cacheBlockSize\n which could lead to problems if snoop addresses are cache block\n aligned. This patch implementation assumes a cacheBlock granularity.\n * Load reservations should also be cleared on faults\n\nChange-Id: I64513534710b5f269260fcb204f717801913e2f5\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71520\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\n" }, { "commit": "b182b15f93621206c87c6c760cdfc1f5df1877cf", "tree": "cd4efff00f7e5f7add646f5f2bc4ea1a9cff871f", "parents": [ "a63d376ecd4debd60f89fa2e0592dac6f9addae2" ], "author": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Tue Jun 13 18:14:38 2023 -0700" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Thu Jun 15 20:14:55 2023 +0000" }, "message": "scons,stdlib: Remove deprecated \u0027distutils\u0027 module\n\nThe Python module \u0027distutils\u0027 will be removed in Python 3.12:\nhttps://docs.python.org/3/library/distutils.html\n\nThis patch removed usage of \u0027distutils\u0027 in the gem5 code base.\n\nChange-Id: I1e3a944446149f3cd6cbf4211a1565b5f74c85a0\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71679\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\n" }, { "commit": "a63d376ecd4debd60f89fa2e0592dac6f9addae2", "tree": "182611dd0d6606c726c29020b98a442de11e815d", "parents": [ "82587ce71bbbdc80d3ef6386e07c892f309697a3" ], "author": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Tue Jun 13 17:42:23 2023 -0700" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Thu Jun 15 20:14:55 2023 +0000" }, "message": "python: Remove Python \u0027pipes\u0027 module\n\nThis is scheduled for removal from Python in 3.13:\nhttps://docs.python.org/3/library/pipes.html.\n\nThe \u0027shlex.quote\u0027 function can replace the \u0027pipes.quote\u0027 function used\nin \"main.py\". A special wrapper has been made to account for the Windows\ncase which \u0027shlex.quote\u0027 doesn\u0027t handle.\n\nChange-Id: I9c84605f0ccd8468b9cab6cece6248ef8c2107f0\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71678\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\n" }, { "commit": "82587ce71bbbdc80d3ef6386e07c892f309697a3", "tree": "e30cfe6d33e166d1a325e1e118666f71ca355ff1", "parents": [ "328aaa626fbbc3d664086b6dd4bde11bd71f9d5d" ], "author": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Mon Jun 12 14:09:15 2023 -0700" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Thu Jun 15 20:14:55 2023 +0000" }, "message": "stdlib: Refactor gem5 Vision/gem5-resources code\n\nThis patch includes several changes to the gem5 tools interface to the\ngem5-resources infrastructure. These are:\n\n* The old download and JSON query functions have been removed from the\n downloader module. These functions were used for directly downloading\n and inspecting the resource JSON file, hosted at\n https://resources.gem5.org/resources. This information is now obtained\n via `gem5.client`. If a resources JSON file is specified as a client,\n it should conform to the new schema:\n https//resources.gem5.org/gem5-resources-schema.json. The old schema\n (pre-v23.0) is no longer valid. Tests have been updated to reflect\n this change. Those which tested these old functions have been removed.\n* Unused imports have been removed.\n* For the resource query functions, and those tasked with obtaining the\n resources, the parameter `gem5_version` has been added. In all cases\n it does the same thing:\n * It will filter results based on compatibility to the\n `gem5_version` specified. If no resources are compatible the\n latest version of that resource is chosen (though a warning is\n thrown).\n * By default it is set to the current gem5 version.\n * It is optional. If `None`, this filtering functionality is not\n carried out.\n * Tests have been updated to fix the version to “develop” so the\n they do not break between versions.\n* The `gem5_version` parameters will filter using a logic which will\n base compatibility on the specificity of the gem5-version specified in\n a resource’s data. If a resource has a compatible gem5-version of\n “v18.4” it will be compatible with any minor/hotfix version within the\n v18.4 release (this can be seen as matching on “v18.4.*.*”.) Likewise,\n if a resource has a compatible gem5-version of “v18.4.1” then it’s\n only compatible with the v18.4.1 release but any of it’s hot fix\n releases (“v18.4.1.*”).\n* The ‘list_resources’ function has been updated to use the\n “gem5.client” APIs to get resource information from the clients\n (MongoDB or a JSON file). This has been designed to remain backwards\n compatible to as much as is possible, though, due to schema changes,\n the function does search across all versions of gem5.\n* `get_resources` function was added to the `AbstractClient`. This is a\n more general function than `get_resource_by_id`. It was\n primarily created to handle the `list_resources` update but is a\n useful update to the API. The `get_resource_by_id` function has been\n altered to function as a wrapped to the `get_resources` function.\n* Removed “GEM5_RESOURCE_JSON” code has been removed. This is no longer\n used.\n* Tests have been cleaned up a little bit to be easier to read.\n* Some docstrings have been updated.\n\nThings that are left TODO with this code:\n\n* The client_wrapper/client/abstract_client abstractions are rather\n pointless. In particular the client_wrapper and client classes could\n be merged.\n* The downloader module no longer does much and should have its\n functions merged into other modules.\n* With the addition of the `get_resources` function, much of the code in\n the `AbstractClient` could be simplified.\n\nChange-Id: I0ce48e88b93a2b9db53d4749861fa0b5f9472053\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71506\nReviewed-by: Kunal Pai \u003ckunpai@ucdavis.edu\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "328aaa626fbbc3d664086b6dd4bde11bd71f9d5d", "tree": "5a04b0e5ed8e94e3f93d776ea9e82e71d1a1680e", "parents": [ "f4559a703f16d98c9142bba6c51bc9d85ad684ec" ], "author": { "name": "Roger Chang", "email": "rogerycchang@google.com", "time": "Tue Jun 13 17:25:47 2023 +0800" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Thu Jun 15 20:10:04 2023 +0000" }, "message": "arch-riscv: Fix unexpected behavior of float operations in Mac OS\n\nThe uint_fast16_t is the integer at least 16 bits size, it can be\n32, 64 bits and more. Usually most of the simulations are in the\nx86-64 linux host, the size of uint_fast16_t is 64 bits. Therefore,\nthere is no problem for double precision float operations and it can\npass FloatMM test. However, in the Mac OS, the size of uint_fast16_t\nis 16 bits, it will lose the upper bits when converting float\nregister bits to freg_t and it will generate unexpected results for\nFloatMM test.\n\nThe change can guarantee that the size of data in freg_t is at least\n64 bits and it will not lose any data from floating point to freg_t.\n\nReference:\nhttps://developer.apple.com/documentation/kernel/uint_fast16_t\n\nhttps://codebrowser.dev/glibc/glibc/stdlib/stdint.h.html\n\nChange-Id: I3df6610f0903cdee0f56584d6cbdb51ac26c86c8\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71519\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\n" }, { "commit": "f4559a703f16d98c9142bba6c51bc9d85ad684ec", "tree": "2917afa3039197806f6b4717198d95367bd0a8d9", "parents": [ "d89ba08eb031dff1704261441a4eb21104ca7694" ], "author": { "name": "Ayaz Akram", "email": "yazakram@ucdavis.edu", "time": "Wed Jun 14 11:03:33 2023 -0700" }, "committer": { "name": "Ayaz Akram", "email": "yazakram@ucdavis.edu", "time": "Wed Jun 14 23:16:10 2023 +0000" }, "message": "configs: Fix SPEC benchmarks example scripts\n\nThis small change fixes the gem5_library example\nscripts for SPEC benchmarks to make them compatible\nwith the latest version of the std library.\n\nChange-Id: I3da9745f0ee6b253871e32082e135e0fa4040108\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71718\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\n" }, { "commit": "d89ba08eb031dff1704261441a4eb21104ca7694", "tree": "c22ef8f6dba4f3c765e657b224a1a8be44573f25", "parents": [ "f78471fb81db40c836b89a015a61b8311b4b98fd" ], "author": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Mon Jun 12 15:31:04 2023 -0700" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Tue Jun 13 19:29:43 2023 +0000" }, "message": "python: Ignore -s as gem5 option\n\nThis enables more compatibility with the normal python binary. This is\nneeded to get multiprocessing to work on some systems.\n\nChange-Id: Ibb946136d153979bf54a773060010a0ae479a9d1\nSigned-off-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71518\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "55cecfc3e8fb2bdddfd96a850b0fdaca9bcdd0b3", "tree": "9b1c1098c8da7523a25340e42b4380c3ea1cfa70", "parents": [ "20245469517e2aab6bb450598b5fd530329e60a3" ], "author": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Mon Jun 12 21:00:28 2023 -0700" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Tue Jun 13 17:49:30 2023 +0000" }, "message": "misc: Remove \u0027run-name\u0027 from workflow yaml files\n\nThis field is not necessary and was not a helpful description of the\nrun.\n\nChange-Id: I078481920833fb36099e6c30295c0b60ac0ee3a0\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71505\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\n" }, { "commit": "20245469517e2aab6bb450598b5fd530329e60a3", "tree": "72b2d4dcacc90ae75919ce5227ae16ab36dc451f", "parents": [ "5ca9541037378c230cbc5c15b7e1f90e77cfed5c" ], "author": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Mon Jun 12 20:50:36 2023 -0700" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Tue Jun 13 17:49:30 2023 +0000" }, "message": "misc: Update GitHub Actions Workflow names\n\nChange-Id: Iaf4cbdf7a8edd2b9ae00308ae41f6fa805ab9446\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71504\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\n" }, { "commit": "5ca9541037378c230cbc5c15b7e1f90e77cfed5c", "tree": "9c4d6c6ef8eaf917b2eabca1c6bd35cc32a8f99f", "parents": [ "9c1603119c9e48ded2d63d46fb2a9d3fcfb53910" ], "author": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Mon Jun 12 20:47:47 2023 -0700" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Tue Jun 13 17:49:30 2023 +0000" }, "message": "misc: Add \u0027synchronize\u0027 as CI Test action. Remove \u0027reopen\u0027\n\n\u0027synchronize\u0027 will re-run the tests everytime the pull-request is\nupdated, inclusive of rebasing. \u0027reopen\u0027 seems pointless as reopening\ndoes not change the pull-request functionality.\n\nChange-Id: I24c2686e19a8b0901323e9bd794142994dc2a87c\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71503\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "9c1603119c9e48ded2d63d46fb2a9d3fcfb53910", "tree": "b781e2a9c058f0170d5a4351dbe7e4874db2363a", "parents": [ "2e2f869901f3447bc39c687e8c16e18ed798b196" ], "author": { "name": "Melissa Jost", "email": "melissakjost@gmail.com", "time": "Mon Jun 12 14:37:51 2023 -0700" }, "committer": { "name": "Melissa Jost", "email": "mkjost@ucdavis.edu", "time": "Tue Jun 13 02:18:13 2023 +0000" }, "message": "misc: Increase timeout for GitHub Actions\n\nThis increases the timeout for our compiler tests, and for\nthe very-long runs in our weekly tests.\n\nChange-Id: I027d2e98ce5596430ffcb20ef484e1cd7d4f644b\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71501\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\n" }, { "commit": "2e2f869901f3447bc39c687e8c16e18ed798b196", "tree": "1c6d9caa696e2f67d8339030b1ce6e3d225db448", "parents": [ "cc564c8931d31eda9a9baf19d11cafc7138127b1" ], "author": { "name": "Melissa Jost", "email": "melissakjost@gmail.com", "time": "Fri Jun 09 15:54:32 2023 -0700" }, "committer": { "name": "Melissa Jost", "email": "mkjost@ucdavis.edu", "time": "Sat Jun 10 05:57:57 2023 +0000" }, "message": "misc: Adjust timeout for compiler tests\n\nThis updates the timeout for the compiler tests to run per step\nas opposed to by job, as well as increases this limit from\n4 hours to 6 hours.\n\nChange-Id: I6b0fe5561f74e450cd79205a96084dd27ccccead\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71458\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "f78471fb81db40c836b89a015a61b8311b4b98fd", "tree": "7ce58f283ac73ebf6622598cb77eb5d38af516c2", "parents": [ "1ae409d627f8dc1945bb28ece10747f4744b1b9c" ], "author": { "name": "Mahyar Samani", "email": "msamani@ucdavis.edu", "time": "Thu Jun 08 14:56:50 2023 -0700" }, "committer": { "name": "Mahyar Samani", "email": "msamani@ucdavis.edu", "time": "Fri Jun 09 03:40:11 2023 +0000" }, "message": "tests: Reducing json stat dump size.\n\nThis change reduces the number of stats dumped as json in\ntraffic_gen tests.\n\nChange-Id: I94becb2e6d5da6096271cf7893ff2b380314da06\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71402\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "cc564c8931d31eda9a9baf19d11cafc7138127b1", "tree": "36b0bcf69eba7af58efdc9ea3f7919df57b30a81", "parents": [ "27492d9d1854f1fb80bd91e3f69659cad08ffd70" ], "author": { "name": "Melissa Jost", "email": "melissakjost@gmail.com", "time": "Thu Jun 08 14:25:06 2023 -0700" }, "committer": { "name": "Melissa Jost", "email": "mkjost@ucdavis.edu", "time": "Fri Jun 09 02:18:48 2023 +0000" }, "message": "misc: Add weekly tests to Github workflows\n\nThis introduces the very-long tests from our weekly tests to be\nable to run within GitHub.\n\nChange-Id: I5f5b4c521b47272cb27640c572a869c26c04b95a\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71401\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "27492d9d1854f1fb80bd91e3f69659cad08ffd70", "tree": "f76d9e7def67cb7c8c58f3a5dc8cfe34cc969c07", "parents": [ "ad0a2d1beaa043c03c0e43406078b3a09a3861ac" ], "author": { "name": "Melissa Jost", "email": "melissakjost@gmail.com", "time": "Thu Jun 08 14:23:11 2023 -0700" }, "committer": { "name": "Melissa Jost", "email": "mkjost@ucdavis.edu", "time": "Fri Jun 09 02:18:41 2023 +0000" }, "message": "misc: Update GitHub yaml files\n\nThis introduces a few fixes to the yaml files, such as fixing\nthe failing SystemC tests by removing an extra Docker container,\ndeclaring the Python version for our compiler tests, fixing\ntypos in the GPU daily tests, and adjusting the timeout values\nfor our compiler tests and unittests.\n\nChange-Id: I3b4f2220750138783717b3678b0d8676155cb2a1\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71400\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nMaintainer: Matt Sinclair \u003cmattdsinclair@gmail.com\u003e\nReviewed-by: Matt Sinclair \u003cmattdsinclair@gmail.com\u003e\n" }, { "commit": "1ae409d627f8dc1945bb28ece10747f4744b1b9c", "tree": "97c11cbc3c19df20a8f8167276961cda31979cfb", "parents": [ "d33c41118b1636b55a5aadb34e5724c9be673896" ], "author": { "name": "Roger Chang", "email": "rogerycchang@google.com", "time": "Sat Jun 03 10:30:38 2023 +0800" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Fri Jun 09 01:48:02 2023 +0000" }, "message": "stdlib: Add U74VecFU to U74CPU\n\nThis change is to elimilate the warning message from U74CPU.\n\nChange-Id: I7a5d0cd0b2955e54ed14fc1ac6f7127bd7f0604b\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71238\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71399\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\n" }, { "commit": "d33c41118b1636b55a5aadb34e5724c9be673896", "tree": "bb15ed54ca78442ce144739534d75d48f1c415dc", "parents": [ "8219b1961a66f786588860810135a7e405bd70c8" ], "author": { "name": "Xuan Hu", "email": "huxuan@bosc.ac.cn", "time": "Tue Jan 17 21:08:57 2023 +0800" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Fri Jun 09 01:48:02 2023 +0000" }, "message": "arch-riscv,cpu-minor: Add MinorDefaultVecFU for risc-v v-ext\n\nChange-Id: Id5c5ae5fa1901154cadeb0a4958703f3f15d491f\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67295\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71398\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\n" }, { "commit": "8219b1961a66f786588860810135a7e405bd70c8", "tree": "8ab40e6d5135adf91abce086544592713639f603", "parents": [ "3322127793e1d7fbaa9f28df14a3f5f72fa772f6" ], "author": { "name": "Roger Chang", "email": "rogerycchang@google.com", "time": "Mon Jun 05 14:32:18 2023 +0800" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Thu Jun 08 20:50:32 2023 +0000" }, "message": "scons: Fix grpc protobuf actions\n\nThe change will fix the proto import issue and build issue with\n--no-duplicate-sources options, more details please reference:\nhttps://gem5-review.googlesource.com/c/public/gem5/+/64491.\n\nChange-Id: I259413f7739f89598dcd42c3f2e1e865cec3de43\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71318\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71338\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\n" }, { "commit": "3322127793e1d7fbaa9f28df14a3f5f72fa772f6", "tree": "8928c980bdcc9f414481454d9a24f2d9ca904a91", "parents": [ "4434d4897368b48e464ed70bbdd5a45d1c4a326f" ], "author": { "name": "KUNAL PAI", "email": "kunpai@ucdavis.edu", "time": "Wed Jun 07 15:30:15 2023 -0700" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Thu Jun 08 15:52:56 2023 +0000" }, "message": "tests: Fix bugs related to gem5 Vision\n\nThis patch fixes refs under tests/pyunit/stdlib/resources.\n\nRemoves instances of {url_base} in refs.\n\nAlso, renames two refs: mongo_mock and mongo_dup_mock\nto mongo-mock and mongo-dup-mock to follow naming\nconvention of other refs.\n\nChange-Id: If115114bc7a89764e7c546b77a93d36d6a3b5f8a\nCo-authored-by: Parth Shah \u003chelloparthshah@gmail.com\u003e\nCo-authored-by: Harshil2107 \u003charshilp2107@gmail.com\u003e\nCo-authored-by: aarsli \u003carsli@ucdavis.edu\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71378\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\n" }, { "commit": "4434d4897368b48e464ed70bbdd5a45d1c4a326f", "tree": "a7666d09a204ef22267e4c6f8e989a38ce90d8b2", "parents": [ "70ec55ce2a4ee221fbb15bc2fafd38cee6ff8c65" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Fri Jun 02 09:24:42 2023 +0100" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed Jun 07 07:38:08 2023 +0000" }, "message": "arch-arm: Apply FEAT_IDST to missing ID registers\n\nWhen FEAT_IDST got implemented [1], we forgot to add the\nlogic for AArch64 ID registers tracking AArch32 state/capabilities\n\n[1]: https://gem5-review.googlesource.com/c/public/gem5/+/70723\n\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nChange-Id: I19bddf67ecc379a14f91cfede385692536982101\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71178\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\n" }, { "commit": "70ec55ce2a4ee221fbb15bc2fafd38cee6ff8c65", "tree": "af783f73065e84ed2f7f56827563123d516bce16", "parents": [ "cf2d5b68a91aafb46efd7e59b789b35681dd6ff3" ], "author": { "name": "Kunal Pai", "email": "62979320+kunpai@users.noreply.github.com", "time": "Sun May 21 23:35:40 2023 -0700" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Tue Jun 06 20:20:54 2023 +0000" }, "message": "stdlib, tests, configs: Introduce gem5 Vision to resources\n\nThis patch makes changes to the stdlib based on the gem5 Vision project.\nFirstly, a MongoDB database is supported.\nA JSON database\u0027s support is continued.\nThe JSON can either be a local path or a raw GitHub link.\n\nThe data for these databases is stored in src/python\nunder \"gem5-config.json\".\nThis will be used by default.\nHowever, the configuration can be overridden:\n- by providing a path using the GEM5_CONFIG env variable.\n- by placing a gem5-config.json file in the current working directory.\n\nAn AbstractClient is an abstract class that implements\nsearching and sorting relevant to the databases.\n\nClients is an optional list that can be passed\nwhile defining any Resource class and obtain_resource.\nThese databases can be defined in the config JSON.\n\nResources now have versions. This allows for a\nsingle version, e.g., \u0027x86-ubuntu-boot\u0027, to have\nmultiple versions. As such, the key of a resource is\nits ID and Version (e.g., \u0027x86-ubuntu-boot/v2.1.0\u0027).\nDifferent versions of a resource might be compatible\nwith different versions of gem5.\n\nBy default, it picks the latest version compatible with the gem5 Version\nof the user.\n\nA gem5 resource schema now has additional fields.\nThese are:\n- source_url: Stores URL of GitHub Source of the resource.\n- license: License information of the resource.\n- tags: Words to identify a resource better, like hello for hello-world\n- example_usage: How to use the resource in a simulation.\n- gem5_versions: List of gem5 versions that resource is compatible with.\n- resource_version: The version of the resource itself.\n- size: The download size of the resource, if it exists.\n- code_examples: List of objects.\nThese objects contain the path to where a resource is\nused in gem5 example config scripts,\nand if the resource itself is used in tests or not.\n- category: Category of the resource, as defined by classes in\nsrc/python/gem5/resources/resource.py.\n\nSome fields have been renamed:\n- \"name\" is changed to \"id\"\n- \"documentation\" is changed to \"description\"\n\nBesides these, the schema also supports resource specialization.\nIt adds fields relevant to a specific resource as specified in\nsrc/python/gem5/resources/resource.py\nThese changes have been made to better present\ninformation on the new gem5 Resources website.\n\nBut, they do not affect the way resources are used by a gem5 user.\nThis patch is also backwards compatible.\nExisting code doesn\u0027t break with this new infrastructure.\n\nAlso, refs in the tests have been changed to match this new schema.\nTests have been changed to work with the two clients.\n\nChange-Id: Ia9bf47f7900763827fd5e873bcd663cc3ecdba40\nCo-authored-by: Kunal Pai \u003ckunpai@ucdavis.edu\u003e\nCo-authored-by: Parth Shah \u003chelloparthshah@gmail.com\u003e\nCo-authored-by: Harshil Patel \u003charshilp2107@gmail.com\u003e\nCo-authored-by: aarsli \u003carsli@ucdavis.edu\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71278\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\n" }, { "commit": "ad0a2d1beaa043c03c0e43406078b3a09a3861ac", "tree": "5b15ac4a1c2d9a78667d297fc93507d41556f11d", "parents": [ "5fa484e2e02604ad3a5bf01f35ad1f97ca6d17b8" ], "author": { "name": "Melissa Jost", "email": "melissakjost@gmail.com", "time": "Mon Jun 05 16:40:16 2023 -0700" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Tue Jun 06 13:36:26 2023 +0000" }, "message": "misc: Adding GitHub workflow files\n\nThis changes adds all of the workflows that will be run as we\nmove to using GitHub. It includes our compiler tests, our\nnightly runs, and the continuous integration tests to be\nrun on every pull request.\n\nChange-Id: I54c79aca7c0603337bd9fca443a0e2ffef603b0e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71298\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\n" }, { "commit": "cf2d5b68a91aafb46efd7e59b789b35681dd6ff3", "tree": "0ff654904aeafcf0a93ede7accde6e136567f07f", "parents": [ "a74695f5bcc3dd6c424e4d708732cc686a98794d" ], "author": { "name": "Matthew Poremba", "email": "matthew.poremba@amd.com", "time": "Tue May 30 13:57:09 2023 -0500" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Fri Jun 02 06:46:40 2023 +0000" }, "message": "gpu-compute: Gfx version check for FS and SE mode\n\nThere is no GPU device in SE mode to get version from and no GPU driver\nin FS mode to get version from, so a conditional needs to be added\ndepending on the mode to get the gfx version.\n\nChange-Id: I33fdafb60d351ebc5148e2248244537fb5bebd31\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71078\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nMaintainer: Matt Sinclair \u003cmattdsinclair@gmail.com\u003e\nReviewed-by: Matt Sinclair \u003cmattdsinclair@gmail.com\u003e\n(cherry picked from commit ebd5b3e4ae49b24dec4efc299d0b0198be9f4df3)\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71158\nReviewed-by: Matthew Poremba \u003cmatthew.poremba@amd.com\u003e\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\n" }, { "commit": "a74695f5bcc3dd6c424e4d708732cc686a98794d", "tree": "28d85e3699b78d6b56486ee2d89bb00875e2ab97", "parents": [ "32df25e426d125ea4e00cb8d130f4ee3d3662b73" ], "author": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Tue May 30 10:43:52 2023 -0700" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Thu Jun 01 22:45:50 2023 +0000" }, "message": "stdlib: Fix incorrect path and checks for DRAMsim3\n\nThere are three bugs fixed in this patch:\n\n1. The `dram_3_dir` was missing the \"dramsim3\" directory.\n2. Missing `not` when checking if configs is a directory.\n3. Missing `not` when checking if input file is a file.\n\nChange-Id: I185f4832c1c2f1ecc4e138c148ad7969ef9b6fd4\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71058\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "32df25e426d125ea4e00cb8d130f4ee3d3662b73", "tree": "b8b01c3f539f5fac860d44d0e65fdcdc757942bb", "parents": [ "65d077d79546a5b15b53162821d33c5cab9df3ef" ], "author": { "name": "Ayaz Akram", "email": "yazakram@ucdavis.edu", "time": "Thu Nov 10 13:26:44 2022 -0800" }, "committer": { "name": "Ayaz Akram", "email": "yazakram@ucdavis.edu", "time": "Fri May 26 20:08:00 2023 +0000" }, "message": "mem: HBMCtrl changes to allow PC data buses to be in different states\n\nThis change updates the HBMCtrl such that both pseudo channels\ncan be in separate states (read or write) at the same time. In\naddition, the controller queues are now always split in two\nhalves for both pseudo channels.\n\nChange-Id: Ifb599e611ad99f6c511baaf245bad2b5c9210a86\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65491\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "65d077d79546a5b15b53162821d33c5cab9df3ef", "tree": "6917b158a5e784d576a2f0d4ab96d8b9ec19c4ad", "parents": [ "741af7ddaed08be6eda0949471e5fec4f09b81d4" ], "author": { "name": "Melissa Jost", "email": "melissakjost@gmail.com", "time": "Thu May 25 15:42:20 2023 -0700" }, "committer": { "name": "Melissa Jost", "email": "melissakjost@gmail.com", "time": "Fri May 26 04:42:25 2023 +0000" }, "message": "base: Output link to common errors page\n\nThis change adds a link to the common errors page that outputs\nwhenever a fatal signal is raised, showing when the program\naborts or segfaults.\n\nChange-Id: I88420a594423570af670b460cfce7c03c4208120\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70978\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nMaintainer: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\n" }, { "commit": "741af7ddaed08be6eda0949471e5fec4f09b81d4", "tree": "a2e8d55fced8e3696a2fc951a601c6c3e532d412", "parents": [ "e0a28b1a27a5cd79eca7649ad7cb5ec8cce85b08" ], "author": { "name": "Ayaz Akram", "email": "yazakram@ucdavis.edu", "time": "Tue Feb 21 15:16:38 2023 -0800" }, "committer": { "name": "Ayaz Akram", "email": "yazakram@ucdavis.edu", "time": "Fri May 26 03:58:44 2023 +0000" }, "message": "mem: Add a DDR5 memory interface\n\nThis change adds a single DDR5 memory inteface.\nA DDR5 DIMM contains two physical channels. Therefore,\ntwo instances of this interface should be used to model\na DDR5 DIMM. The configuration includes 3 different speed\nbins models. The configuration is tested with different\ntypes of memory traffic using the traffic generator and shows\nperformance similar to what is observed in existing\nliterature [1]. One of the key features of DDR5\n\"same bank refresh\" is yet not supported in gem5, but is\nexpected to improve the performance of the DDR5 model.\n\n[1] Exploration of DDR5 with the Open-Source Simulator DRAMSys.\n\nChange-Id: I5856a10c8dcd92dbecc7fd4dcea0f674b2412dd7\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68257\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "e0a28b1a27a5cd79eca7649ad7cb5ec8cce85b08", "tree": "1669ec0ea3f10ff43b73484e3ae0c0b8882dbc09", "parents": [ "5095e29c8e1cc8b0ec08826e60b0c9622629d3a1" ], "author": { "name": "KUNAL PAI", "email": "kunpai@ucdavis.edu", "time": "Fri May 19 14:38:48 2023 -0700" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Thu May 25 21:42:31 2023 +0000" }, "message": "stdlib: Edit RISCVMatched Configuration\n\nThis patch changes the RISCVMatched Cache Hierarchy to\nprivate L1 shared L2.\nIt also changes the RISCVMatched Core\u0027s parameters to\nbetter match hardware performance.\nAlso, sizes are changed to MiB or KiB instead of MB\nor KB, to match the datasheet.\nAll the changes that deviate from the datasheet and the\nARM HPI CPU (reference for pipeline parameters)\nare documented.\n\nThe core parameters that are changed are:\n - threadPolicy:\n This is initialized to \"SingleThreaded\".\n - decodeToExecuteForwardDelay:\n This is changed from 1 to 2 to avoid a PMC address fault.\n - fetch1ToFetch2BackwardDelay:\n This is changed from 1 to 0 to better match hardware performance.\n - fetch2InputBufferSize:\n This is changed from 2 to 1 to better match hardware performance.\n - decodeInputBufferSize:\n This is changed from 3 to 2 to better match hardware performance.\n - decodeToExecuteForwardDelay:\n This is changed from 2 to 1 to better match hardware performance.\n - executeInputBufferSize:\n This is changed from 7 to 4 to better match hardware performance.\n - executeMaxAccessesInMemory:\n This is changed from 2 to 1 to better match hardware performance.\n - executeLSQStoreBufferSize:\n This is changed from 5 to 3 to better match hardware performance.\n - executeBranchDelay:\n This is changed from 1 to 2 to better match hardware performance.\n - enableIdling:\n This is changed to False to better match hardware performance.\n - MemReadFU: changed to 2 cycles from 3 cycles.\n\nThe changes in the branch predictor are:\n\n - BTBEntries:\n This is changed from 16 entries to 32 entries.\n - RASSize:\n This is changed from 6 entries to 12 entries.\n - IndirectSets:\n This is changed from 8 sets to 16 sets.\n - localPredictorSize:\n This is changed from 8192 to 16384.\n - globalPredictorSize:\n This is changed from 8192 to 16384.\n - choicePredictorSize:\n This is changed from 8192 to 16384.\n - localCtrBits:\n This is changed from 2 to 4.\n - globalCtrBits:\n This is changed from 2 to 4.\n - choiceCtrBits:\n This is changed from 2 to 4.\n\nChange-Id: I4235140f33be6a3b529a819ae6a7223cb88bb7ab\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70798\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\n" }, { "commit": "5095e29c8e1cc8b0ec08826e60b0c9622629d3a1", "tree": "b6ca36c501bd46b0fc91ddf04092f731a4806bed", "parents": [ "0fae6e8163ab50d24c74098397d1f65c7a1664fd" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Mon Apr 17 13:09:49 2023 +0100" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Thu May 25 21:36:58 2023 +0000" }, "message": "arch-arm: Implement FEAT_HCX\n\nThis is just making the HCRX_EL2 register read/writable;\ntrapping behaviour will be implemented with further extensions\n\nChange-Id: Id1ec42a754b7d999782edde3a8ec6c6099e3331e\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70939\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "0fae6e8163ab50d24c74098397d1f65c7a1664fd", "tree": "05e9abd318c5ef42e76b82c9c482470548cb9b35", "parents": [ "9de1443ebb8196950bcfdfc481ee0550feab0d7b" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Sat Apr 15 09:19:31 2023 +0100" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Thu May 25 21:36:58 2023 +0000" }, "message": "arch-arm: Implement FEAT_EVT\n\nThis extension is optional in Armv8.2 but mandatory since Armv8.5\nWe only implement this for AArch64\n\nChange-Id: I063642ac24d27f0a81ba79b1d38f72468bb130eb\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70938\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\n" }, { "commit": "9de1443ebb8196950bcfdfc481ee0550feab0d7b", "tree": "9a178fcf25eec2a79774a4d1e8d09325116d30c4", "parents": [ "eb4f83b178605a90ac714f1b2f779847aecd84b2" ], "author": { "name": "Richard Cooper", "email": "richard.cooper@arm.com", "time": "Mon Nov 09 19:05:09 2020 +0000" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Thu May 25 21:36:39 2023 +0000" }, "message": "arch-arm: Add support for Armv8.2-I8MM NEON extension.\n\nAdd support for the Armv8.2-I8MM NEON extension. This provides the\nSUDOT and USDOT mixed-sign SIMD Dot Product instructions, as well as\nthe SMMLA, UMMLA, and USMMLA SIMD Matrix Multiply-Accumulate\ninstructions.\n\nFor more information please refer to the Arm Architecture Reference\nManual (https://developer.arm.com/documentation/ddi0487/latest/).\n\nAdditional Contributors: Giacomo Travaglini\n\nChange-Id: I6fb9318f67cc9d2737079283e1a095630c4d2ad9\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70737\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "eb4f83b178605a90ac714f1b2f779847aecd84b2", "tree": "d61ff22a1f4bc9395360c526f22ee1ced9c6803d", "parents": [ "fab3d8a1c1de836bb79b4f5151a0eabe79aefca3" ], "author": { "name": "Richard Cooper", "email": "richard.cooper@arm.com", "time": "Mon Nov 09 18:56:31 2020 +0000" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Thu May 25 21:36:39 2023 +0000" }, "message": "arch-arm: Add support for Armv8.2-DotProd NEON extension.\n\nAdd support for the Armv8.2-DotProd NEON extension. This provides the\nSDOT and UDOT SIMD Dot Product instructions.\n\nFor more information please refer to the Arm Architecture Reference\nManual (https://developer.arm.com/documentation/ddi0487/latest/).\n\nChange-Id: I4caa3b97a74c65f32421487c55c3e36427194e61\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70736\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "fab3d8a1c1de836bb79b4f5151a0eabe79aefca3", "tree": "ea724fa780351ea8f14ed6b3bb09a28c62555693", "parents": [ "d02ea0dfbbb2fe0edf85ad832ca28c0cfcae0ee5" ], "author": { "name": "Richard Cooper", "email": "richard.cooper@arm.com", "time": "Mon Nov 09 18:50:16 2020 +0000" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Thu May 25 21:36:39 2023 +0000" }, "message": "arch-arm: Fix too long lines in existing Arm NEON instructons.\n\nThese lines break the current gem5 coding guidelines.\n\nChange-Id: I587fcb2d75c4ab9de47fa53b4ae96526a20afe3f\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70735\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "d02ea0dfbbb2fe0edf85ad832ca28c0cfcae0ee5", "tree": "49060369fd27d3cd4f1fce4bc8b2ba845905e805", "parents": [ "560df49c28352765445a39250a1cc3354b861957" ], "author": { "name": "Richard Cooper", "email": "richard.cooper@arm.com", "time": "Wed Oct 28 22:10:01 2020 +0000" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Thu May 25 21:36:39 2023 +0000" }, "message": "arch-arm, cpu, configs: Add new Op Classes for Matrix Multiply insts\n\nAdd SimdMatMultAcc and SimdFloatMatMultAcc Op Classes for the SVE\nMatrix Multiply Accumulate instructions in the SVE F32MM, F64MM and\nI8MM extensions.\n\nInitial latencies have been set to be the same as SimdMultAcc and\nSimdFloatMultAcc respectively.\n\nChange-Id: Ifab63a0efbb0ccfbd272245e0b0b055279f66e3a\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70734\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\n" }, { "commit": "560df49c28352765445a39250a1cc3354b861957", "tree": "0b542a0655340aadfc0de922394d946f8c3afbdd", "parents": [ "f8b60b7a1d2b8f7112801c1b97c2ca4959e111d0" ], "author": { "name": "Richard Cooper", "email": "richard.cooper@arm.com", "time": "Thu Oct 08 19:40:15 2020 +0100" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Thu May 25 21:36:39 2023 +0000" }, "message": "arch-arm: Declare support for Armv8.2-I8MM.\n\nSets the appropriate bit in the ID_AA64ZFR0_EL1 sysreg that declares\nsupport for ARMv8.2-I8MM.\n\nThis indicates that all pre-requisites for Armv8.2 SVE Int8 matrix\nmultiplication instructions have been met.\n\nSMMLA, SUDOT, UMMLA, USMMLA, and USDOT instructions are implemented.\n\nFor more information please refer to the \"ARM Architecture Reference\nManual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A\"\n(https://developer.arm.com/architectures/cpu-architecture/a-profile/\ndocs/arm-architecture-reference-manual-supplement-armv8-a)\n\nAdditional Contributors: Giacomo Travaglini\n\nChange-Id: Id97e1c5de8c23a25336a6b323034e9eca8e598e4\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70733\nMaintainer: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "f8b60b7a1d2b8f7112801c1b97c2ca4959e111d0", "tree": "fc6c8ec633b94ea53ea1692179311a6e8ccc38f4", "parents": [ "9421a46d71016378e7991c26cf5c73494d62668e" ], "author": { "name": "Richard Cooper", "email": "richard.cooper@arm.com", "time": "Thu Oct 01 18:31:49 2020 +0100" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Thu May 25 21:36:39 2023 +0000" }, "message": "arch-arm: Added Armv8.2-I8MM SVE mixed-sign dot product instrs.\n\nAdd support for the SVE mixed sign dot product instructions (USDOT,\nSUDOT) required by the Armv8.2 SVE Int8 matrix multiplication\nextension (ARMv8.2-I8MM).\n\nFor more information please refer to the \"ARM Architecture Reference\nManual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A\"\n(https://developer.arm.com/architectures/cpu-architecture/a-profile/\ndocs/arm-architecture-reference-manual-supplement-armv8-a)\n\nChange-Id: I83841654cee74b940f967b3a37b99d87c01bd92c\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70732\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "9421a46d71016378e7991c26cf5c73494d62668e", "tree": "36b7ff00230d490661058530a7286f8ea8d4160e", "parents": [ "98e67c8610fd016bc4150a6ab12f1497a2524a50" ], "author": { "name": "Richard Cooper", "email": "richard.cooper@arm.com", "time": "Tue Sep 29 16:15:23 2020 +0100" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Thu May 25 21:36:39 2023 +0000" }, "message": "arch-arm: Re-factor Arm decoder for SVE mixed-sign DOT insts.\n\nRe-factored the Arm instruction decoder to add placeholders for the\nSVE Integer mixed-sign DOT product instructions. This has involved\nmoving some existing decode helper functions.\n\nChange-Id: I42b280d4bd1b4ab9d8c633bdc523bd08c281d218\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70731\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "98e67c8610fd016bc4150a6ab12f1497a2524a50", "tree": "7f8885a975330ded7c88e23a54ade5eb35ac1214", "parents": [ "0f857873f95eac5e99f84c89df7bd1c2f4461a96" ], "author": { "name": "Richard Cooper", "email": "richard.cooper@arm.com", "time": "Mon Sep 28 17:50:52 2020 +0100" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Thu May 25 21:36:39 2023 +0000" }, "message": "arch-arm: Add support for Arm SVE Integer Matrix instructions.\n\nAdd support for the Arm SVE Integer Matrix Multiply-Accumulate\n(SMMLA, USMMLA, UMMLA) instructions. Because the associated SUDOT and\nUSDOT instructions have not yet been implemented, the SVE Feature ID\nregister 0 (ID_AA64ZFR0_EL1) has not yet been updated to indicate\nsupport for SVE Int8 matrix multiplication instructions at this time.\n\nFor more information please refer to the \"ARM Architecture Reference\nManual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A\"\n(https://developer.arm.com/architectures/cpu-architecture/a-profile/\ndocs/arm-architecture-reference-manual-supplement-armv8-a)\n\nAdditional Contributors: Giacomo Travaglini\n\nChange-Id: Ia50e28fae03634cbe04b42a9900bab65a604817f\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70730\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "0f857873f95eac5e99f84c89df7bd1c2f4461a96", "tree": "889bb3787a6fe206b9a68a38941df9c774a2eb1e", "parents": [ "8bf89d696737c9d270c5e2d7adde429fa39dd58f" ], "author": { "name": "Richard Cooper", "email": "richard.cooper@arm.com", "time": "Thu Oct 08 19:35:47 2020 +0100" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Thu May 25 21:36:39 2023 +0000" }, "message": "arch-arm: Declare support for Armv8.2-F64MM.\n\nSets the appropriate bit in the ID_AA64ZFR0_EL1 sysreg that declares\nsupport for ARMv8.2-F64MM.\n\nThis indicates that all pre-requisites for Armv8.2 SVE FP64\ndouble-precision floating-point matrix multiplication instructions\nhave been met.\n\nFMMLA, and LD1RO* instructions have been implemented, as well as the\n128-bit element variants of TRN1, TRN2, UZP1, UZP2, ZIP1, and ZIP2.\n\nFor more information please refer to the \"ARM Architecture Reference\nManual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A\"\n(https://developer.arm.com/architectures/cpu-architecture/a-profile/\ndocs/arm-architecture-reference-manual-supplement-armv8-a)\n\nAdditional Contributors: Giacomo Travaglini\n\nChange-Id: Idac3a3ca590e6eb2beb217a40a8c10af1e917440\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70729\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\n" }, { "commit": "8bf89d696737c9d270c5e2d7adde429fa39dd58f", "tree": "fdca403643e5fad1a67f046a0d088ee8e144dd21", "parents": [ "19e802304335d78956a2cdaa965ccf010c9152fb" ], "author": { "name": "Richard Cooper", "email": "richard.cooper@arm.com", "time": "Fri Sep 18 16:40:45 2020 +0100" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Thu May 25 21:36:39 2023 +0000" }, "message": "arch-arm: Added 128-bit encodings of SVE TRN, UZP, and ZIP insts.\n\nAdd support for the 128-bit element encodings of the TRN1, TRN2, UZP1,\nUZP2, ZIP1, and ZIP2 instructions, required by the Armv8.2 SVE\nDouble-precision floating-point Matrix Multiplication\ninstructions (ARMv8.2-F64MM).\n\nFor more information please refer to the \"ARM Architecture Reference\nManual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A\"\n(https://developer.arm.com/architectures/cpu-architecture/a-profile/\ndocs/arm-architecture-reference-manual-supplement-armv8-a)\n\nChange-Id: I496576340c48410fedb2cf6fc7d1a02e219b3bd4\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70728\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "19e802304335d78956a2cdaa965ccf010c9152fb", "tree": "04753cbd0eb935f74eda80728f8611e99796c096", "parents": [ "94a629b527174676fba1b04af5df0f51ed27ad15" ], "author": { "name": "Richard Cooper", "email": "richard.cooper@arm.com", "time": "Mon Sep 14 18:55:09 2020 +0100" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Thu May 25 21:36:39 2023 +0000" }, "message": "arch-arm: Support Arm SVE Load-Broadcast Octaword instructions.\n\nAdd support for the Arm SVE Load-Broadcast Octaword (LD1RO{B,H,W,D})\ninstructions. These are similar to the Load-Broadcast\nQuadword (LD1RQ{B,H,W,D}) instructions, but work on a 32-byte memory\nsegment rather than a 16-byte memory segment. Consequently, the LD1ROx\nimplementations build on the code for the LD1RQx implementations.\n\nFor more information please refer to the \"ARM Architecture Reference\nManual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A\"\n(https://developer.arm.com/architectures/cpu-architecture/a-profile/\ndocs/arm-architecture-reference-manual-supplement-armv8-a)\n\nChange-Id: I98ee4f56c8099bf40c9034baa488d318ae57d3aa\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70727\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "94a629b527174676fba1b04af5df0f51ed27ad15", "tree": "5a496358af07b586232bfe98bd733dc51e1c3b08", "parents": [ "87ec6919a39083c9e54eb686c235316c2b2062d3" ], "author": { "name": "Richard Cooper", "email": "richard.cooper@arm.com", "time": "Fri Aug 21 20:11:31 2020 +0100" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Thu May 25 21:36:39 2023 +0000" }, "message": "arch-arm: Add support for Arm SVE fmmla instruction.\n\nAdd support for the Arm SVE Floating Point Matrix Multiply-Accumulate\n(FMMLA) instruction. Both 32-bit element (single precision) and 64-bit\nelement (double precision) encodings are implemented, but because the\nassociated required instructions (LD1RO*, etc) have not yet been\nimplemented, the SVE Feature ID register 0 (ID_AA64ZFR0_EL1) has only\nbeen updated to indicate 32-bit element support at this time.\n\nFor more information please refer to the \"ARM Architecture Reference\nManual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A\"\n(https://developer.arm.com/architectures/cpu-architecture/a-profile/\ndocs/arm-architecture-reference-manual-supplement-armv8-a)\n\nAdditional Contributors: Giacomo Travaglini\n\nChange-Id: If3547378ffa48527fe540767399bcc37a5dab524\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70726\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\n" }, { "commit": "87ec6919a39083c9e54eb686c235316c2b2062d3", "tree": "b82cfc33ff302bc101f0abcd2b3b433250befba2", "parents": [ "6b4a1020bed8e2251adbc3f4cb065865e9006b12" ], "author": { "name": "Matthew Poremba", "email": "matthew.poremba@amd.com", "time": "Wed Apr 19 15:57:47 2023 -0500" }, "committer": { "name": "Matthew Poremba", "email": "matthew.poremba@amd.com", "time": "Thu May 25 19:14:46 2023 +0000" }, "message": "mem: Handle DRAM write queue drain and disabled power down\n\nWrite queue drain logic seems off currently. An event is scheduled if\nthe write queue is empty instead of non-empty. There is no check to see\nif draining is complete when bus is in write mode. Finally the power\ndown check on drain always fails if DRAM powerdown is disabled.\n\nThis changeset reverses the drain conditional for the write queue to\nschedule an event if the write queue is *not* empty and checks in the\nevent processing method that the queues are all empty so that\nsignalDrainDone can be called. Lastly the powerdown state is ignored if\nDRAM powerdown is disabled. Powerdown is disabled in the GPU_VIPER\nprotocol by default. This changeset successfully drains and checkpoints\na GPUFS simulation using GPU_VIPER protocol.\n\nChange-Id: I5459856a694c9054b28677049a06b99b9ad91bbb\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69917\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\n" }, { "commit": "6b4a1020bed8e2251adbc3f4cb065865e9006b12", "tree": "7d3c20362508dfc1d85f0d8e22561e842fda505e", "parents": [ "2aa95ccc7d4695975c3ee686fc68c32bc616b36b" ], "author": { "name": "Matthew Poremba", "email": "matthew.poremba@amd.com", "time": "Fri May 05 10:50:48 2023 -0500" }, "committer": { "name": "Matthew Poremba", "email": "matthew.poremba@amd.com", "time": "Thu May 25 19:14:32 2023 +0000" }, "message": "configs,dev-amdgpu: GPUFS MI200/gfx90a support\n\nAdd support for MI200-like device. This includes adding PCI IDs and new\nMMIOs for the device, a different MAP_PROCESS packet, and a different\ncalculation for the number of VGPRs.\n\nChange-Id: I0fb7b3ad928826beaa5386d52a94ba504369cb0d\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70317\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "2aa95ccc7d4695975c3ee686fc68c32bc616b36b", "tree": "a7577fdaf12b95cbb0bf6da88b2e9243a1500b5e", "parents": [ "dc76c00c9bb69ebb43899b0fb07b4f57c9add715" ], "author": { "name": "Matthew Poremba", "email": "matthew.poremba@amd.com", "time": "Fri May 19 13:39:43 2023 -0500" }, "committer": { "name": "Matthew Poremba", "email": "matthew.poremba@amd.com", "time": "Thu May 25 14:38:09 2023 +0000" }, "message": "arch-x86: Fix CPUID function 0\n\nThis should return the number of standard features, not the number of\nextended features.\n\nChange-Id: Ieb3a36d832cee603f1efd39b4f430b5ac0478561\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70778\nMaintainer: Matt Sinclair \u003cmattdsinclair@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Matt Sinclair \u003cmattdsinclair@gmail.com\u003e\n" }, { "commit": "dc76c00c9bb69ebb43899b0fb07b4f57c9add715", "tree": "887726a540aa2ac5dfa6a9972efc79cdcd13e3f1", "parents": [ "dfa3c073cfd0112ab834fbf7d1056e0aa2a090e3" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed May 24 13:10:16 2023 +0100" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Thu May 25 07:30:48 2023 +0000" }, "message": "arch-arm: Add an ArmAllRelease containing every defined extension\n\nThis is probably the easiest way to instantiate a release containing\nany implemented extension. It is alternatively possible to use the\nlatest release (e.g. Armv92 as of now).\nThis could be preferrable for consistency across simulations.\nHowever if users want to always be up to date with development,\nusing ArmAllRelease will allow them to do so without the need\nto change their configuration script\n\nChange-Id: Ibca629e99da9b571f233de9d05a5a9186d02aa99\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70958\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\n" }, { "commit": "dfa3c073cfd0112ab834fbf7d1056e0aa2a090e3", "tree": "f3dcd6a711ae7dfeec889fa4bf1b597fcfacd396", "parents": [ "2579bacf06eb57b75b7fae1c9b1b133fa64f9841" ], "author": { "name": "Prajwal Hegde", "email": "prhegde@wisc.edu", "time": "Thu Apr 27 14:38:36 2023 -0500" }, "committer": { "name": "Prajwal Rathnakar Hegde", "email": "prhegde@wisc.edu", "time": "Wed May 24 01:22:30 2023 +0000" }, "message": "arch-arm,cpu: Add four Arm SVE2 int instructions\n\nThis changeset adds ARM SVE2 integer instructions\n- ADCLB, ADCLT, SBCLB, SBCLT\n- Decoding logic as per sve encoding of Version: 2023-03\n\nChange-Id: I1bd3fe24b33677baa0b6da3c1dd7423f2b13b2c6\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70137\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nMaintainer: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\n" }, { "commit": "2579bacf06eb57b75b7fae1c9b1b133fa64f9841", "tree": "7d0c8b6738bcd21dbe90e77bfe56216c7864e3f3", "parents": [ "5fa81af8c65416e51a99fff1e9aef7dd10fe347f" ], "author": { "name": "Roger Chang", "email": "rogerycchang@google.com", "time": "Sat May 13 23:09:48 2023 +0800" }, "committer": { "name": "Roger Chang", "email": "rogerycchang@google.com", "time": "Tue May 23 23:58:16 2023 +0000" }, "message": "arch-riscv: Merge rv32 and rv64 version of xperm4 and xperm8\n\nRemove unessential postfix like \u0027_32\u0027 and \u0027_64\u0027 from mnemonic\n\nChange-Id: I83d47eeccd04fe61ac8ee0addd7221abbdcefbd1\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70600\nReviewed-by: Yu-hsin Wang \u003cyuhsingw@google.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\n" }, { "commit": "5fa81af8c65416e51a99fff1e9aef7dd10fe347f", "tree": "3bfb5dd2a67e844d1dd52be3627024f64782df6e", "parents": [ "4dccd7dd6c69971541be2cbb0de4a2fe2b52f3ac" ], "author": { "name": "Roger Chang", "email": "rogerycchang@google.com", "time": "Sat May 13 23:04:46 2023 +0800" }, "committer": { "name": "Roger Chang", "email": "rogerycchang@google.com", "time": "Tue May 23 23:58:16 2023 +0000" }, "message": "arch-riscv: Simplify the rev8 and brev8 instructions\n\nThese mnemonic of instructions should not have \u0027rv32_\u0027 prefix\n\nChange-Id: Ic072ba8b84e5a51be060e5d7ca16dd913c318957\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70599\nReviewed-by: Yu-hsin Wang \u003cyuhsingw@google.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "4dccd7dd6c69971541be2cbb0de4a2fe2b52f3ac", "tree": "f0737bedac38fb3505e9dbf2703a91af9c4afcf7", "parents": [ "1a2904e021671374d20527b46a10d2de2ae310ce" ], "author": { "name": "Roger Chang", "email": "rogerycchang@google.com", "time": "Sat May 13 21:42:39 2023 +0800" }, "committer": { "name": "Roger Chang", "email": "rogerycchang@google.com", "time": "Tue May 23 23:58:16 2023 +0000" }, "message": "arch-riscv: Add BS format isa\n\nThis format is helper for aes32dsi, aes32dsmi, aes32esi, aes32esmi,\nsm4ed, sm4ks disassembly\n\nChange-Id: Ieff1932e267efc0a8c5fd8e557fc467dc376da4e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70598\nReviewed-by: Yu-hsin Wang \u003cyuhsingw@google.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\n" }, { "commit": "1a2904e021671374d20527b46a10d2de2ae310ce", "tree": "897900a149282bb05de5b51eba58e3043590c304", "parents": [ "d537ded9d225f04ebdcb2d64585f30c8e7f7756d" ], "author": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Tue May 23 08:41:31 2023 -0700" }, "committer": { "name": "Jason Lowe-Power", "email": "power.jg@gmail.com", "time": "Tue May 23 20:54:41 2023 +0000" }, "message": "scons: Add os import to marshall\n\nThis file was missing the `import os` after\nI3ad28b6ee52fd347d2fe71f279baab629e88d12c\n\nChange-Id: I7fde59e92f03fd240f48a304488d77628bfdb852\nSigned-off-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70918\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\n" }, { "commit": "d537ded9d225f04ebdcb2d64585f30c8e7f7756d", "tree": "0803033461c780c67dcb449443db1724a6812919", "parents": [ "4d18546bfb24570ada5d524260c68d2eb3b92a63" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue May 16 15:42:00 2023 +0100" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue May 23 19:51:21 2023 +0000" }, "message": "arch-arm: Fix printing of VecElemClass registers\n\nAt the moment it is not possible to trace the value of VecElemClass\nregisters. If a AArch32 SIMD binary is run with tracing on,\nsimulation will fail the following assertion [1].\n\nstd::string\nvalString(const void *val, size_t size) const override\n{\n assert(size \u003d\u003d sizeof(ValueType));\n\nThe problem is that Arm VecElems are stored in RegVal (uint64_t),\nbut the VecElem data type (ValueType above) per se is a uint32_t.\n\nSo valString is getting called with size \u003d 8 (coming from RegVal)\nbut ValueType has size \u003d 4. We fix this problem by using RegVal as\na VecElemRegClassOps template parameter to make them match.\nThis is not changing anything from a functionality perspective.\nThe result will be that we will be able to print VecElems as 64bit\nvalues.\n\nThis solution is the most simple one but a bit dirty. I believe\nin the long term we should make the VecElemClass use the void* interface\nrather than the RegVal one. In this way we will be able to correctly\nprint the VecElem size as 32bit value.\n\n[1]: https://github.com/gem5/gem5/blob/v22.1.0.0/src/cpu/reg_class.hh#L362\n\nChange-Id: Ic3fc252d41449f828b77f938fefc0cd4274b1c57\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70697\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\n" }, { "commit": "4d18546bfb24570ada5d524260c68d2eb3b92a63", "tree": "a6922ab2e5343b464efc224ea68ef52ebd3c0cc9", "parents": [ "332ef131dc0d8c71dc76bf9d0726390d0ec3abbd" ], "author": { "name": "Matthew Poremba", "email": "matthew.poremba@amd.com", "time": "Mon May 22 16:03:58 2023 -0500" }, "committer": { "name": "Matthew Poremba", "email": "matthew.poremba@amd.com", "time": "Tue May 23 14:28:16 2023 +0000" }, "message": "dev-amdgpu: Update SDMA checkpointing\n\nPatch https://gem5-review.googlesource.com/c/public/gem5/+/70040 added\nsupport for a variable number of SDMA engines to support newer GPU\nmodels. As part of this an SDMA IDs map was added to map from SDMA ID\nnumber to the SDMA SimObject pointer. In order to get the correct\npointer in unserialize now, we need to store the ID in the checkpoint\nand use that to index the new map. We can\u0027t simply assign using the loop\nvariable as the SDMAs might not be in order in the checkpoint and\nadditionally the checkpoint contains both the gfx and page offset for\nthe SDMA engines, so each SDMA is inserted into the SDMA offset map\n(sdmaEngs) twice.\n\nChange-Id: I08e9a8d785f467b6eebff8ab0a9336851c87258d\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70878\nMaintainer: Matt Sinclair \u003cmattdsinclair@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Matt Sinclair \u003cmattdsinclair@gmail.com\u003e\n" }, { "commit": "332ef131dc0d8c71dc76bf9d0726390d0ec3abbd", "tree": "9e4ec4a5665256dfd60b66bc8718afdd868313ca", "parents": [ "7b91521c605be23ea512d4e59b6cd1ac95a087a0" ], "author": { "name": "Luming Wang", "email": "wlm199558@126.com", "time": "Sat May 20 17:29:59 2023 +0800" }, "committer": { "name": "Luming Wang", "email": "wlm199558@126.com", "time": "Tue May 23 07:24:59 2023 +0000" }, "message": "scons: fix build failed caused by Non-ASCII directory path\n\nThis patch addresses the issue of gem5 failing to build when\nthe build directory path contains non-ASCII characters.\nThe previous patches[1] that attempted to fix this issue\nbecame ineffective after the upgrade of Python and pybind11\nto new versions. This new patch manually sets the locale in\nmarshal.py based on the `LC_CTYPE` environment variable,\nproviding a comprehensive solution that works with Non-ASCII\nbuild directory paths.\n\n[1] https://gem5-review.googlesource.com/c/public/gem5/+/58369\n\nChange-Id: I3ad28b6ee52fd347d2fe71f279baab629e88d12c\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70818\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\n" }, { "commit": "7b91521c605be23ea512d4e59b6cd1ac95a087a0", "tree": "4712afe862bc6d7214f05bd01619b75338ed5b6d", "parents": [ "3787ab5b200d4a60459e6f9fa8b7688672a70591" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Fri Apr 14 11:02:07 2023 +0100" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue May 23 06:43:21 2023 +0000" }, "message": "arch-arm: Define a AA64ZFR0 data type\n\nChange-Id: I6b0dcf0c1882f356783934f625c2bc3a25fbb885\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70725\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\n" }, { "commit": "3787ab5b200d4a60459e6f9fa8b7688672a70591", "tree": "4a226085e721608c9a0181bc10adc338e89a92e0", "parents": [ "ae115fcfd5b4180fe9bb0273f47e457f64e036b5" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Thu Apr 13 10:52:06 2023 +0100" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue May 23 06:43:21 2023 +0000" }, "message": "arch-arm: Rename AdvSIMD instruction pool\n\nThe decoding function was wrongly named decodeNeon3SameExtra,\nreferring to the \"AdvSIMD three same Extra\" instruction pool\n\nThis might be an old name as I can only find the\n\"AdvSIMD *scalar* three same Extra\" in the Arm arm. The\nencoding space reserved to the pool bears the\n\"Advanced SIMD three-register extension\" name; we\ntherefore rename the function to decodeNeon3RegExtension\n\nChange-Id: I056da8f0c7808935d12a4b05490d30654178071f\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70724\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\n" }, { "commit": "ae115fcfd5b4180fe9bb0273f47e457f64e036b5", "tree": "bfe66fb9178a1dad1e6f11cce7668328a5e4b75a", "parents": [ "e005e6f250536c751fc2d4718e0d3af0bc547583" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Mar 07 22:33:31 2023 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue May 23 06:43:21 2023 +0000" }, "message": "arch-arm: Implement FEAT_IDST\n\nChange-Id: I3cabcfdb10f4eefaf2ab039376d840cc4c54609a\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70723\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\n" }, { "commit": "e005e6f250536c751fc2d4718e0d3af0bc547583", "tree": "e495c6573a2c6ef2c8b7e54e9f1e23d34fd44668", "parents": [ "1629ee71c7794f97de4d9e24fd0cf339576fadea" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed Mar 08 07:59:35 2023 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue May 23 06:43:21 2023 +0000" }, "message": "arch-arm: Implement trapping of SME registers\n\nChange-Id: Ic5bcc79a535c928265fbc1db1cd0c85ba1a1b152\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70722\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\n" }, { "commit": "1629ee71c7794f97de4d9e24fd0cf339576fadea", "tree": "ee4d60b2a692fa285f262faba0c07498d080167f", "parents": [ "2a5c427c5c406aca25bfaaa40af7216f25623ffa" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Mar 07 16:13:45 2023 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue May 23 06:43:21 2023 +0000" }, "message": "arch-arm: Implement FEAT_RNG\n\nChange-Id: I9d60d249172ef4bbaf5d9b38ef279eff344b80d8\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70721\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\n" }, { "commit": "2a5c427c5c406aca25bfaaa40af7216f25623ffa", "tree": "a18dd147bc778407df3c5b40d6ee7d6eb15419df", "parents": [ "e3d2191b73581cf2bcae88ba4fa8c2f46c35efd9" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Mar 07 16:59:16 2023 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue May 23 06:43:21 2023 +0000" }, "message": "arch-arm: Extend SCR to be 64-bit wide\n\nChange-Id: I9928de3db61957404269d189a15a951fd6707c8a\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70720\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\n" }, { "commit": "e3d2191b73581cf2bcae88ba4fa8c2f46c35efd9", "tree": "1c2dd8dd2c50d4ae9cfaab630dc693f2f6038b25", "parents": [ "223a07031f0a0c53e72c445675d52d6921eb6e8e" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Mon Mar 06 19:37:39 2023 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue May 23 06:43:21 2023 +0000" }, "message": "arch-arm: Implement FEAT_FLAGM(2)\n\nChange-Id: I21f1eb91ad9acb019a776a7d5edd38754571a62e\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70719\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "223a07031f0a0c53e72c445675d52d6921eb6e8e", "tree": "cfa063e9cf4fca6696d96e5d9772fe5d8089a911", "parents": [ "3b3911f521a83ec0c2d5e2c30e06cd8f3432bf49" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Mar 07 14:58:15 2023 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue May 23 06:43:21 2023 +0000" }, "message": "arch-arm: Improve debugging of CC regs accesses\n\nAs of now we are simply printing the CC reg index which is\nnot particularly helpful. With this patch we actually print\nthe (NZ|C|V) reg name.\n\nChange-Id: Ib4b56a372b25e5bc2b6b762d2ef3ff2084097cce\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70718\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "3b3911f521a83ec0c2d5e2c30e06cd8f3432bf49", "tree": "fd8b7c42736e24f4cba1d407a1a9559d08125d50", "parents": [ "98821e365cfe04b1e1463dba69a9e0788d9ae10c" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Mar 07 12:40:24 2023 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue May 23 06:43:21 2023 +0000" }, "message": "arch-arm: Split decodeDataProcReg into subfunctions\n\nThis will increase readibility, it will make it easier\nfor devs to add new instructions, and it removes some\nduplication (some register indexes were read more than\nonce)\n\nChange-Id: Ifa03a93cb73de0b2dc93d7784f9011e0e55dfc1e\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70717\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "98821e365cfe04b1e1463dba69a9e0788d9ae10c", "tree": "623799cf92a7ac9b3eaed900c26319fa97d9f1e8", "parents": [ "a3cae504019bad10f8e5fc6fd661ef12848c9cbe" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Thu May 18 10:47:55 2023 +0100" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue May 23 06:43:21 2023 +0000" }, "message": "arch-arm: Extend auxiliary vector with AT_HWCAP2 entry\n\nThe presence of some of the new extensions is reported via\nthe AT_HWCAP2 entry\n\nChange-Id: I7a2d813ea84bf528b1f9df09121f9e97456a11c0\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70760\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\n" }, { "commit": "a3cae504019bad10f8e5fc6fd661ef12848c9cbe", "tree": "80dac5d85737972848f1c754763894a99350ed8f", "parents": [ "00426eea99b6f71ac48630cd81bf4145213bc738" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed May 17 15:34:50 2023 +0100" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue May 23 06:43:21 2023 +0000" }, "message": "arch-arm: Enable FEAT_PAuth in SE mode\n\nIt was in theory already possible to use FEAT_PAuth instructions in\nSE mode, however its presence was hidden to userspace code as\nthe cpu feature was not listed in the auxiliary vectors\n\nChange-Id: I6da5da0878dde56c22ffdba25eff15e36f5022fe\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70759\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "00426eea99b6f71ac48630cd81bf4145213bc738", "tree": "58ea907e3be366591fa8d67d089cb8b49dd154eb", "parents": [ "4198d027ac2673457953eecfbec9db681991f78d" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed May 17 15:33:34 2023 +0100" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue May 23 06:43:21 2023 +0000" }, "message": "arch-arm: Define remaining fields of the arm64 AT_HWCAP entry\n\nChange-Id: I4db4884d677f6d25417ae6edceb7f1e8dfad36cb\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70758\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "4198d027ac2673457953eecfbec9db681991f78d", "tree": "17511fc68b27649b86ab5b6d83a6e0850ab3a16e", "parents": [ "9c0f337d7813589207d0c3f48a0c785ba5378a79" ], "author": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Mon May 22 13:59:24 2023 -0700" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Tue May 23 03:14:55 2023 +0000" }, "message": "tests,systemc: Fix nightly systemc test\n\nThis fixes these nightly failing tests:\nhttps://jenkins.gem5.org/job/nightly/609/\n\nDue to this commit:\nhttps://gem5-review.googlesource.com/c/public/gem5/+/68758\nThe source files are not copied to the \"build\" directory by default.\nThis caused the systemc tests to fail as the\n\"util/systemc/gem5_within_systemc/Makefile\" depends on generated source\nfiles in the \"build\" directory.\n\nThis patch adds the \"--duplicate-sources\" flag to the building of the\nARM binaries necessisary for running systemc. The README has been\nupdated to reflect this.\n\nChange-Id: I3006005e43276097be98f7d4685f3d98c180d3f9\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70860\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\n" }, { "commit": "9c0f337d7813589207d0c3f48a0c785ba5378a79", "tree": "4ef6c7ffeef65a59ec2951dbf7ca6f5625a8153e", "parents": [ "08644a76707ac8ee14f9ff0d52af7c3e324209f0" ], "author": { "name": "Roger Chang", "email": "rogerycchang@google.com", "time": "Fri May 12 23:22:14 2023 +0800" }, "committer": { "name": "Roger Chang", "email": "rogerycchang@google.com", "time": "Tue May 23 02:34:09 2023 +0000" }, "message": "arch-riscv: Simplify amd merge RV32/RV64 the RVM instructions\n\nThe change move the details implementation to utility.hh and merge\nthe RV32 and RV64 versions into one.\n\nChange-Id: I438bfb0fc511f0f27e83f247d386c58493db65b4\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70597\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Yu-hsin Wang \u003cyuhsingw@google.com\u003e\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\n" }, { "commit": "08644a76707ac8ee14f9ff0d52af7c3e324209f0", "tree": "e382d3adb5d6a0a0074db575337edc53eae20e42", "parents": [ "44919c1c4d02d980316d84a3749279810acd1362" ], "author": { "name": "Matthew Poremba", "email": "matthew.poremba@amd.com", "time": "Tue May 16 19:46:50 2023 -0500" }, "committer": { "name": "Matthew Poremba", "email": "matthew.poremba@amd.com", "time": "Mon May 22 15:08:11 2023 +0000" }, "message": "dev-amdgpu: Fix nbio psp ring assert\n\nThe size of the packet changes between ROCm 4.x and ROCm 5.x. Change how\nthe address is set based on the incoming packet size so that both\nversions continue to work for now.\n\nChange-Id: I91694e4760198fd9129e60140df4e863666be2e2\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70677\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Matt Sinclair \u003cmattdsinclair@gmail.com\u003e\nMaintainer: Matt Sinclair \u003cmattdsinclair@gmail.com\u003e\n" }, { "commit": "44919c1c4d02d980316d84a3749279810acd1362", "tree": "d8132d9fb8508c315c65851e5ce6c3b872d29bb4", "parents": [ "c4d61ca1439c677c7c9f0dfd06b7093d9779b611" ], "author": { "name": "Ayaz Akram", "email": "yazakram@ucdavis.edu", "time": "Sun Apr 30 16:25:04 2023 -0700" }, "committer": { "name": "Roger Chang", "email": "rogerycchang@google.com", "time": "Sun May 21 23:56:01 2023 +0000" }, "message": "configs: Update riscv/fs_linux.py script\n\nThis change fixes a couple of small issues with\nthe configs/example/riscv/fs_linux.py script to ensure\nthat it works with the latest version of gem5.\n\nChange-Id: I9753ca4c8dd0b87d05681b167cf51e3c097e9152\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70177\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nReviewed-by: Alex Richardson \u003calexrichardson@google.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Roger Chang \u003crogerycchang@google.com\u003e\n" }, { "commit": "c4d61ca1439c677c7c9f0dfd06b7093d9779b611", "tree": "7c110b0c199c0d45a8797477689c1c286ecefbb8", "parents": [ "fccd13ac85b7b11409e0f92b81cb64345e51b079" ], "author": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Wed May 10 12:19:38 2023 -0700" }, "committer": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Wed May 17 17:49:48 2023 +0000" }, "message": "tests: Add \u0027--duplicate-sources\u0027 to libgem5 SST build\n\nUnfortunately the building of SST (in \"ext/sst\") depends on generated\nheader files. Therefore it adds the build directory to the include path.\nFor this to work the libgem5.so must be build with\n\"--duplicate-sources\".\n\nChange-Id: I5ed26a89c81402d421f5dfa110de7cf758f28694\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70497\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "fccd13ac85b7b11409e0f92b81cb64345e51b079", "tree": "bb6097a7cd00a4ccd3d23111713049a3f694d0e5", "parents": [ "bc63da39dc3c92e9a2a7c55145645cfcb8c96a5c" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Wed Mar 08 09:37:34 2023 +0000" }, "committer": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Wed May 17 17:49:48 2023 +0000" }, "message": "scons: default to not duplicating sources in the build directory\n\nWe now default to --no-duplicate-sources, but keep --duplicate-sources to\nopt-out of this new build behaviour in case it introduces regressions.\n\nChange-Id: I2f01ceaef7b6b9bff80f4402081f007110f7e6f3\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68758\nMaintainer: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nReviewed-by: Bobby Bruce \u003cbbruce@ucdavis.edu\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "bc63da39dc3c92e9a2a7c55145645cfcb8c96a5c", "tree": "21224106e00a4b95a3b945b1499189cd10af8443", "parents": [ "aff1ddb196ab08ec3d60437e8d85c20df5de5b26" ], "author": { "name": "Bobby R. Bruce", "email": "bbruce@ucdavis.edu", "time": "Mon May 15 17:25:59 2023 -0700" }, "committer": { "name": "Bobby Bruce", "email": "bbruce@ucdavis.edu", "time": "Wed May 17 17:49:01 2023 +0000" }, "message": "arch-riscv: Fix WFI for O3 CPU\n\nThis commit:\nhttps://gem5-review.googlesource.com/c/public/gem5/+/61511\nintroduced a bug where the O3 CPU hangs. This is because WFI must be\ntagged as `IsNonSpeculative`, `IsQuiesce`, and `IsSerializeAfter` to\nfunction correctly with O3 CPUs.\n\nChange-Id: I8b6cb049710d05f37f89a9ce22acc604112bc445\nIssue-on: https://gem5.atlassian.net/browse/GEM5-1323\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70657\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nReviewed-by: Roger Chang \u003crogerycchang@google.com\u003e\nReviewed-by: Jui-min Lee \u003cfcrh@google.com\u003e\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "aff1ddb196ab08ec3d60437e8d85c20df5de5b26", "tree": "71509269157b96e1d4f4aa714ef340438a2bebf5", "parents": [ "20bf5e17e3b69065dda95609bd0070da4f123cec" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Thu Jul 21 16:14:18 2022 +0100" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed May 17 08:11:06 2023 +0000" }, "message": "arch-arm: Implement FEAT_TLBIOS\n\nThis feature is mandatory in Armv8.4\nWe are currently not distinguishing Inner and Outer domains.\nWe therefore implement TLBIOS instructions as TLBIIS\n\nChange-Id: I2198e6155f1eea7c5f8083c6ffb178d3a3d163d3\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70567\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\n" }, { "commit": "20bf5e17e3b69065dda95609bd0070da4f123cec", "tree": "22e9419cd64180f34c03f8aab2b51640c0a5f888", "parents": [ "60dd3c7d05c41988abfa9833556e2247466f4b26" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Feb 21 13:25:02 2023 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed May 17 08:11:06 2023 +0000" }, "message": "arch-arm: Extend SCTLR to be 64-bit wide\n\nIn AArch64 SCTLR_EL1/_EL2/_EL3 is 64-bit wide\n\nChange-Id: I80931f9dd1a57f3132229b84d32a8ab08eee3371\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70566\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\n" }, { "commit": "60dd3c7d05c41988abfa9833556e2247466f4b26", "tree": "2bbbc4523e7523adb544f8e5455499136c1bacb6", "parents": [ "3e1b9dfc0f8ca9bd0e869a6f1bf04dd31f7acb18" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed Feb 08 10:48:29 2023 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed May 17 08:11:06 2023 +0000" }, "message": "arch-arm: Simplify FPSCR writes\n\nThe old logic was setting up a mask which was covering pretty much\nthe entire register, except for the FPSCR[14:13] and FPSCR[6:5]\nregister fields. Those RES0 fields were treated as WI.\nWe simplify this by explicitly marking them as RES0 at construction\ntime\n\nChange-Id: I59942bd98c074349307d27e3a99351ee25f4db95\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70565\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "3e1b9dfc0f8ca9bd0e869a6f1bf04dd31f7acb18", "tree": "8efbb3a665bb10151c677e2a676e544763b6c899", "parents": [ "f72d22cc3830099ef5c99f0312e84b54d7296315" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Feb 07 15:26:47 2023 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed May 17 08:11:06 2023 +0000" }, "message": "arch-arm: Remove unnecessary case in ISA::readMiscReg\n\nChange-Id: I8b95a75fbfec2626fbe8b455ae9b3f30acda538f\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70564\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "f72d22cc3830099ef5c99f0312e84b54d7296315", "tree": "b7abc49eafcbe1514902c26f0b0af02f15c8e898", "parents": [ "bc5b00cd2b5dea850acf63f6a1055ff260c8fba7" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Feb 07 14:47:40 2023 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed May 17 08:11:06 2023 +0000" }, "message": "arch-arm: Implement RES0/RES1 with miscreg specifiers\n\nChange-Id: Ic2caea121e02f63f069f1576760c849bcbdac894\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70563\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "bc5b00cd2b5dea850acf63f6a1055ff260c8fba7", "tree": "de3708f088eced4385188ab65a845aa1a81ab48c", "parents": [ "32b4ab376c08b48cf973dbafc3a7119a76c642cb" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Feb 07 11:12:23 2023 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed May 17 08:11:06 2023 +0000" }, "message": "arch-arm: Group self hosted debug writes in ISA switch\n\nChange-Id: If9c0675743856b603e7b5ec1898f5cdd650f3ce6\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70562\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\n" }, { "commit": "32b4ab376c08b48cf973dbafc3a7119a76c642cb", "tree": "27cc118d98640dc8179f125689a16d79b2dc35f2", "parents": [ "7c735d131d2525afbff26ee34ec9db7d4e27ba12" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Feb 07 10:56:30 2023 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed May 17 08:11:06 2023 +0000" }, "message": "arch-arm: Update MISCREG_DBGDIDR to point to Armv8 debug arch\n\nChange-Id: I20691ecdaedde6740c706782635b1f9a4491dc51\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70561\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "7c735d131d2525afbff26ee34ec9db7d4e27ba12", "tree": "992e74fe5d9b909254ca9d05f62fc47ad1dd636c", "parents": [ "c85aa11ad061d7ed62fd2a1c8e5245d9b4a4680c" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Feb 07 10:03:04 2023 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed May 17 08:11:06 2023 +0000" }, "message": "arch-arm: Implement RAZ/WI with raz specifier\n\nChange-Id: I195f042fbeb10c0ca1f9095a0d26e6c213496ee5\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70560\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" }, { "commit": "c85aa11ad061d7ed62fd2a1c8e5245d9b4a4680c", "tree": "9a1d5e9bde2d63e9c3ab00b4881ebc7221eef1e7", "parents": [ "de2503f7ceae4832892d64a4440de4a97aa3e211" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Feb 07 10:29:42 2023 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed May 17 08:11:06 2023 +0000" }, "message": "arch-arm: Provide default mask for raz/rao helpers\n\nRather than forcing raz registers to write something like:\n\n.raz(uint64_t(-1))\n\nwe provide a shorter version where if\nno bitmask is specified we assume the entire register is\nraz/rao. This won\u0027t be probably used by rao but I\nam striving for symmetry and providing a default won\u0027t\nprobably hurt\n\nChange-Id: I309e345fc8336df3a74474f8f9202bf7e2095b41\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70559\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n" } ], "next": "de2503f7ceae4832892d64a4440de4a97aa3e211" }