| commit | 058e2cec7c56bf0549efff1df5974799c41cd1be | [log] [tgz] |
|---|---|---|
| author | Adrien Pesle <adrien.pesle@arm.com> | Mon Sep 03 16:43:24 2018 +0200 |
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | Mon Oct 01 08:28:51 2018 +0000 |
| tree | 0be3f4915fae6c32e017735bb4bd36cd34c6e2d4 | |
| parent | cf20e8211e2c3f1b2085c949a1e992a1f5d1071c [diff] |
dev-arm: Add basic support for level sensitive SPIs in GICv2 For level sensitive interrupt IRQ line must be cleared when interrupt is deasserted. This is not the case for edge-trigerred interrupt. Change-Id: Ib1660da74a296750c0eb9e20878d4ee64bd23130 Reviewed-on: https://gem5-review.googlesource.com/12944 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>