commit 163065d79ee6fd1b078b4301bb5d909c957071e2
author Giacomo Travaglini <giacomo.travaglini@arm.com> Mon Jan 21 14:43:11 2019 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Wed Jan 23 14:08:55 2019 +0000
tree 79dfc2ef4ec856700f45cd73b19d94d1181863bd
parent 51aba755390f96a7f1d997b1849bd47072823dea

arch-arm: IsStoreConditional flag set depending on flavor

This patch is aligning A32 with A64 where the IsStoreConditional flag
doesn't have to be specified manually in the instruction implementation,
but will be automatically added to any exclusive store.

Change-Id: Id02ed6fc2beeca6d125017393714a7c6eb3d8a33
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15816
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/arch/arm/isa/insts/str.isa

diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index c165eaf..ea412aa 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -48,8 +48,7 @@
         execBase = 'Store'
 
         def __init__(self, mnem, post, add, writeback, size=4,
-                     sign=False, user=False, flavor="normal",
-                     instFlags = []):
+                     sign=False, user=False, flavor="normal"):
             super(StoreInst, self).__init__()
 
             self.name = mnem
@@ -60,7 +59,7 @@
             self.sign = sign
             self.user = user
             self.flavor = flavor
-            self.instFlags = instFlags
+            self.instFlags = []
             if self.add:
                 self.op = " +"
             else:
@@ -185,6 +184,7 @@
                 self.memFlags.append("ArmISA::TLB::UserMode")
 
             if self.flavor == "exclusive":
+                self.instFlags.append("IsStoreConditional")
                 self.memFlags.append("Request::LLSC")
             elif self.flavor != "fp":
                 self.memFlags.append("ArmISA::TLB::AllowUnaligned")
@@ -259,6 +259,7 @@
 
             # Add memory request flags where necessary
             if self.flavor == "exclusive":
+                self.instFlags.append("IsStoreConditional")
                 self.memFlags.append("Request::LLSC")
                 self.memFlags.append("ArmISA::TLB::AlignDoubleWord")
             else:
@@ -379,14 +380,14 @@
 
     buildDoubleStores("strd")
 
-    StoreImmEx("strex", False, True, False, size=4, flavor="exclusive",
-               instFlags = ['IsStoreConditional']).emit()
-    StoreImmEx("strexh", False, True, False, size=2, flavor="exclusive",
-               instFlags = ['IsStoreConditional']).emit()
-    StoreImmEx("strexb", False, True, False, size=1, flavor="exclusive",
-               instFlags = ['IsStoreConditional']).emit()
-    StoreDoubleImmEx("strexd", False, True, False, flavor="exclusive",
-               instFlags = ['IsStoreConditional']).emit()
+    StoreImmEx("strex", False, True, False, size=4,
+               flavor="exclusive").emit()
+    StoreImmEx("strexh", False, True, False, size=2,
+               flavor="exclusive").emit()
+    StoreImmEx("strexb", False, True, False, size=1,
+               flavor="exclusive").emit()
+    StoreDoubleImmEx("strexd", False, True, False,
+                     flavor="exclusive").emit()
 
     StoreImm("vstr", False, True, False, size=4, flavor="fp").emit()
     StoreImm("vstr", False, False, False, size=4, flavor="fp").emit()