x86 regressions: stats update due to new x87 instructions
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
index f6f5195..e5a53f4 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
@@ -30,7 +30,7 @@
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -78,7 +78,6 @@
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
-isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@@ -465,9 +464,6 @@
int_slave=system.membus.master[2]
pio=system.membus.master[1]
-[system.cpu.isa]
-type=X86ISA
-
[system.cpu.itb]
type=X86TLB
children=walker
@@ -528,7 +524,7 @@
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr
index ac4ad20..f5691fd 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
index 48eb9aa..22f96a7 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:14:29
-gem5 started Oct 30 2012 16:17:19
-gem5 executing on u200540-lin
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 00:35:30
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -40,4 +42,4 @@
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 607235830000 because target called exit()
+Exiting @ tick 607445544000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
index 74f46e9..63873cc 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
@@ -1,63 +1,63 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.607236 # Number of seconds simulated
-sim_ticks 607235830000 # Number of ticks simulated
-final_tick 607235830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.607446 # Number of seconds simulated
+sim_ticks 607445544000 # Number of ticks simulated
+final_tick 607445544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 71722 # Simulator instruction rate (inst/s)
-host_op_rate 132152 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 49489751 # Simulator tick rate (ticks/s)
-host_mem_usage 226812 # Number of bytes of host memory used
-host_seconds 12269.93 # Real time elapsed on the host
+host_inst_rate 57635 # Simulator instruction rate (inst/s)
+host_op_rate 106195 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 39782943 # Simulator tick rate (ticks/s)
+host_mem_usage 279268 # Number of bytes of host memory used
+host_seconds 15268.99 # Real time elapsed on the host
sim_insts 880025277 # Number of instructions simulated
-sim_ops 1621493925 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 57472 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1693120 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1750592 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 57472 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 57472 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory
-system.physmem.bytes_written::total 162112 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 898 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 26455 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 27353 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 94645 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2788241 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2882887 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 94645 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 94645 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 266967 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 266967 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 266967 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 94645 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2788241 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3149854 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 27355 # Total number of read requests seen
-system.physmem.writeReqs 2533 # Total number of write requests seen
-system.physmem.cpureqs 29888 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 1750592 # Total number of bytes read from memory
-system.physmem.bytesWritten 162112 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 1750592 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize()
+sim_ops 1621493926 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 57728 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1693184 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1750912 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 57728 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 57728 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 162176 # Number of bytes written to this memory
+system.physmem.bytes_written::total 162176 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 902 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 26456 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 27358 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 2534 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 2534 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 95034 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2787384 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2882418 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 95034 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 95034 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 266980 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 266980 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 266980 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 95034 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2787384 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3149398 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 27359 # Total number of read requests seen
+system.physmem.writeReqs 2534 # Total number of write requests seen
+system.physmem.cpureqs 29893 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1750912 # Total number of bytes read from memory
+system.physmem.bytesWritten 162176 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 1750912 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 162176 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 1747 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 1689 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 1686 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 1672 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 1754 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 1754 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 1753 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1755 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 1779 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 1777 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 1808 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 1776 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 1809 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 1712 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 1664 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 1638 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 1660 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 1666 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 1668 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 1691 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 1661 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 1667 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 1672 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 1692 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 1676 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 162 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis
@@ -72,19 +72,19 @@
system.physmem.perBankWrReqs::10 154 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 153 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 154 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 154 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 155 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 156 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 156 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 607235813000 # Total gap between requests
+system.physmem.totGap 607445529000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 27355 # Categorize read packet sizes
+system.physmem.readPktSize::6 27359 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -93,7 +93,7 @@
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 2533 # categorize write packet sizes
+system.physmem.writePktSize::6 2534 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
@@ -105,9 +105,9 @@
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 26898 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 336 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 95 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 26894 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 345 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 94 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
@@ -141,7 +141,7 @@
system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 110 # What write queue length does an incoming req see
@@ -171,14 +171,14 @@
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 67414668 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 820820668 # Sum of mem lat for all requests
-system.physmem.totBusLat 109420000 # Total cycles spent in databus access
-system.physmem.totBankLat 643986000 # Total cycles spent in bank access
-system.physmem.avgQLat 2464.44 # Average queueing delay per request
-system.physmem.avgBankLat 23541.80 # Average bank access latency per request
+system.physmem.totQLat 68456169 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 822256169 # Sum of mem lat for all requests
+system.physmem.totBusLat 109436000 # Total cycles spent in databus access
+system.physmem.totBankLat 644364000 # Total cycles spent in bank access
+system.physmem.avgQLat 2502.14 # Average queueing delay per request
+system.physmem.avgBankLat 23552.18 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 30006.24 # Average memory access latency
+system.physmem.avgMemAccLat 30054.32 # Average memory access latency
system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s
@@ -186,593 +186,451 @@
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 4.32 # Average write queue length over time
-system.physmem.readRowHits 17706 # Number of row buffer hits during reads
-system.physmem.writeRowHits 1086 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 64.73 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 42.87 # Row buffer hit rate for writes
-system.physmem.avgGap 20317044.06 # Average gap between requests
+system.physmem.avgWrQLen 6.29 # Average write queue length over time
+system.physmem.readRowHits 17697 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1084 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 64.68 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 42.78 # Row buffer hit rate for writes
+system.physmem.avgGap 20320661.33 # Average gap between requests
system.cpu.workload.num_syscalls 48 # Number of system calls
-system.cpu.numCycles 1214471661 # number of cpu cycles simulated
+system.cpu.numCycles 1214891089 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 158566645 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 158566645 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 26386333 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 83466743 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 83279512 # Number of BTB hits
+system.cpu.BPredUnit.lookups 158385701 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 158385701 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 26390414 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 84292336 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 84079165 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 179036467 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1457944289 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 158566645 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 83279512 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 399021545 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 88092537 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 574509498 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 50 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 341 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 186960601 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 10940939 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1214117357 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.059847 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.253407 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 179135724 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1458430747 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 158385701 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 84079165 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 399080479 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 88232216 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 574634439 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 381 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 187842502 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 11743850 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1214538068 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.059666 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.253312 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 822311931 67.73% 67.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 26973525 2.22% 69.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 13085420 1.08% 71.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 20645432 1.70% 72.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 26636403 2.19% 74.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 18254688 1.50% 76.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 31306986 2.58% 79.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 39069186 3.22% 82.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 215833786 17.78% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 822675210 67.74% 67.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 26883309 2.21% 69.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 13192065 1.09% 71.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 20566257 1.69% 72.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 26639433 2.19% 74.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 18282936 1.51% 76.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 31338155 2.58% 79.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 39109954 3.22% 82.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 215850749 17.77% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1214117357 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.130564 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.200476 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 288149545 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 497851788 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 274001581 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 92564987 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 61549456 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2343342483 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 61549456 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 336776305 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 124136399 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 2472 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 303957244 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 387695481 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2247540252 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 338 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 242690737 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 120190709 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2617793255 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5721514338 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 5721508630 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 5708 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 1886895257 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 730897998 # Number of HB maps that are undone due to squashing
+system.cpu.fetch.rateDist::total 1214538068 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.130370 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.200462 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 288247470 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 497953946 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 274080522 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 92569137 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 61686993 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 2343830219 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 61686993 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 336887109 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 124143934 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 2487 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 304057721 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 387759824 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2248180627 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 354 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 242798221 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 120202889 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 2618438730 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5723603734 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 5723598334 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 5400 # Number of floating rename lookups
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+system.cpu.rename.UndoneMaps 731543472 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 87 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 731315186 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 531685334 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 219218078 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 341957322 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 144669482 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1993566712 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 286 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1783999852 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 259167 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 371673921 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 759176081 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 236 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1214117357 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.469380 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.421908 # Number of insts issued each cycle
+system.cpu.rename.skidInsts 731379517 # count of insts added to the skid buffer
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+system.cpu.memDep0.conflictingStores 144686488 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 1994506429 # Number of instructions added to the IQ (excludes non-spec)
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+system.cpu.iq.iqInstsIssued 1784080761 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 243450 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 372613756 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 761627172 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::1 364096004 29.99% 59.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 234218772 19.29% 78.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 141579875 11.66% 90.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 60576135 4.99% 95.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 39770363 3.28% 98.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 11069235 0.91% 99.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 2042198 0.17% 99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 607441 0.05% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 360345167 29.67% 29.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 364336445 30.00% 59.67% # Number of insts issued each cycle
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+system.cpu.iq.issued_per_cycle::3 141446603 11.65% 90.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 60702765 5.00% 95.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 39742301 3.27% 98.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 11032116 0.91% 99.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 2048046 0.17% 99.95% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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-system.cpu.iq.fu_full::IntMult 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 2239769 77.53% 93.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 201121 6.96% 100.00% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.09% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 2259609 77.90% 92.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 203424 7.01% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 46812236 2.62% 2.62% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1065749303 59.74% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 478900937 26.84% 89.21% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 192537376 10.79% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 46812462 2.62% 2.62% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1065847679 59.74% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 478866421 26.84% 89.21% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 192554199 10.79% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1783999852 # Type of FU issued
-system.cpu.iq.rate 1.468951 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2888934 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.001619 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4785264711 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2365417546 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1724692001 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 451 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1804 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 116 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1740076331 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 219 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 209988104 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1784080761 # Type of FU issued
+system.cpu.iq.rate 1.468511 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2900605 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.001626 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4785843295 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2367295034 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1724820361 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 350 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1704 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 92 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1740168733 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 171 # Number of floating point alu accesses
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system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 112643213 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 39222 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 182717 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 31032021 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 113016880 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 39297 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 180469 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 31115283 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2338 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 61 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2481 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 68 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 61549456 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1140639 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 111456 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1993566998 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 62891461 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 531685334 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 219218078 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 82 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 54713 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 2863 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 182717 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 2045566 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 24470672 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 26516238 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1766182455 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 474610807 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 17817397 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 61686993 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1142263 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 110648 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 1994506717 # Number of instructions dispatched to IQ
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+system.cpu.iew.iewIQFullEvents 54039 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 2855 # Number of times the LSQ has become full, causing a stall
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+system.cpu.iew.predictedTakenIncorrect 2045569 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 24474359 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 26519928 # Number of branch mispredicts detected at execute
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system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 666317556 # number of memory reference insts executed
-system.cpu.iew.exec_branches 110350315 # Number of branches executed
-system.cpu.iew.exec_stores 191706749 # Number of stores executed
-system.cpu.iew.exec_rate 1.454281 # Inst execution rate
-system.cpu.iew.wb_sent 1725793430 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1724692117 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1267138729 # num instructions producing a value
-system.cpu.iew.wb_consumers 1828924593 # num instructions consuming a value
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+system.cpu.iew.wb_sent 1725940615 # cumulative count of insts sent to commit
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+system.cpu.iew.wb_producers 1267203875 # num instructions producing a value
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.420117 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.692833 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.419733 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.692799 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 372074312 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 26386383 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1152567901 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.406853 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.830346 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 373014217 # The number of squashed insts skipped by commit
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+system.cpu.commit.committed_per_cycle::stdev 1.830012 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 417955350 36.26% 36.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 415054079 36.01% 72.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 86939331 7.54% 79.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 122127082 10.60% 90.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 24184880 2.10% 92.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 25402622 2.20% 94.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 16383099 1.42% 96.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 12042950 1.04% 97.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 32478508 2.82% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 418199685 36.28% 36.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 415017727 36.00% 72.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 87014149 7.55% 79.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 122172880 10.60% 90.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 24164674 2.10% 92.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 25337442 2.20% 94.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 16460362 1.43% 96.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 12052065 1.05% 97.19% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1152567901 # Number of insts commited each cycle
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system.cpu.commit.committedInsts 880025277 # Number of instructions committed
-system.cpu.commit.committedOps 1621493925 # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps 1621493926 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
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+system.cpu.commit.refs 607228179 # Number of memory references committed
system.cpu.commit.loads 419042121 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 107161574 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 1621354435 # Number of committed integer instructions.
+system.cpu.commit.int_insts 1621354437 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 32478508 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 32432091 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3113657630 # The number of ROB reads
-system.cpu.rob.rob_writes 4048721682 # The number of ROB writes
-system.cpu.timesIdled 59087 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 354304 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3114927127 # The number of ROB reads
+system.cpu.rob.rob_writes 4050738571 # The number of ROB writes
+system.cpu.timesIdled 58873 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 353021 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 880025277 # Number of Instructions Simulated
-system.cpu.committedOps 1621493925 # Number of Ops (including micro ops) Simulated
+system.cpu.committedOps 1621493926 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated
-system.cpu.cpi 1.380042 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.380042 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.724616 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.724616 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3542913524 # number of integer regfile reads
-system.cpu.int_regfile_writes 1974599259 # number of integer regfile writes
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-system.cpu.misc_regfile_reads 910763104 # number of misc regfile reads
-system.cpu.icache.replacements 26 # number of replacements
-system.cpu.icache.tagsinuse 814.074374 # Cycle average of tags in use
-system.cpu.icache.total_refs 186959214 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 915 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 204327.009836 # Average number of references to valid blocks.
+system.cpu.cpi 1.380518 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.380518 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.724366 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.724366 # IPC: Total IPC of All Threads
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+system.cpu.icache.avg_refs 206418.805495 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 814.074374 # Average occupied blocks per requestor
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46195.872556 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 46195.872556 # average ReadReq miss latency
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-system.cpu.icache.blocked_cycles::no_mshrs 249 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses
@@ -781,14 +639,156 @@
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
index 065406d..6f8b69a 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
@@ -10,7 +10,7 @@
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -68,13 +68,13 @@
[system.cpu.dtb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
-clock=1
+clock=500
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@@ -91,7 +91,7 @@
[system.cpu.itb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.membus.slave[3]
@@ -129,9 +129,9 @@
[system.physmem]
type=SimpleMemory
-clock=1
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr
index ac4ad20..f5691fd 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
index 128fee1..c175f03 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
@@ -3,8 +3,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 22:29:00
-gem5 started Sep 10 2012 22:29:07
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 00:35:29
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
@@ -41,4 +41,4 @@
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 963992671000 because target called exit()
+Exiting @ tick 963992671500 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
index bf8fc96..5647e6e 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
@@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.963993 # Number of seconds simulated
-sim_ticks 963992671000 # Number of ticks simulated
-final_tick 963992671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 963992671500 # Number of ticks simulated
+final_tick 963992671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 939514 # Simulator instruction rate (inst/s)
-host_op_rate 1731105 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1029157174 # Simulator tick rate (ticks/s)
-host_mem_usage 266280 # Number of bytes of host memory used
-host_seconds 936.68 # Real time elapsed on the host
+host_inst_rate 908989 # Simulator instruction rate (inst/s)
+host_op_rate 1674860 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 995719480 # Simulator tick rate (ticks/s)
+host_mem_usage 267620 # Number of bytes of host memory used
+host_seconds 968.14 # Real time elapsed on the host
sim_insts 880025278 # Number of instructions simulated
-sim_ops 1621493926 # Number of ops (including micro ops) simulated
+sim_ops 1621493927 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 9492133560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1842452909 # Number of bytes read from this memory
system.physmem.bytes_read::total 11334586469 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 9492133560 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 9492133560 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 864451000 # Number of bytes written to this memory
-system.physmem.bytes_written::total 864451000 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 864451002 # Number of bytes written to this memory
+system.physmem.bytes_written::total 864451002 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1186516695 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 419042121 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1605558816 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 188186057 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 188186057 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 9846686438 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1911272735 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 11757959173 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 9846686438 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 9846686438 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 896740220 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 896740220 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 9846686438 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2808012955 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 12654699393 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_writes::cpu.data 188186058 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 188186058 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 9846686433 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1911272734 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 11757959167 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 9846686433 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 9846686433 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 896740222 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 896740222 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 9846686433 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2808012956 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 12654699389 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls
-system.cpu.numCycles 1927985343 # number of cpu cycles simulated
+system.cpu.numCycles 1927985344 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 880025278 # Number of instructions committed
-system.cpu.committedOps 1621493926 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 1621354436 # Number of integer alu accesses
+system.cpu.committedOps 1621493927 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 1621354438 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls
-system.cpu.num_int_insts 1621354436 # number of integer instructions
+system.cpu.num_int_insts 1621354438 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 4204103507 # number of times the integer registers were read
-system.cpu.num_int_register_writes 1886895257 # number of times the integer registers were written
+system.cpu.num_int_register_reads 4204103512 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1886895258 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 607228178 # number of memory refs
+system.cpu.num_mem_refs 607228179 # number of memory refs
system.cpu.num_load_insts 419042121 # Number of load instructions
-system.cpu.num_store_insts 188186057 # Number of store instructions
+system.cpu.num_store_insts 188186058 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 1927985343 # Number of busy cycles
+system.cpu.num_busy_cycles 1927985344 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
index fe83ea7..1561748 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
@@ -10,7 +10,7 @@
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -61,21 +61,22 @@
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=2
size=262144
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
@@ -90,7 +91,7 @@
[system.cpu.dtb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.cpu.toL2Bus.slave[3]
@@ -99,21 +100,22 @@
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=2
size=131072
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
@@ -122,7 +124,7 @@
[system.cpu.interrupts]
type=X86LocalApic
-clock=1
+clock=500
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@@ -139,30 +141,31 @@
[system.cpu.itb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=20
size=2097152
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
@@ -172,10 +175,10 @@
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@@ -213,9 +216,9 @@
[system.physmem]
type=SimpleMemory
-clock=1
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr
index ac4ad20..f5691fd 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
index 02ca976..ad62c8d 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
@@ -3,8 +3,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 22:29:00
-gem5 started Sep 10 2012 22:43:43
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 00:35:29
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
@@ -41,4 +41,4 @@
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 1801979679000 because target called exit()
+Exiting @ tick 1800193397000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
index ea680ba..87bad38 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.800193 # Number of seconds simulated
-sim_ticks 1800193396000 # Number of ticks simulated
-final_tick 1800193396000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 1800193397000 # Number of ticks simulated
+final_tick 1800193397000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 332254 # Simulator instruction rate (inst/s)
-host_op_rate 612196 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 679663607 # Simulator tick rate (ticks/s)
-host_mem_usage 227800 # Number of bytes of host memory used
-host_seconds 2648.65 # Real time elapsed on the host
+host_inst_rate 477976 # Simulator instruction rate (inst/s)
+host_op_rate 880696 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 977754272 # Simulator tick rate (ticks/s)
+host_mem_usage 276196 # Number of bytes of host memory used
+host_seconds 1841.15 # Real time elapsed on the host
sim_insts 880025278 # Number of instructions simulated
-sim_ops 1621493926 # Number of ops (including micro ops) simulated
+sim_ops 1621493927 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1682368 # Number of bytes read from this memory
system.physmem.bytes_read::total 1728576 # Number of bytes read from this memory
@@ -35,26 +35,26 @@
system.physmem.bw_total::cpu.data 934548 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1049487 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls
-system.cpu.numCycles 3600386792 # number of cpu cycles simulated
+system.cpu.numCycles 3600386794 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 880025278 # Number of instructions committed
-system.cpu.committedOps 1621493926 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 1621354436 # Number of integer alu accesses
+system.cpu.committedOps 1621493927 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 1621354438 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls
-system.cpu.num_int_insts 1621354436 # number of integer instructions
+system.cpu.num_int_insts 1621354438 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 4204103507 # number of times the integer registers were read
-system.cpu.num_int_register_writes 1886895257 # number of times the integer registers were written
+system.cpu.num_int_register_reads 4204103512 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1886895258 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 607228178 # number of memory refs
+system.cpu.num_mem_refs 607228179 # number of memory refs
system.cpu.num_load_insts 419042121 # Number of load instructions
-system.cpu.num_store_insts 188186057 # Number of store instructions
+system.cpu.num_store_insts 188186058 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 3600386792 # Number of busy cycles
+system.cpu.num_busy_cycles 3600386794 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 4 # number of replacements
@@ -136,22 +136,22 @@
system.cpu.icache.overall_avg_mshr_miss_latency::total 53002.770083 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 437952 # number of replacements
-system.cpu.dcache.tagsinuse 4094.905744 # Cycle average of tags in use
-system.cpu.dcache.total_refs 606786130 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 4094.905742 # Cycle average of tags in use
+system.cpu.dcache.total_refs 606786131 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 1372.670230 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 771786000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4094.905744 # Average occupied blocks per requestor
+system.cpu.dcache.avg_refs 1372.670233 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 771787000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4094.905742 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 418844795 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 418844795 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 187941335 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 187941335 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 606786130 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 606786130 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 606786130 # number of overall hits
-system.cpu.dcache.overall_hits::total 606786130 # number of overall hits
+system.cpu.dcache.WriteReq_hits::cpu.data 187941336 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 187941336 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 606786131 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 606786131 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 606786131 # number of overall hits
+system.cpu.dcache.overall_hits::total 606786131 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 197326 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 197326 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 244722 # number of WriteReq misses
@@ -170,12 +170,12 @@
system.cpu.dcache.overall_miss_latency::total 6851581000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 419042121 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 419042121 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 607228178 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 607228178 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 607228178 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 607228178 # number of overall (read+write) accesses
+system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 607228179 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 607228179 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 607228179 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 607228179 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000471 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses
@@ -236,14 +236,14 @@
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2532 # number of replacements
-system.cpu.l2cache.tagsinuse 22211.029339 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 22211.029327 # Cycle average of tags in use
system.cpu.l2cache.total_refs 519268 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 21.788687 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 21021.301366 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks 21021.301355 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 643.199216 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 546.528757 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 546.528756 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.641519 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.019629 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.016679 # Average percentage of cache occupancy
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
index b0792be..4d1a878 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -30,7 +30,7 @@
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -78,7 +78,6 @@
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
-isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@@ -465,9 +464,6 @@
int_slave=system.membus.master[2]
pio=system.membus.master[1]
-[system.cpu.isa]
-type=X86ISA
-
[system.cpu.itb]
type=X86TLB
children=walker
@@ -528,9 +524,9 @@
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
index ac4ad20..f5691fd 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
index d71b96b..0aa3d6e 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:14:29
-gem5 started Oct 30 2012 16:29:18
-gem5 executing on u200540-lin
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 00:35:30
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -23,4 +25,4 @@
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 66000220500 because target called exit()
+Exiting @ tick 65982862500 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 80c10d7..1e22e45 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.066000 # Number of seconds simulated
-sim_ticks 66000220500 # Number of ticks simulated
-final_tick 66000220500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.065983 # Number of seconds simulated
+sim_ticks 65982862500 # Number of ticks simulated
+final_tick 65982862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 92408 # Simulator instruction rate (inst/s)
-host_op_rate 162716 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 38603772 # Simulator tick rate (ticks/s)
-host_mem_usage 361664 # Number of bytes of host memory used
-host_seconds 1709.68 # Real time elapsed on the host
+host_inst_rate 71115 # Simulator instruction rate (inst/s)
+host_op_rate 125222 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 29700736 # Simulator tick rate (ticks/s)
+host_mem_usage 413360 # Number of bytes of host memory used
+host_seconds 2221.59 # Real time elapsed on the host
sim_insts 157988547 # Number of instructions simulated
-sim_ops 278192462 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 64832 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1881344 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1946176 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 64832 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 64832 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9344 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9344 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1013 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 29396 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 30409 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 146 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 146 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 982300 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 28505117 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 29487417 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 982300 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 982300 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 141575 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 141575 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 141575 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 982300 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 28505117 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 29628992 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 30411 # Total number of read requests seen
-system.physmem.writeReqs 146 # Total number of write requests seen
-system.physmem.cpureqs 30558 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 1946176 # Total number of bytes read from memory
-system.physmem.bytesWritten 9344 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 1946176 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 9344 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 46 # Number of read reqs serviced by write Q
+sim_ops 278192463 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1883072 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1948288 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 11136 # Number of bytes written to this memory
+system.physmem.bytes_written::total 11136 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 1019 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 29423 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 30442 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 174 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 174 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 988378 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 28538804 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 29527182 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 988378 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 988378 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 168771 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 168771 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 168771 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 988378 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 28538804 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 29695953 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 30444 # Total number of read requests seen
+system.physmem.writeReqs 174 # Total number of write requests seen
+system.physmem.cpureqs 30619 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1948288 # Total number of bytes read from memory
+system.physmem.bytesWritten 11136 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 1948288 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 11136 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 1914 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 2026 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 1920 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 2031 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 1924 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1999 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 1961 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1964 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 1870 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 1865 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 1866 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 1859 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 1922 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 1899 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 1824 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 1923 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1903 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 1827 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 1881 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 1910 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1876 # Track reads on a per bank basis
@@ -61,15 +61,15 @@
system.physmem.perBankRdReqs::15 1770 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 93 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 6 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 5 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 4 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 11 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 6 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 7 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 7 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 14 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 14 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 1 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 11 # Track writes on a per bank basis
@@ -77,14 +77,14 @@
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 66000206500 # Total gap between requests
+system.physmem.totGap 65982842000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 30411 # Categorize read packet sizes
+system.physmem.readPktSize::6 30444 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -93,7 +93,7 @@
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 146 # categorize write packet sizes
+system.physmem.writePktSize::6 174 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
@@ -105,11 +105,11 @@
system.physmem.neitherpktsize::6 1 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 29839 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 401 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 29860 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 399 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 98 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -138,29 +138,29 @@
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
@@ -171,125 +171,126 @@
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 10043842 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 570319842 # Sum of mem lat for all requests
-system.physmem.totBusLat 121460000 # Total cycles spent in databus access
-system.physmem.totBankLat 438816000 # Total cycles spent in bank access
-system.physmem.avgQLat 330.77 # Average queueing delay per request
-system.physmem.avgBankLat 14451.37 # Average bank access latency per request
+system.physmem.totQLat 10444357 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 571602357 # Sum of mem lat for all requests
+system.physmem.totBusLat 121544000 # Total cycles spent in databus access
+system.physmem.totBankLat 439614000 # Total cycles spent in bank access
+system.physmem.avgQLat 343.72 # Average queueing delay per request
+system.physmem.avgBankLat 14467.65 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 18782.15 # Average memory access latency
-system.physmem.avgRdBW 29.49 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 0.14 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 29.49 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 0.14 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 18811.37 # Average memory access latency
+system.physmem.avgRdBW 29.53 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 29.53 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.17 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.19 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 11.23 # Average write queue length over time
-system.physmem.readRowHits 29628 # Number of row buffer hits during reads
-system.physmem.writeRowHits 33 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 97.57 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 22.60 # Row buffer hit rate for writes
-system.physmem.avgGap 2159904.65 # Average gap between requests
+system.physmem.avgWrQLen 11.24 # Average write queue length over time
+system.physmem.readRowHits 29640 # Number of row buffer hits during reads
+system.physmem.writeRowHits 45 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 97.54 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 25.86 # Row buffer hit rate for writes
+system.physmem.avgGap 2155034.36 # Average gap between requests
system.cpu.workload.num_syscalls 444 # Number of system calls
-system.cpu.numCycles 132000442 # number of cpu cycles simulated
+system.cpu.numCycles 131965726 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 34554509 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 34554509 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 911394 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 24765022 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 24662055 # Number of BTB hits
+system.cpu.BPredUnit.lookups 34537566 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 34537566 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 909846 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 24744786 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 24642661 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 26596332 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 185596643 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 34554509 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 24662055 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 56507097 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6124499 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 43643381 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 161 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 25948459 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 189220 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 131924094 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.485407 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.326719 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 26601820 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 185569905 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 34537566 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 24642661 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 56492855 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6109576 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 43628030 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 159 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 25952050 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 188970 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 131886743 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.485312 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.326723 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 77963907 59.10% 59.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1995685 1.51% 60.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2954745 2.24% 62.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 3921734 2.97% 65.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 7794021 5.91% 71.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 4758298 3.61% 75.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2730030 2.07% 77.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1578417 1.20% 78.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 28227257 21.40% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 77942049 59.10% 59.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1996023 1.51% 60.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2954192 2.24% 62.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 3924230 2.98% 65.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 7791327 5.91% 71.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 4757391 3.61% 75.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2730462 2.07% 77.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1561040 1.18% 78.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 28230029 21.40% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 131924094 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.261776 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.406030 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 37436709 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 35891345 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 44770440 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 8648508 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 5177092 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 324637130 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 5177092 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 43002137 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 8530644 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 9064 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 47590207 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 27614950 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 320247590 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 230 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 56685 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 25740543 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 371 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 322254877 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 849337194 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 849335025 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 2169 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 279212744 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 43042133 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 470 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 464 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 62360742 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 102568175 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 35245114 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 39579817 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 6021711 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 315893152 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1659 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 302191539 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 115107 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 37070468 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 54283440 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1213 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 131924094 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.290647 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.699813 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 131886743 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.261716 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.406198 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 37433496 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 35884188 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 44759605 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 8645670 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 5163784 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 324546222 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 5163784 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 42999384 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 8526748 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 9161 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 47575820 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 27611846 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 320149985 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 225 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 53569 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 25749083 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 361 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 322162823 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 849088667 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 849086832 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1835 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 279212745 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 42950078 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 468 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 462 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 62353215 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 102529083 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 35255084 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 39579305 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 5971941 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 315806334 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1679 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 302165189 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 115128 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 36987116 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 54145851 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1234 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 131886743 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.291096 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.700528 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 24546585 18.61% 18.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 23206107 17.59% 36.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 25921610 19.65% 55.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 25807341 19.56% 75.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 18909357 14.33% 89.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 8337371 6.32% 96.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 4135132 3.13% 99.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 899614 0.68% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 160977 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 24537309 18.60% 18.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 23216690 17.60% 36.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 25879367 19.62% 55.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 25801755 19.56% 75.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 18920728 14.35% 89.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 8321327 6.31% 96.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 4137839 3.14% 99.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 905905 0.69% 99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 165823 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 131924094 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 131886743 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 38482 1.96% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 38358 1.96% 1.96% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available
@@ -318,12 +319,12 @@
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1831710 93.52% 95.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 88409 4.51% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1830721 93.50% 95.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 88976 4.54% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 31296 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 171161443 56.64% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 31295 0.01% 0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 171151869 56.64% 56.65% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.65% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.65% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 35 0.00% 56.65% # Type of FU issued
@@ -352,285 +353,393 @@
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 97760077 32.35% 89.00% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 33238688 11.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 97747173 32.35% 89.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 33234817 11.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 302191539 # Type of FU issued
-system.cpu.iq.rate 2.289322 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1958601 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006481 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 738380204 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 352997189 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 299552936 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 676 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1019 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 193 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 304118533 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 311 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 53992044 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 302165189 # Type of FU issued
+system.cpu.iq.rate 2.289725 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1958055 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.006480 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 738289800 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 352827074 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 299525455 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 504 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 863 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 154 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 304091716 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 233 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 54002404 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 11788791 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 25892 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 34061 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 3805363 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 11749699 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 26201 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 33919 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 3815332 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 3223 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 8493 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 3226 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 8521 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 5177092 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1727451 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 159578 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 315894811 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 195834 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 102568175 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 35245114 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 3211 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 73329 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 34061 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 522882 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 446154 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 969036 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 300573249 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 97290254 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1618290 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 5163784 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1727826 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 159628 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 315808013 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 197001 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 130308372 # number of memory reference insts executed
-system.cpu.iew.exec_branches 30889144 # Number of branches executed
-system.cpu.iew.exec_stores 33018118 # Number of stores executed
-system.cpu.iew.exec_rate 2.277062 # Inst execution rate
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-system.cpu.iew.wb_count 299553129 # cumulative count of insts written-back
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-system.cpu.iew.wb_consumers 298002309 # num instructions consuming a value
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.269334 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.736581 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.269723 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.736636 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 37715212 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
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-system.cpu.commit.committed_per_cycle::1 19282988 15.21% 61.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 11825828 9.33% 70.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 9598483 7.57% 78.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1735999 1.37% 79.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 2077835 1.64% 81.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1295284 1.02% 82.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 717786 0.57% 82.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 22041624 17.39% 100.00% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::3 9592484 7.57% 78.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1741744 1.37% 79.38% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.committedInsts 157988547 # Number of instructions committed
-system.cpu.commit.committedOps 278192462 # Number of ops (including micro ops) committed
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.loads 90779384 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 29309705 # Number of branches committed
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 278186170 # Number of committed integer instructions.
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system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 22041624 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 22046111 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 420613052 # The number of ROB reads
-system.cpu.rob.rob_writes 636997439 # The number of ROB writes
-system.cpu.timesIdled 13642 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 76348 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 420497824 # The number of ROB reads
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+system.cpu.timesIdled 13700 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 78983 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 157988547 # Number of Instructions Simulated
-system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated
+system.cpu.committedOps 278192463 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated
-system.cpu.cpi 0.835506 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.835506 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.196879 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.196879 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 592880828 # number of integer regfile reads
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-system.cpu.fp_regfile_writes 79 # number of floating regfile writes
-system.cpu.misc_regfile_reads 192706911 # number of misc regfile reads
-system.cpu.icache.replacements 61 # number of replacements
-system.cpu.icache.tagsinuse 834.549611 # Cycle average of tags in use
-system.cpu.icache.total_refs 25947121 # Total number of references to valid blocks.
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+system.cpu.cpi 0.835287 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.835287 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.197194 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.197194 # IPC: Total IPC of All Threads
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.icache.occ_percent::total 0.407495 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 25947121 # number of ReadReq hits
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-system.cpu.icache.overall_hits::total 25947121 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1338 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1338 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1338 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1338 # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::total 1338 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 65589000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 65589000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 65589000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 65589000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 65589000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 65589000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 25948459 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 25948459 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 25948459 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 25948459 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 25948459 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 25948459 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 836.141366 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.408272 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.408272 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 25950700 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 25950700 # number of ReadReq hits
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+system.cpu.icache.demand_hits::total 25950700 # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total 25950700 # number of overall hits
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+system.cpu.icache.overall_misses::total 1350 # number of overall misses
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+system.cpu.icache.ReadReq_accesses::cpu.inst 25952050 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49020.179372 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 49020.179372 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 49020.179372 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 49020.179372 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 49020.179372 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 49020.179372 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 78 # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48353.333333 # average ReadReq miss latency
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+system.cpu.icache.demand_avg_miss_latency::total 48353.333333 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 48353.333333 # average overall miss latency
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-system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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+system.cpu.icache.avg_blocked_cycles::no_mshrs 48.600000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 308 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 308 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 308 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 308 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 308 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 308 # number of overall MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses::total 1030 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 1030 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 1030 # number of demand (read+write) MSHR misses
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-system.cpu.icache.overall_mshr_misses::total 1030 # number of overall MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::total 51699000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51699000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 51699000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51699000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 51699000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 310 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 310 # number of ReadReq MSHR hits
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+system.cpu.icache.overall_mshr_hits::total 310 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50193.203883 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50193.203883 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50193.203883 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 50193.203883 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50193.203883 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 50193.203883 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50076.923077 # average ReadReq mshr miss latency
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+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50076.923077 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 50076.923077 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50076.923077 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 50076.923077 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 454 # number of replacements
-system.cpu.l2cache.tagsinuse 20802.546521 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 4028808 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 30388 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 132.578913 # Average number of references to valid blocks.
+system.cpu.dcache.replacements 2072071 # number of replacements
+system.cpu.dcache.tagsinuse 4072.565348 # Cycle average of tags in use
+system.cpu.dcache.total_refs 71946755 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 2076167 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 34.653645 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 21155511000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4072.565348 # Average occupied blocks per requestor
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+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49884.690873 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41472.982158 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 41754.532913 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49884.690873 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41472.982158 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 41754.532913 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -639,168 +748,60 @@
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 146 # number of writebacks
-system.cpu.l2cache.writebacks::total 146 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1013 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 400 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 1413 # number of ReadReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks 174 # number of writebacks
+system.cpu.l2cache.writebacks::total 174 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1019 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 424 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1443 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28998 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 28998 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 1013 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 29398 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 30411 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 1013 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 29398 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 30411 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 37745579 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14639611 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52385190 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29001 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 29001 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 1019 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 29425 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 30444 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 29425 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 30444 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 37999583 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15880149 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53879732 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 824070390 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 824070390 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37745579 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 838710001 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 876455580 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37745579 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 838710001 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 876455580 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984451 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000201 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000708 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 824195395 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 824195395 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37999583 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 840075544 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 878075127 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37999583 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 840075544 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 878075127 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.980751 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000213 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000723 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352585 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352585 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984451 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014160 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.014640 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984451 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014160 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.014640 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37261.183613 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 36599.027500 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37073.736730 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352690 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352690 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.980751 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014173 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.014656 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.980751 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014173 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.014656 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37291.052993 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37453.181604 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37338.691615 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28418.180219 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28418.180219 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37261.183613 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28529.491836 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28820.347243 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37261.183613 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28529.491836 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28820.347243 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28419.550878 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28419.550878 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37291.052993 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28549.721121 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28842.304789 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37291.052993 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28549.721121 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28842.304789 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 2072087 # number of replacements
-system.cpu.dcache.tagsinuse 4072.565599 # Cycle average of tags in use
-system.cpu.dcache.total_refs 71969114 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 2076183 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 34.664148 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 21167717000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4072.565599 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.994279 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.994279 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 40627633 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 40627633 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 31341474 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 31341474 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 71969107 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 71969107 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 71969107 # number of overall hits
-system.cpu.dcache.overall_hits::total 71969107 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2625254 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2625254 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 98277 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 98277 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2723531 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2723531 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2723531 # number of overall misses
-system.cpu.dcache.overall_misses::total 2723531 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 31319760000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 31319760000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 2088062998 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 2088062998 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 33407822998 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 33407822998 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 33407822998 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 33407822998 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 43252887 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 43252887 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 74692638 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 74692638 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 74692638 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 74692638 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060695 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.060695 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.036463 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.036463 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.036463 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.036463 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.182756 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.182756 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21246.710807 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 21246.710807 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12266.364142 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12266.364142 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12266.364142 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12266.364142 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 32155 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 9466 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.396894 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 2066445 # number of writebacks
-system.cpu.dcache.writebacks::total 2066445 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631206 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 631206 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16138 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 16138 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 647344 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 647344 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 647344 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 647344 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994048 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1994048 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82139 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 82139 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2076187 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2076187 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2076187 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2076187 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21982292500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 21982292500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1812892498 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1812892498 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23795184998 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 23795184998 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23795184998 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 23795184998 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046102 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046102 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002613 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002613 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027796 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.027796 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027796 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.027796 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11023.953536 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.953536 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22071.032007 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22071.032007 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11461.002789 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11461.002789 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11461.002789 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11461.002789 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
index 21c7d02..93f7366 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
@@ -10,7 +10,7 @@
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -68,13 +68,13 @@
[system.cpu.dtb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
-clock=1
+clock=500
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@@ -91,7 +91,7 @@
[system.cpu.itb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.membus.slave[3]
@@ -129,9 +129,9 @@
[system.physmem]
type=SimpleMemory
-clock=1
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
index ac4ad20..f5691fd 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
index 809429d..20b1e73 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
@@ -3,8 +3,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 22:29:00
-gem5 started Sep 10 2012 22:54:55
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 00:45:38
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
@@ -25,4 +25,4 @@
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 168950039000 because target called exit()
+Exiting @ tick 168950039500 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
index 0a05e58..e854ab4 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
@@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.168950 # Number of seconds simulated
-sim_ticks 168950039000 # Number of ticks simulated
-final_tick 168950039000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 168950039500 # Number of ticks simulated
+final_tick 168950039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 917389 # Simulator instruction rate (inst/s)
-host_op_rate 1615374 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 981038557 # Simulator tick rate (ticks/s)
-host_mem_usage 400492 # Number of bytes of host memory used
-host_seconds 172.22 # Real time elapsed on the host
+host_inst_rate 911205 # Simulator instruction rate (inst/s)
+host_op_rate 1604486 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 974425819 # Simulator tick rate (ticks/s)
+host_mem_usage 402856 # Number of bytes of host memory used
+host_seconds 173.38 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
-sim_ops 278192463 # Number of ops (including micro ops) simulated
+sim_ops 278192464 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 717246011 # Number of bytes read from this memory
system.physmem.bytes_read::total 2458815323 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1741569312 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1741569312 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 243173115 # Number of bytes written to this memory
-system.physmem.bytes_written::total 243173115 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 243173117 # Number of bytes written to this memory
+system.physmem.bytes_written::total 243173117 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 217696164 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 90779446 # Number of read requests responded to by this memory
system.physmem.num_reads::total 308475610 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 31439751 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 31439751 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 10308191240 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 4245314267 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 14553505507 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 10308191240 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 10308191240 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1439319674 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1439319674 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 10308191240 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 5684633941 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 15992825181 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_writes::cpu.data 31439752 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 31439752 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 10308191209 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 4245314255 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 14553505464 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 10308191209 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 10308191209 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1439319681 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1439319681 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 10308191209 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 5684633936 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 15992825145 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
-system.cpu.numCycles 337900079 # number of cpu cycles simulated
+system.cpu.numCycles 337900080 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 157988548 # Number of instructions committed
-system.cpu.committedOps 278192463 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 278186171 # Number of integer alu accesses
+system.cpu.committedOps 278192464 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 278186173 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
-system.cpu.num_int_insts 278186171 # number of integer instructions
+system.cpu.num_int_insts 278186173 # number of integer instructions
system.cpu.num_fp_insts 40 # number of float instructions
-system.cpu.num_int_register_reads 739519993 # number of times the integer registers were read
-system.cpu.num_int_register_writes 279212718 # number of times the integer registers were written
+system.cpu.num_int_register_reads 739519998 # number of times the integer registers were read
+system.cpu.num_int_register_writes 279212719 # number of times the integer registers were written
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
-system.cpu.num_mem_refs 122219135 # number of memory refs
+system.cpu.num_mem_refs 122219136 # number of memory refs
system.cpu.num_load_insts 90779384 # Number of load instructions
-system.cpu.num_store_insts 31439751 # Number of store instructions
+system.cpu.num_store_insts 31439752 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 337900079 # Number of busy cycles
+system.cpu.num_busy_cycles 337900080 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
index 519e449..046ac10 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -10,7 +10,7 @@
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -61,21 +61,22 @@
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=2
size=262144
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
@@ -90,7 +91,7 @@
[system.cpu.dtb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.cpu.toL2Bus.slave[3]
@@ -99,21 +100,22 @@
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=2
size=131072
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
@@ -122,7 +124,7 @@
[system.cpu.interrupts]
type=X86LocalApic
-clock=1
+clock=500
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@@ -139,30 +141,31 @@
[system.cpu.itb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=20
size=2097152
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
@@ -172,10 +175,10 @@
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@@ -213,9 +216,9 @@
[system.physmem]
type=SimpleMemory
-clock=1
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
index ac4ad20..f5691fd 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
index 0ff981a..d9a250b 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
@@ -3,8 +3,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 22:29:00
-gem5 started Sep 10 2012 23:03:49
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 00:35:30
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
@@ -25,4 +25,4 @@
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 368209206000 because target called exit()
+Exiting @ tick 365989064000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
index c24d579..2cdeaff 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.365989 # Number of seconds simulated
-sim_ticks 365989063000 # Number of ticks simulated
-final_tick 365989063000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 365989064000 # Number of ticks simulated
+final_tick 365989064000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 621192 # Simulator instruction rate (inst/s)
-host_op_rate 1093819 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1439024491 # Simulator tick rate (ticks/s)
-host_mem_usage 361884 # Number of bytes of host memory used
-host_seconds 254.33 # Real time elapsed on the host
+host_inst_rate 426513 # Simulator instruction rate (inst/s)
+host_op_rate 751021 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 988040650 # Simulator tick rate (ticks/s)
+host_mem_usage 411308 # Number of bytes of host memory used
+host_seconds 370.42 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
-sim_ops 278192463 # Number of ops (including micro ops) simulated
+sim_ops 278192464 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory
system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory
@@ -35,35 +35,35 @@
system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
-system.cpu.numCycles 731978126 # number of cpu cycles simulated
+system.cpu.numCycles 731978128 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 157988548 # Number of instructions committed
-system.cpu.committedOps 278192463 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 278186171 # Number of integer alu accesses
+system.cpu.committedOps 278192464 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 278186173 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
-system.cpu.num_int_insts 278186171 # number of integer instructions
+system.cpu.num_int_insts 278186173 # number of integer instructions
system.cpu.num_fp_insts 40 # number of float instructions
-system.cpu.num_int_register_reads 739519993 # number of times the integer registers were read
-system.cpu.num_int_register_writes 279212718 # number of times the integer registers were written
+system.cpu.num_int_register_reads 739519998 # number of times the integer registers were read
+system.cpu.num_int_register_writes 279212719 # number of times the integer registers were written
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
-system.cpu.num_mem_refs 122219135 # number of memory refs
+system.cpu.num_mem_refs 122219136 # number of memory refs
system.cpu.num_load_insts 90779384 # Number of load instructions
-system.cpu.num_store_insts 31439751 # Number of store instructions
+system.cpu.num_store_insts 31439752 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 731978126 # Number of busy cycles
+system.cpu.num_busy_cycles 731978128 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 24 # number of replacements
-system.cpu.icache.tagsinuse 665.632511 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 665.632509 # Cycle average of tags in use
system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 665.632511 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 665.632509 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.325016 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits
@@ -136,22 +136,22 @@
system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2062733 # number of replacements
-system.cpu.dcache.tagsinuse 4076.488641 # Cycle average of tags in use
-system.cpu.dcache.total_refs 120152368 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 4076.488630 # Cycle average of tags in use
+system.cpu.dcache.total_refs 120152369 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 58.133676 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 126079699000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4076.488641 # Average occupied blocks per requestor
+system.cpu.dcache.avg_refs 58.133677 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 126079700000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4076.488630 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.995236 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 31333642 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 120152368 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 120152368 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 120152368 # number of overall hits
-system.cpu.dcache.overall_hits::total 120152368 # number of overall hits
+system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 120152369 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 120152369 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 120152369 # number of overall hits
+system.cpu.dcache.overall_hits::total 120152369 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses
@@ -170,12 +170,12 @@
system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 122219197 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 122219197 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 122219197 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 122219197 # number of overall (read+write) accesses
+system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 122219198 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 122219198 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 122219198 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 122219198 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses
@@ -236,13 +236,13 @@
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 318 # number of replacements
-system.cpu.l2cache.tagsinuse 20041.899874 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 20041.899820 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3992419 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 30026 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 132.965397 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 19330.353270 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 557.646384 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks 19330.353217 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 557.646383 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 153.900220 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
index 39d5d8c..891e598 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
@@ -30,7 +30,7 @@
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -78,7 +78,6 @@
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
-isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@@ -465,9 +464,6 @@
int_slave=system.membus.master[2]
pio=system.membus.master[1]
-[system.cpu.isa]
-type=X86ISA
-
[system.cpu.itb]
type=X86TLB
children=walker
@@ -528,9 +524,9 @@
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/parser
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
-input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
index ac4ad20..f5691fd 100755
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
index f635f91..1d8d627 100755
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
@@ -1,28 +1,17 @@
+Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:14:29
-gem5 started Oct 30 2012 16:49:35
-gem5 executing on u200540-lin
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 01:06:22
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *********info: Increasing stack size by one page.
-**************************************info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-**
+****************************************
58924 words stored in 3784810 bytes
@@ -34,8 +23,18 @@
Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
* do you know where John 's
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
* how fast the program is it
* I am wondering whether to invite to the party
* I gave him for his birthday it
@@ -75,9 +74,11 @@
the man with whom I play tennis is here
there is a dog in the park
this is not the man we know and love
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
we like to eat at restaurants , usually on weekends
what did John say he thought you should do
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 434496110500 because target called exit()
+Exiting @ tick 434474519000 because target called exit()
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index 05261b4..c659e89 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -1,90 +1,90 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.434496 # Number of seconds simulated
-sim_ticks 434496110500 # Number of ticks simulated
-final_tick 434496110500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.434475 # Number of seconds simulated
+sim_ticks 434474519000 # Number of ticks simulated
+final_tick 434474519000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 78440 # Simulator instruction rate (inst/s)
-host_op_rate 145045 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 41217689 # Simulator tick rate (ticks/s)
-host_mem_usage 343084 # Number of bytes of host memory used
-host_seconds 10541.50 # Real time elapsed on the host
+host_inst_rate 64407 # Simulator instruction rate (inst/s)
+host_op_rate 119096 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 33842135 # Simulator tick rate (ticks/s)
+host_mem_usage 385848 # Number of bytes of host memory used
+host_seconds 12838.27 # Real time elapsed on the host
sim_insts 826877109 # Number of instructions simulated
-sim_ops 1528988699 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 205760 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24473920 # Number of bytes read from this memory
-system.physmem.bytes_read::total 24679680 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 205760 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 205760 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 18793728 # Number of bytes written to this memory
-system.physmem.bytes_written::total 18793728 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3215 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 382405 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 385620 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 293652 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 293652 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 473560 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 56327133 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 56800693 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 473560 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 473560 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 43254076 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 43254076 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 43254076 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 473560 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 56327133 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 100054769 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 385622 # Total number of read requests seen
-system.physmem.writeReqs 293652 # Total number of write requests seen
-system.physmem.cpureqs 889960 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 24679680 # Total number of bytes read from memory
-system.physmem.bytesWritten 18793728 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 24679680 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 18793728 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 136 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 210686 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 24775 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 22937 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 24964 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 25246 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 24873 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 24535 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 23841 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 24700 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 22880 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 23587 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 23221 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 23429 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 24164 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 24144 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 24092 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 24098 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 19149 # Track writes on a per bank basis
+sim_ops 1528988700 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 208768 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24478784 # Number of bytes read from this memory
+system.physmem.bytes_read::total 24687552 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 208768 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 208768 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 18796800 # Number of bytes written to this memory
+system.physmem.bytes_written::total 18796800 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 3262 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 382481 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 385743 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 293700 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 293700 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 480507 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 56341127 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 56821634 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 480507 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 480507 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 43263297 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 43263297 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 43263297 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 480507 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 56341127 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 100084930 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 385745 # Total number of read requests seen
+system.physmem.writeReqs 293700 # Total number of write requests seen
+system.physmem.cpureqs 892876 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 24687552 # Total number of bytes read from memory
+system.physmem.bytesWritten 18796800 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 24687552 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 18796800 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 153 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 213431 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 24700 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 23020 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 24951 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 25312 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 24893 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 24562 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 23866 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 24721 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 22873 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 23594 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 23233 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 23428 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 24104 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 24149 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 24038 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 24148 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 19119 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 17956 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 18934 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 18992 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 19023 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 18726 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 18089 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 18519 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 17452 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 17936 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 17736 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 17628 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 18448 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 18286 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 18332 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 18446 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 18933 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 18994 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 19037 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 18740 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 18105 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 18525 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 17461 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 17937 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 17747 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 17631 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 18446 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 18298 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 18336 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 18435 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 434496092500 # Total gap between requests
+system.physmem.totGap 434474501000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 385622 # Categorize read packet sizes
+system.physmem.readPktSize::6 385745 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -93,7 +93,7 @@
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 293652 # categorize write packet sizes
+system.physmem.writePktSize::6 293700 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
@@ -102,14 +102,14 @@
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 210686 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 213431 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 380872 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4191 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 366 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 51 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 380876 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 4272 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 384 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 53 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -140,29 +140,29 @@
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 12765 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 12770 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 12770 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 12770 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 12770 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 12770 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 12770 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 12770 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 12770 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 12770 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 12770 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 12770 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 12769 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 12769 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 12769 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 12769 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 12769 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 12769 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 12769 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 12769 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 12769 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 12769 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
@@ -171,161 +171,161 @@
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3490991093 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 11561975093 # Sum of mem lat for all requests
-system.physmem.totBusLat 1541944000 # Total cycles spent in databus access
-system.physmem.totBankLat 6529040000 # Total cycles spent in bank access
-system.physmem.avgQLat 9056.08 # Average queueing delay per request
-system.physmem.avgBankLat 16937.17 # Average bank access latency per request
+system.physmem.totQLat 3519471180 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 11592783180 # Sum of mem lat for all requests
+system.physmem.totBusLat 1542368000 # Total cycles spent in databus access
+system.physmem.totBankLat 6530944000 # Total cycles spent in bank access
+system.physmem.avgQLat 9127.45 # Average queueing delay per request
+system.physmem.avgBankLat 16937.45 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 29993.24 # Average memory access latency
-system.physmem.avgRdBW 56.80 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 43.25 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 56.80 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 43.25 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 30064.90 # Average memory access latency
+system.physmem.avgRdBW 56.82 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 43.26 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 56.82 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 43.26 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.63 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.03 # Average read queue length over time
-system.physmem.avgWrQLen 9.57 # Average write queue length over time
-system.physmem.readRowHits 340592 # Number of row buffer hits during reads
-system.physmem.writeRowHits 151278 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 9.43 # Average write queue length over time
+system.physmem.readRowHits 340663 # Number of row buffer hits during reads
+system.physmem.writeRowHits 151214 # Number of row buffer hits during writes
system.physmem.readRowHitRate 88.35 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 51.52 # Row buffer hit rate for writes
-system.physmem.avgGap 639647.76 # Average gap between requests
+system.physmem.writeRowHitRate 51.49 # Row buffer hit rate for writes
+system.physmem.avgGap 639455.00 # Average gap between requests
system.cpu.workload.num_syscalls 551 # Number of system calls
-system.cpu.numCycles 868992222 # number of cpu cycles simulated
+system.cpu.numCycles 868949039 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 214993851 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 214993851 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 13132727 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 150483811 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 147870058 # Number of BTB hits
+system.cpu.BPredUnit.lookups 215014033 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 215014033 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 13139181 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 150598539 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 147901505 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 180595819 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1193570142 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 214993851 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 147870058 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 371300946 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 83432044 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 232898189 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 32611 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 320539 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 60 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 173489759 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 3820168 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 855191197 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.591382 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.388294 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 180614780 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1193262475 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 215014033 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 147901505 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 371277896 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 83426833 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 232782957 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 33410 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 326127 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 173495456 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 3828583 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 855065189 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.591332 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.388123 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 488292980 57.10% 57.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 24712697 2.89% 59.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 27343487 3.20% 63.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 28814936 3.37% 66.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 18484341 2.16% 68.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 24598023 2.88% 71.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 30669616 3.59% 75.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 28863276 3.38% 78.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 183411841 21.45% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 488192448 57.09% 57.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 24710241 2.89% 59.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 27337259 3.20% 63.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 28858306 3.37% 66.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 18484631 2.16% 68.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 24605565 2.88% 71.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 30659669 3.59% 75.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 28862609 3.38% 78.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 183354461 21.44% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 855191197 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.247406 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.373511 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 237057033 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 189447507 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 313514348 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 45129276 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 70043033 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2167224659 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 70043033 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 270477979 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 55455808 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 15344 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 322737561 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 136461472 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2120443257 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 31742 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 21271807 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 100951250 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 96 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 2216845941 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5356850652 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 5356713794 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 136858 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 1614040851 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 602805090 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1368 # count of serializing insts renamed
+system.cpu.fetch.rateDist::total 855065189 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.247441 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.373225 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 236982201 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 189423350 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 313528776 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 45100886 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 70029976 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 2167023894 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 70029976 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 270449019 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 55242457 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 16336 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 322681638 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 136645763 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2120157955 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 31600 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 21404699 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 100960761 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 90 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 2216593007 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5356094891 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 5355960834 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 134057 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 1614040852 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 602552155 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1359 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1337 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 329763590 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 512746819 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 204948217 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 196647356 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 55718334 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2034222855 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 23204 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1808269086 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 840688 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 499770877 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 818821894 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 22651 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 855191197 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.114462 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.887618 # Number of insts issued each cycle
+system.cpu.rename.skidInsts 330141203 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 512720290 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 204905378 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 196472643 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 55515054 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2034068735 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 23193 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1808313369 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 844321 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 499602168 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 818314817 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 22641 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 855065189 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.114825 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.887939 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 234669237 27.44% 27.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 145408124 17.00% 44.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 138604269 16.21% 60.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 132699771 15.52% 76.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 96142027 11.24% 87.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 58835818 6.88% 94.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 34929865 4.08% 98.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 11989965 1.40% 99.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1912121 0.22% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 234637640 27.44% 27.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 145403734 17.00% 44.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 138360213 16.18% 60.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 132907886 15.54% 76.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 96033162 11.23% 87.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 58823756 6.88% 94.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 34984723 4.09% 98.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 12006815 1.40% 99.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1907260 0.22% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 855191197 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 855065189 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 4982607 32.47% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 7772291 50.65% 83.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2591536 16.89% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 4945166 32.31% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 7763763 50.73% 83.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 2595950 16.96% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 2719540 0.15% 0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1190958422 65.86% 66.01% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 2718674 0.15% 0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1190900507 65.86% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.01% # Type of FU issued
@@ -354,291 +354,399 @@
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 438908111 24.27% 90.28% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 175683013 9.72% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 438963543 24.27% 90.28% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 175730645 9.72% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1808269086 # Type of FU issued
-system.cpu.iq.rate 2.080881 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 15346434 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.008487 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4487893952 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2534230949 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1768791787 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 22539 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 44036 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 5119 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1820885356 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 10624 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 170553013 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1808313369 # Type of FU issued
+system.cpu.iq.rate 2.081035 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 15304879 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.008464 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4487818661 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2533909829 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1768767082 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 22466 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 43013 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 5176 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1820889036 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 10538 # Number of floating point alu accesses
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system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 128644663 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 472582 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 269715 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 55788376 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 128618134 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 471778 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 270529 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 55745634 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 12339 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1555 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 12450 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 553 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 70043033 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 17673850 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 2842089 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2034246059 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 2370262 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 512746819 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 204948561 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 6149 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1800682 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 76001 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 269715 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 9110771 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4492681 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 13603452 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1780575608 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 431395989 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 27693478 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 70029976 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 17665795 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 2858627 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2034091928 # Number of instructions dispatched to IQ
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+system.cpu.iew.iewDispStoreInsts 204905820 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 6054 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1808225 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 77432 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 270529 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 9117470 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 4488132 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 13605602 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1780566222 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 431424657 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 27747147 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 602081251 # number of memory reference insts executed
-system.cpu.iew.exec_branches 169281204 # Number of branches executed
-system.cpu.iew.exec_stores 170685262 # Number of stores executed
-system.cpu.iew.exec_rate 2.049012 # Inst execution rate
-system.cpu.iew.wb_sent 1775484026 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1768796906 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1341657182 # num instructions producing a value
-system.cpu.iew.wb_consumers 1964610476 # num instructions consuming a value
+system.cpu.iew.exec_refs 602146985 # number of memory reference insts executed
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+system.cpu.iew.exec_rate 2.049103 # Inst execution rate
+system.cpu.iew.wb_sent 1775473697 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1768772258 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1341647639 # num instructions producing a value
+system.cpu.iew.wb_consumers 1964496611 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.035458 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.682913 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.035530 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.682947 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 505293245 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 13164973 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 785148164 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.947389 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.457160 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 505138383 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 13172358 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 785035213 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.947669 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.458282 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 291743548 37.16% 37.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 195452528 24.89% 62.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 62380641 7.95% 70.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 92170452 11.74% 81.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 25089847 3.20% 84.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 28355719 3.61% 88.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 9376881 1.19% 89.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 10764120 1.37% 91.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 69814428 8.89% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 291749690 37.16% 37.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 195656651 24.92% 62.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 62029976 7.90% 69.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 92178611 11.74% 81.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 25075018 3.19% 84.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 28259306 3.60% 88.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 9351525 1.19% 89.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 10844976 1.38% 91.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 69889460 8.90% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 785148164 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 785035213 # Number of insts commited each cycle
system.cpu.commit.committedInsts 826877109 # Number of instructions committed
-system.cpu.commit.committedOps 1528988699 # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps 1528988700 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 533262341 # Number of memory references committed
+system.cpu.commit.refs 533262342 # Number of memory references committed
system.cpu.commit.loads 384102156 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 149758583 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 1528317557 # Number of committed integer instructions.
+system.cpu.commit.int_insts 1528317559 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 69814428 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 69889460 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 2749615680 # The number of ROB reads
-system.cpu.rob.rob_writes 4138789024 # The number of ROB writes
-system.cpu.timesIdled 344205 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 13801025 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 2749272836 # The number of ROB reads
+system.cpu.rob.rob_writes 4138465929 # The number of ROB writes
+system.cpu.timesIdled 341987 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 13883850 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 826877109 # Number of Instructions Simulated
-system.cpu.committedOps 1528988699 # Number of Ops (including micro ops) Simulated
+system.cpu.committedOps 1528988700 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated
-system.cpu.cpi 1.050933 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.050933 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.951536 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.951536 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3357495880 # number of integer regfile reads
-system.cpu.int_regfile_writes 1848564966 # number of integer regfile writes
-system.cpu.fp_regfile_reads 5116 # number of floating regfile reads
-system.cpu.fp_regfile_writes 3 # number of floating regfile writes
-system.cpu.misc_regfile_reads 980239891 # number of misc regfile reads
-system.cpu.icache.replacements 5389 # number of replacements
-system.cpu.icache.tagsinuse 1038.396160 # Cycle average of tags in use
-system.cpu.icache.total_refs 173252420 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 6992 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 24778.664188 # Average number of references to valid blocks.
+system.cpu.cpi 1.050881 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.050881 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.951583 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.951583 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3357585069 # number of integer regfile reads
+system.cpu.int_regfile_writes 1848487641 # number of integer regfile writes
+system.cpu.fp_regfile_reads 5173 # number of floating regfile reads
+system.cpu.fp_regfile_writes 5 # number of floating regfile writes
+system.cpu.misc_regfile_reads 980297933 # number of misc regfile reads
+system.cpu.icache.replacements 5393 # number of replacements
+system.cpu.icache.tagsinuse 1034.711161 # Cycle average of tags in use
+system.cpu.icache.total_refs 173255659 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 6985 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 24803.959771 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1038.396160 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.507029 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.507029 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 173268230 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 173268230 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 173268230 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 173268230 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 173268230 # number of overall hits
-system.cpu.icache.overall_hits::total 173268230 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 221529 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 221529 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 221529 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 221529 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 221529 # number of overall misses
-system.cpu.icache.overall_misses::total 221529 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 1367876999 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 1367876999 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 1367876999 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 1367876999 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 1367876999 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 1367876999 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 173489759 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 173489759 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 173489759 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 173489759 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 173489759 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 173489759 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001277 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.001277 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.001277 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.001277 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.001277 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.001277 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6174.708499 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 6174.708499 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 6174.708499 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 6174.708499 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 6174.708499 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 6174.708499 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 496 # number of cycles access was blocked
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+system.cpu.icache.occ_percent::total 0.505230 # Average percentage of cache occupancy
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+system.cpu.icache.overall_hits::total 173271213 # number of overall hits
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+system.cpu.icache.overall_misses::total 224243 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 1407047499 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 1407047499 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 1407047499 # number of demand (read+write) miss cycles
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+system.cpu.icache.overall_miss_latency::cpu.inst 1407047499 # number of overall miss cycles
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39872.367584 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.542920 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.542920 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40354.075631 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40354.075631 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43487.723567 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40101.909565 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40130.547344 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43487.723567 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40101.909565 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40130.547344 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 2529431 # number of replacements
-system.cpu.dcache.tagsinuse 4087.842516 # Cycle average of tags in use
-system.cpu.dcache.total_refs 405341407 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 2533527 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 159.990956 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 1787438000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4087.842516 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.998008 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.998008 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 256611582 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 256611582 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 148160067 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 148160067 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 404771649 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 404771649 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 404771649 # number of overall hits
-system.cpu.dcache.overall_hits::total 404771649 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2888518 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2888518 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1000134 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1000134 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 3888652 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3888652 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3888652 # number of overall misses
-system.cpu.dcache.overall_misses::total 3888652 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 49903831500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 49903831500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 24367147000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 24367147000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 74270978500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 74270978500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 74270978500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 74270978500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 259500100 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 259500100 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 408660301 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 408660301 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 408660301 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 408660301 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011131 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.011131 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006705 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.006705 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.009516 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.009516 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.009516 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.009516 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17276.621264 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17276.621264 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24363.882240 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 24363.882240 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 19099.415042 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 19099.415042 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 19099.415042 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 19099.415042 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 7749 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 632 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.261076 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 2331049 # number of writebacks
-system.cpu.dcache.writebacks::total 2331049 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1126114 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 1126114 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16846 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 16846 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1142960 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1142960 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1142960 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1142960 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762404 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1762404 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 983288 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 983288 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2745692 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2745692 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2745692 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2745692 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26902331000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 26902331000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 22198368000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 22198368000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49100699000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 49100699000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49100699000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 49100699000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006792 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006792 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006592 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006592 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006719 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.006719 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006719 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.006719 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15264.565332 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15264.565332 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22575.652301 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22575.652301 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17882.813877 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 17882.813877 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17882.813877 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 17882.813877 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
index dd8a284..5fcf89c 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
@@ -10,7 +10,7 @@
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -68,13 +68,13 @@
[system.cpu.dtb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
-clock=1
+clock=500
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@@ -91,7 +91,7 @@
[system.cpu.itb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.membus.slave[3]
@@ -129,9 +129,9 @@
[system.physmem]
type=SimpleMemory
-clock=1
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr
index ac4ad20..f5691fd 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
index 8d28e1b..cda6458 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
@@ -3,8 +3,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 22:29:00
-gem5 started Sep 10 2012 22:29:08
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 00:35:29
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
@@ -71,4 +71,4 @@
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 885229327000 because target called exit()
+Exiting @ tick 885229327500 because target called exit()
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
index 370f149..2fe2ac2 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
@@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.885229 # Number of seconds simulated
-sim_ticks 885229327000 # Number of ticks simulated
-final_tick 885229327000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 885229327500 # Number of ticks simulated
+final_tick 885229327500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 957113 # Simulator instruction rate (inst/s)
-host_op_rate 1769809 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1024655834 # Simulator tick rate (ticks/s)
-host_mem_usage 269560 # Number of bytes of host memory used
-host_seconds 863.93 # Real time elapsed on the host
+host_inst_rate 941243 # Simulator instruction rate (inst/s)
+host_op_rate 1740465 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1007666185 # Simulator tick rate (ticks/s)
+host_mem_usage 271920 # Number of bytes of host memory used
+host_seconds 878.49 # Real time elapsed on the host
sim_insts 826877110 # Number of instructions simulated
-sim_ops 1528988700 # Number of ops (including micro ops) simulated
+sim_ops 1528988701 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 8546776520 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 2285655656 # Number of bytes read from this memory
system.physmem.bytes_read::total 10832432176 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 8546776520 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 8546776520 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 991849460 # Number of bytes written to this memory
-system.physmem.bytes_written::total 991849460 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 991849462 # Number of bytes written to this memory
+system.physmem.bytes_written::total 991849462 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1068347065 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 384102185 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1452449250 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 149160201 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 149160201 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 9654872765 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2581992695 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 12236865460 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 9654872765 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 9654872765 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1120443516 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1120443516 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 9654872765 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_writes::cpu.data 149160202 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 149160202 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 9654872760 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2581992694 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 12236865453 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 9654872760 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 9654872760 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1120443518 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1120443518 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 9654872760 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3702436212 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 13357308977 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 13357308971 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 551 # Number of system calls
-system.cpu.numCycles 1770458655 # number of cpu cycles simulated
+system.cpu.numCycles 1770458656 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 826877110 # Number of instructions committed
-system.cpu.committedOps 1528988700 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 1528317558 # Number of integer alu accesses
+system.cpu.committedOps 1528988701 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 1528317560 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
-system.cpu.num_int_insts 1528317558 # number of integer instructions
+system.cpu.num_int_insts 1528317560 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 3855106250 # number of times the integer registers were read
-system.cpu.num_int_register_writes 1614040851 # number of times the integer registers were written
+system.cpu.num_int_register_reads 3855106255 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1614040852 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 533262341 # number of memory refs
+system.cpu.num_mem_refs 533262342 # number of memory refs
system.cpu.num_load_insts 384102156 # Number of load instructions
-system.cpu.num_store_insts 149160185 # Number of store instructions
+system.cpu.num_store_insts 149160186 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 1770458655 # Number of busy cycles
+system.cpu.num_busy_cycles 1770458656 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
index 1740f8a..bfee22e 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -10,7 +10,7 @@
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -61,21 +61,22 @@
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=2
size=262144
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
@@ -90,7 +91,7 @@
[system.cpu.dtb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.cpu.toL2Bus.slave[3]
@@ -99,21 +100,22 @@
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=2
size=131072
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
@@ -122,7 +124,7 @@
[system.cpu.interrupts]
type=X86LocalApic
-clock=1
+clock=500
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@@ -139,30 +141,31 @@
[system.cpu.itb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=20
size=2097152
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
@@ -172,10 +175,10 @@
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@@ -213,9 +216,9 @@
[system.physmem]
type=SimpleMemory
-clock=1
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr
index ac4ad20..f5691fd 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
index 66dfa99..26674a0 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
@@ -3,8 +3,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 22:29:00
-gem5 started Sep 10 2012 22:29:27
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 00:51:49
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
@@ -71,4 +71,4 @@
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 1652606827000 because target called exit()
+Exiting @ tick 1647872848000 because target called exit()
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
index fbbc379..c29684f 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.647873 # Number of seconds simulated
-sim_ticks 1647872847000 # Number of ticks simulated
-final_tick 1647872847000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 1647872848000 # Number of ticks simulated
+final_tick 1647872848000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 897428 # Simulator instruction rate (inst/s)
-host_op_rate 1659445 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1788472844 # Simulator tick rate (ticks/s)
-host_mem_usage 230968 # Number of bytes of host memory used
-host_seconds 921.39 # Real time elapsed on the host
+host_inst_rate 488671 # Simulator instruction rate (inst/s)
+host_op_rate 903607 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 973865405 # Simulator tick rate (ticks/s)
+host_mem_usage 280376 # Number of bytes of host memory used
+host_seconds 1692.10 # Real time elapsed on the host
sim_insts 826877110 # Number of instructions simulated
-sim_ops 1528988700 # Number of ops (including micro ops) simulated
+sim_ops 1528988701 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24272448 # Number of bytes read from this memory
system.physmem.bytes_read::total 24393152 # Number of bytes read from this memory
@@ -33,37 +33,37 @@
system.physmem.bw_total::writebacks 11351788 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 26154601 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 551 # Number of system calls
-system.cpu.numCycles 3295745694 # number of cpu cycles simulated
+system.cpu.numCycles 3295745696 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 826877110 # Number of instructions committed
-system.cpu.committedOps 1528988700 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 1528317558 # Number of integer alu accesses
+system.cpu.committedOps 1528988701 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 1528317560 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
-system.cpu.num_int_insts 1528317558 # number of integer instructions
+system.cpu.num_int_insts 1528317560 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 3855106250 # number of times the integer registers were read
-system.cpu.num_int_register_writes 1614040851 # number of times the integer registers were written
+system.cpu.num_int_register_reads 3855106255 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1614040852 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 533262341 # number of memory refs
+system.cpu.num_mem_refs 533262342 # number of memory refs
system.cpu.num_load_insts 384102156 # Number of load instructions
-system.cpu.num_store_insts 149160185 # Number of store instructions
+system.cpu.num_store_insts 149160186 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 3295745694 # Number of busy cycles
+system.cpu.num_busy_cycles 3295745696 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 1253 # number of replacements
-system.cpu.icache.tagsinuse 881.356492 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 881.356491 # Cycle average of tags in use
system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 881.356492 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.430350 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits
@@ -136,22 +136,22 @@
system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2514362 # number of replacements
-system.cpu.dcache.tagsinuse 4086.415788 # Cycle average of tags in use
-system.cpu.dcache.total_refs 530743928 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 4086.415786 # Cycle average of tags in use
+system.cpu.dcache.total_refs 530743929 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 8211722000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4086.415788 # Average occupied blocks per requestor
+system.cpu.dcache.warmup_cycle 8211723000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4086.415786 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.997660 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 148369157 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 530743928 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 530743928 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 530743928 # number of overall hits
-system.cpu.dcache.overall_hits::total 530743928 # number of overall hits
+system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 530743929 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 530743929 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 530743929 # number of overall hits
+system.cpu.dcache.overall_hits::total 530743929 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses
@@ -170,12 +170,12 @@
system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 533262386 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 533262386 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 533262386 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 533262386 # number of overall (read+write) accesses
+system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 533262387 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 533262387 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 533262387 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 533262387 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses
@@ -236,14 +236,14 @@
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 348459 # number of replacements
-system.cpu.l2cache.tagsinuse 29286.402699 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 29286.402681 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3655011 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 380814 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 9.597890 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 755936429000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 21041.299363 # Average occupied blocks per requestor
+system.cpu.l2cache.warmup_cycle 755936430000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 21041.299350 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 139.758520 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 8105.344817 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 8105.344812 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
index 66b4a9e..3e10b88 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
@@ -10,7 +10,7 @@
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -68,13 +68,13 @@
[system.cpu.dtb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
-clock=1
+clock=500
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@@ -91,7 +91,7 @@
[system.cpu.itb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.membus.slave[3]
@@ -129,9 +129,9 @@
[system.physmem]
type=SimpleMemory
-clock=1
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
index ac4ad20..f5691fd 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
index 7e9cf37..f8f83dc 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
@@ -3,8 +3,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 22:29:00
-gem5 started Sep 10 2012 22:29:07
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 00:35:30
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
@@ -26,4 +26,4 @@
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 2846007226500 because target called exit()
+Exiting @ tick 2846007227000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
index 2924171..15cf588 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
@@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.846007 # Number of seconds simulated
-sim_ticks 2846007226500 # Number of ticks simulated
-final_tick 2846007226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 2846007227000 # Number of ticks simulated
+final_tick 2846007227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1027178 # Simulator instruction rate (inst/s)
-host_op_rate 1600436 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 971834142 # Simulator tick rate (ticks/s)
-host_mem_usage 265228 # Number of bytes of host memory used
-host_seconds 2928.49 # Real time elapsed on the host
+host_inst_rate 1003542 # Simulator instruction rate (inst/s)
+host_op_rate 1563610 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 949472024 # Simulator tick rate (ticks/s)
+host_mem_usage 267592 # Number of bytes of host memory used
+host_seconds 2997.46 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
-sim_ops 4686862594 # Number of ops (including micro ops) simulated
+sim_ops 4686862595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5023868343 # Number of bytes read from this memory
system.physmem.bytes_read::total 37129731399 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 32105863056 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 32105863056 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 1544656790 # Number of bytes written to this memory
-system.physmem.bytes_written::total 1544656790 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 1544656792 # Number of bytes written to this memory
+system.physmem.bytes_written::total 1544656792 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 4013232882 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1239184745 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5252417627 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 438528337 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 438528337 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 11281019513 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::cpu.data 438528338 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 438528338 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 11281019511 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1765233867 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 13046253380 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 11281019513 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 11281019513 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 542745210 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 542745210 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 11281019513 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2307979077 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 13588998590 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total 13046253378 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 11281019511 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 11281019511 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 542745211 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 542745211 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 11281019511 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 13588998589 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 5692014454 # number of cpu cycles simulated
+system.cpu.numCycles 5692014455 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 3008081022 # Number of instructions committed
-system.cpu.committedOps 4686862594 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 4686862523 # Number of integer alu accesses
+system.cpu.committedOps 4686862595 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 4686862525 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
-system.cpu.num_int_insts 4686862523 # number of integer instructions
+system.cpu.num_int_insts 4686862525 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 11915474418 # number of times the integer registers were read
-system.cpu.num_int_register_writes 5355771935 # number of times the integer registers were written
+system.cpu.num_int_register_reads 11915474423 # number of times the integer registers were read
+system.cpu.num_int_register_writes 5355771936 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 1677713082 # number of memory refs
+system.cpu.num_mem_refs 1677713083 # number of memory refs
system.cpu.num_load_insts 1239184745 # Number of load instructions
-system.cpu.num_store_insts 438528337 # Number of store instructions
+system.cpu.num_store_insts 438528338 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 5692014454 # Number of busy cycles
+system.cpu.num_busy_cycles 5692014455 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
index bb8d06f..514c208 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -10,7 +10,7 @@
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -61,21 +61,22 @@
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=2
size=262144
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
@@ -90,7 +91,7 @@
[system.cpu.dtb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.cpu.toL2Bus.slave[3]
@@ -99,21 +100,22 @@
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=2
size=131072
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
@@ -122,7 +124,7 @@
[system.cpu.interrupts]
type=X86LocalApic
-clock=1
+clock=500
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@@ -139,30 +141,31 @@
[system.cpu.itb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=20
size=2097152
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
@@ -172,10 +175,10 @@
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@@ -185,7 +188,7 @@
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing
+cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
egid=100
env=
errout=cerr
@@ -213,9 +216,9 @@
[system.physmem]
type=SimpleMemory
-clock=1
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
index ac4ad20..f5691fd 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
index 9df33af..e7934dc 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
@@ -3,8 +3,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 22:29:00
-gem5 started Sep 10 2012 22:29:08
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 00:38:11
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
@@ -26,4 +26,4 @@
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 5901048883000 because target called exit()
+Exiting @ tick 5882580525000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index 21fe18a..8918bba 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 5.882581 # Number of seconds simulated
-sim_ticks 5882580524000 # Number of ticks simulated
-final_tick 5882580524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 5882580525000 # Number of ticks simulated
+final_tick 5882580525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 472403 # Simulator instruction rate (inst/s)
-host_op_rate 736047 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 923827707 # Simulator tick rate (ticks/s)
-host_mem_usage 227772 # Number of bytes of host memory used
-host_seconds 6367.62 # Real time elapsed on the host
+host_inst_rate 506721 # Simulator instruction rate (inst/s)
+host_op_rate 789517 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 990939541 # Simulator tick rate (ticks/s)
+host_mem_usage 276172 # Number of bytes of host memory used
+host_seconds 5936.37 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
-sim_ops 4686862594 # Number of ops (including micro ops) simulated
+sim_ops 4686862595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 125326976 # Number of bytes read from this memory
system.physmem.bytes_read::total 125370176 # Number of bytes read from this memory
@@ -35,26 +35,26 @@
system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 11765161048 # number of cpu cycles simulated
+system.cpu.numCycles 11765161050 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 3008081022 # Number of instructions committed
-system.cpu.committedOps 4686862594 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 4686862523 # Number of integer alu accesses
+system.cpu.committedOps 4686862595 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 4686862525 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
-system.cpu.num_int_insts 4686862523 # number of integer instructions
+system.cpu.num_int_insts 4686862525 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 11915474418 # number of times the integer registers were read
-system.cpu.num_int_register_writes 5355771935 # number of times the integer registers were written
+system.cpu.num_int_register_reads 11915474423 # number of times the integer registers were read
+system.cpu.num_int_register_writes 5355771936 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 1677713082 # number of memory refs
+system.cpu.num_mem_refs 1677713083 # number of memory refs
system.cpu.num_load_insts 1239184745 # Number of load instructions
-system.cpu.num_store_insts 438528337 # Number of store instructions
+system.cpu.num_store_insts 438528338 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 11765161048 # Number of busy cycles
+system.cpu.num_busy_cycles 11765161050 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 10 # number of replacements
@@ -137,21 +137,21 @@
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9108581 # number of replacements
system.cpu.dcache.tagsinuse 4084.587031 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1668600405 # Total number of references to valid blocks.
+system.cpu.dcache.total_refs 1668600406 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 58853920000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle 58853921000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4084.587031 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.997214 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 436638510 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 436638510 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1668600405 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1668600405 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1668600405 # number of overall hits
-system.cpu.dcache.overall_hits::total 1668600405 # number of overall hits
+system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 1668600406 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1668600406 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1668600406 # number of overall hits
+system.cpu.dcache.overall_hits::total 1668600406 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses
@@ -170,12 +170,12 @@
system.cpu.dcache.overall_miss_latency::total 200710756000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1239184745 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1239184745 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 438528337 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 438528337 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 1677713082 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 1677713082 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 1677713082 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 1677713082 # number of overall (read+write) accesses
+system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 1677713083 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 1677713083 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 1677713083 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 1677713083 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses
@@ -236,14 +236,14 @@
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1926197 # number of replacements
-system.cpu.l2cache.tagsinuse 31136.249390 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 31136.249384 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8965026 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 1955980 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 4.583393 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 340768633000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 15396.795539 # Average occupied blocks per requestor
+system.cpu.l2cache.warmup_cycle 340768634000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 15396.795536 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 15713.812836 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 15713.812833 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
index 153c74c..7edece4 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
@@ -30,7 +30,7 @@
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -78,7 +78,6 @@
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
-isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@@ -465,9 +464,6 @@
int_slave=system.membus.master[2]
pio=system.membus.master[1]
-[system.cpu.isa]
-type=X86ISA
-
[system.cpu.itb]
type=X86TLB
children=walker
@@ -528,7 +524,7 @@
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr
index ac4ad20..f5691fd 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
index b5276d9..248fa6c 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
@@ -1,10 +1,14 @@
+Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:14:29
-gem5 started Oct 30 2012 17:50:59
-gem5 executing on u200540-lin
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 00:48:42
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
+Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
+Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -22,4 +26,4 @@
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 82887492500 because target called exit()
+122 123 124 Exiting @ tick 82648140000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
index 664d70a..5da80c5 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -1,57 +1,57 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.082887 # Number of seconds simulated
-sim_ticks 82887492500 # Number of ticks simulated
-final_tick 82887492500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.082648 # Number of seconds simulated
+sim_ticks 82648140000 # Number of ticks simulated
+final_tick 82648140000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 73575 # Simulator instruction rate (inst/s)
-host_op_rate 123318 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 46175257 # Simulator tick rate (ticks/s)
-host_mem_usage 235032 # Number of bytes of host memory used
-host_seconds 1795.06 # Real time elapsed on the host
+host_inst_rate 58118 # Simulator instruction rate (inst/s)
+host_op_rate 97410 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 36369167 # Simulator tick rate (ticks/s)
+host_mem_usage 286740 # Number of bytes of host memory used
+host_seconds 2272.48 # Real time elapsed on the host
sim_insts 132071192 # Number of instructions simulated
-sim_ops 221362960 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 218112 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 124480 # Number of bytes read from this memory
-system.physmem.bytes_read::total 342592 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 218112 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 218112 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3408 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1945 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 5353 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2631422 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1501795 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4133217 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2631422 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2631422 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2631422 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1501795 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4133217 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 5355 # Total number of read requests seen
+sim_ops 221362961 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 217728 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 124416 # Number of bytes read from this memory
+system.physmem.bytes_read::total 342144 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 217728 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 217728 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 3402 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1944 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 5346 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 2634397 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1505370 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4139766 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 2634397 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 2634397 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 2634397 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1505370 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4139766 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 5348 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 5520 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 342592 # Total number of bytes read from memory
+system.physmem.cpureqs 5502 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 342144 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 342592 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 342144 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 165 # Reqs where no action is needed
+system.physmem.neitherReadNorWrite 154 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 306 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 321 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 318 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 313 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 318 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 310 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 308 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 368 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 332 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 328 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 306 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 257 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 260 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 277 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 361 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 434 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 437 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 435 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 352 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 370 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 293 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 369 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 295 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
@@ -70,14 +70,14 @@
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 82887463000 # Total gap between requests
+system.physmem.totGap 82648108000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 5355 # Categorize read packet sizes
+system.physmem.readPktSize::6 5348 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -95,13 +95,13 @@
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 165 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 154 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 4195 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 4185 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 926 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 196 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 200 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
@@ -164,570 +164,420 @@
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 16692334 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 122490334 # Sum of mem lat for all requests
-system.physmem.totBusLat 21420000 # Total cycles spent in databus access
-system.physmem.totBankLat 84378000 # Total cycles spent in bank access
-system.physmem.avgQLat 3117.15 # Average queueing delay per request
-system.physmem.avgBankLat 15756.86 # Average bank access latency per request
+system.physmem.totQLat 16873322 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 122447322 # Sum of mem lat for all requests
+system.physmem.totBusLat 21392000 # Total cycles spent in databus access
+system.physmem.totBankLat 84182000 # Total cycles spent in bank access
+system.physmem.avgQLat 3155.07 # Average queueing delay per request
+system.physmem.avgBankLat 15740.84 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 22874.01 # Average memory access latency
-system.physmem.avgRdBW 4.13 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 22895.91 # Average memory access latency
+system.physmem.avgRdBW 4.14 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 4.13 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 4.14 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 4747 # Number of row buffer hits during reads
+system.physmem.readRowHits 4742 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 88.65 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 88.67 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 15478517.83 # Average gap between requests
+system.physmem.avgGap 15454021.69 # Average gap between requests
system.cpu.workload.num_syscalls 400 # Number of system calls
-system.cpu.numCycles 165774986 # number of cpu cycles simulated
+system.cpu.numCycles 165296281 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 19962549 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 19962549 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 2008101 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 13827383 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 13115978 # Number of BTB hits
+system.cpu.BPredUnit.lookups 19953215 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 19953215 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 2011335 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 13840594 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 13098591 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 25874933 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 219082558 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 19962549 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 13115978 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 57603231 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 17636080 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 66812180 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 382 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1920 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 86 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 24490621 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 428850 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 165653450 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.184047 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.324284 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 25830999 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 218891152 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 19953215 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 13098591 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 57573712 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 17632764 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 66415443 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 241 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1579 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 24446052 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 431778 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 165175969 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.190116 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.327383 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 109646244 66.19% 66.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3069160 1.85% 68.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2390407 1.44% 69.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2911043 1.76% 71.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 3444057 2.08% 73.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 3578858 2.16% 75.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 4315336 2.61% 78.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 2737464 1.65% 79.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 33560881 20.26% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 109199449 66.11% 66.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 3061509 1.85% 67.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2383315 1.44% 69.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2892599 1.75% 71.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 3450171 2.09% 73.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 3573015 2.16% 75.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 4309284 2.61% 78.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 2725915 1.65% 79.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 33580712 20.33% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 165653450 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.120420 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.321566 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 38806807 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 56798437 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 44693921 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 9993567 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 15360718 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 353645742 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 15360718 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 46261084 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 15045259 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 23094 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 46566997 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 42396298 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 345315167 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 90 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 18136112 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 22140506 # Number of times rename has blocked due to LSQ full
+system.cpu.fetch.rateDist::total 165175969 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.120712 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.324235 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 38701150 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 56465114 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 44698220 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 9957565 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 15353920 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 353610105 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 15353920 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 46165738 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 14909579 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 23078 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 46524421 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 42199233 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 345243747 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 88 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 17893684 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 22177130 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 107 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 398865932 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 960470736 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 950586912 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 9883824 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 259428603 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 139437329 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1690 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1680 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 90473578 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 86725107 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 31801013 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 58042243 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 18917665 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 333696674 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 3504 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 267486026 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 249957 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 111886449 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 230098096 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 2258 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 165653450 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.614733 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.503292 # Number of insts issued each cycle
+system.cpu.rename.RenamedOperands 398936501 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 960723880 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 950976963 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 9746917 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 259428604 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 139507897 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1674 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1664 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 90390787 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 86672801 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 31756377 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 57758664 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 18775058 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 333623093 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 3362 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 267451276 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 258403 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 111810012 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 230098900 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 2117 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 165175969 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.619190 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.505359 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 45188105 27.28% 27.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 46827780 28.27% 55.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 32851570 19.83% 75.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 19799355 11.95% 87.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 13199962 7.97% 95.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 4781234 2.89% 98.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2328741 1.41% 99.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 535047 0.32% 99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 141656 0.09% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 44964626 27.22% 27.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 46539597 28.18% 55.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 32801785 19.86% 75.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 19824720 12.00% 87.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 13230335 8.01% 95.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 4791341 2.90% 98.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 2351721 1.42% 99.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 529174 0.32% 99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 142670 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 165653450 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 165175969 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 130850 4.93% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 2255745 85.02% 89.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 266492 10.04% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 137826 5.20% 5.20% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.20% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.20% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.20% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.20% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.20% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 2250902 84.86% 90.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 263908 9.95% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 1212176 0.45% 0.45% # Type of FU issued
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-system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.59% # Type of FU issued
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-system.cpu.iq.FU_type_0::FloatAdd 1600871 0.60% 66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.18% # Type of FU issued
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-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.18% # Type of FU issued
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-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.18% # Type of FU issued
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-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 67180560 25.12% 91.30% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 23272219 8.70% 100.00% # Type of FU issued
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+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.16% # Type of FU issued
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+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.16% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.16% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.16% # Type of FU issued
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+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.16% # Type of FU issued
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+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.16% # Type of FU issued
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+system.cpu.iq.FU_type_0::MemWrite 23264809 8.70% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 267486026 # Type of FU issued
-system.cpu.iq.rate 1.613549 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2653087 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.009919 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 698167044 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 441210039 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 260260402 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 5361502 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 4667533 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 2580716 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 266230560 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 2696377 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 18979902 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 267451276 # Type of FU issued
+system.cpu.iq.rate 1.618011 # Inst issue rate
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+system.cpu.iq.fu_busy_rate 0.009918 # FU busy rate (busy events/executed inst)
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+system.cpu.iq.int_inst_queue_writes 441157156 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 260237459 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 5341058 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 4570848 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 2570585 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 266205797 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 2685981 # Number of floating point alu accesses
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system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 30075521 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 29325 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 296266 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 11285297 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 30023215 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 29490 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 296813 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 11240660 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 49068 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads 49425 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 15360718 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 583386 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 263755 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 333700178 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 187889 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 86725107 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 31801013 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1675 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 149208 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 31553 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 296266 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1173784 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 915890 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 2089674 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 264607897 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 66196383 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2878129 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 15353920 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 582358 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 260686 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 333626455 # Number of instructions dispatched to IQ
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+system.cpu.iew.iewIQFullEvents 146774 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 31153 # Number of times the LSQ has become full, causing a stall
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+system.cpu.iew.predictedTakenIncorrect 1177159 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 916050 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 2093209 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 264577691 # Number of executed instructions
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+system.cpu.iew.iewExecSquashedInsts 2873585 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 89076319 # number of memory reference insts executed
-system.cpu.iew.exec_branches 14601653 # Number of branches executed
-system.cpu.iew.exec_stores 22879936 # Number of stores executed
-system.cpu.iew.exec_rate 1.596187 # Inst execution rate
-system.cpu.iew.wb_sent 263672307 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 262841118 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 212055070 # num instructions producing a value
-system.cpu.iew.wb_consumers 375144375 # num instructions consuming a value
+system.cpu.iew.exec_refs 89117815 # number of memory reference insts executed
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+system.cpu.iew.exec_stores 22871926 # Number of stores executed
+system.cpu.iew.exec_rate 1.600627 # Inst execution rate
+system.cpu.iew.wb_sent 263630467 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 262808044 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 212084858 # num instructions producing a value
+system.cpu.iew.wb_consumers 375096623 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.585529 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.565263 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.589921 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.565414 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 112374263 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 2008288 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 150292732 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.472879 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.939566 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 112301239 # The number of squashed insts skipped by commit
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+system.cpu.commit.branchMispredicts 2011502 # The number of times a branch was mispredicted
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+system.cpu.commit.committed_per_cycle::mean 1.477506 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.946000 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 50934932 33.89% 33.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 57339097 38.15% 72.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 13849183 9.21% 81.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 12078421 8.04% 89.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 4153000 2.76% 92.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 2960899 1.97% 94.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1067284 0.71% 94.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1009293 0.67% 95.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 6900623 4.59% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 50722618 33.86% 33.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 57116806 38.12% 71.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 13820755 9.22% 81.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 12019830 8.02% 89.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 4145175 2.77% 91.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 2956577 1.97% 93.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1072909 0.72% 94.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 994916 0.66% 95.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 6972463 4.65% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 150292732 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 149822049 # Number of insts commited each cycle
system.cpu.commit.committedInsts 132071192 # Number of instructions committed
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@@ -754,30 +604,30 @@
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-system.cpu.dcache.demand_avg_mshr_miss_latency::total 44603.672710 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44603.672710 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 44603.672710 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53895.683453 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53895.683453 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42615.988372 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42615.988372 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44817.033224 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 44817.033224 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44817.033224 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 44817.033224 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.tagsinuse 2509.913634 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 3332 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 3792 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.878692 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 0.902701 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 2234.774408 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 274.236525 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.000028 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.068200 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.008369 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.076596 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 3299 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 30 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 3329 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 14 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 14 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 3299 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 37 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 3336 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 3299 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 37 # number of overall hits
+system.cpu.l2cache.overall_hits::total 3336 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 3402 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 386 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 3788 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 154 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 154 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 1560 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 1560 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 3402 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 1946 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 5348 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 3402 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 1946 # number of overall misses
+system.cpu.l2cache.overall_misses::total 5348 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 158303000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21677500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 179980500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68234000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 68234000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 158303000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 89911500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 248214500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 158303000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 89911500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 248214500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 6701 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 416 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 7117 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 14 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 14 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 154 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 154 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 1567 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 1567 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 6701 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1983 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 8684 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 6701 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1983 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 8684 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.507685 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.927885 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.532247 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995533 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.995533 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.507685 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.981341 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.615845 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.507685 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.981341 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.615845 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46532.333921 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56159.326425 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 47513.331573 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43739.743590 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43739.743590 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46532.333921 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46203.237410 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 46412.584144 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46532.333921 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46203.237410 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 46412.584144 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3402 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 386 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 3788 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 154 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 154 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1560 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 1560 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3402 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1946 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 5348 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3402 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1946 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 5348 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115394483 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16844598 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 132239081 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1540154 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1540154 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48432493 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48432493 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115394483 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65277091 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 180671574 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115394483 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65277091 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 180671574 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.507685 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.927885 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.532247 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995533 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995533 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.507685 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.981341 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.615845 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.507685 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981341 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.615845 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33919.601117 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43638.854922 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34910.000264 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31046.469872 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31046.469872 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33919.601117 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33544.239979 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33783.016829 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33919.601117 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33544.239979 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33783.016829 # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
index 0981b56..b845559 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
@@ -10,7 +10,7 @@
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -68,13 +68,13 @@
[system.cpu.dtb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
-clock=1
+clock=500
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@@ -91,7 +91,7 @@
[system.cpu.itb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.membus.slave[3]
@@ -129,9 +129,9 @@
[system.physmem]
type=SimpleMemory
-clock=1
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr
index ac4ad20..f5691fd 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
index bf4b869..82f0dcf 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
@@ -3,8 +3,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 22:29:00
-gem5 started Sep 10 2012 22:29:08
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 00:50:19
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav
@@ -26,4 +26,4 @@
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 131393067000 because target called exit()
+122 123 124 Exiting @ tick 131393067500 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
index 5240c75..c5a1b58 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
@@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.131393 # Number of seconds simulated
-sim_ticks 131393067000 # Number of ticks simulated
-final_tick 131393067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 131393067500 # Number of ticks simulated
+final_tick 131393067500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 917611 # Simulator instruction rate (inst/s)
-host_op_rate 1537997 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 912899116 # Simulator tick rate (ticks/s)
-host_mem_usage 272856 # Number of bytes of host memory used
-host_seconds 143.93 # Real time elapsed on the host
+host_inst_rate 889897 # Simulator instruction rate (inst/s)
+host_op_rate 1491546 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 885328041 # Simulator tick rate (ticks/s)
+host_mem_usage 275216 # Number of bytes of host memory used
+host_seconds 148.41 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
-sim_ops 221362961 # Number of ops (including micro ops) simulated
+sim_ops 221362962 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 310423750 # Number of bytes read from this memory
system.physmem.bytes_read::total 1698378686 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1387954936 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1387954936 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 99822189 # Number of bytes written to this memory
-system.physmem.bytes_written::total 99822189 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 99822191 # Number of bytes written to this memory
+system.physmem.bytes_written::total 99822191 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 173494367 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 56682004 # Number of read requests responded to by this memory
system.physmem.num_reads::total 230176371 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 20515730 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 20515730 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 10563380304 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2362558064 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 12925938368 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 10563380304 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 10563380304 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 759721889 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 759721889 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 10563380304 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3122279953 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 13685660256 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_writes::cpu.data 20515731 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 20515731 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 10563380264 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2362558055 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 12925938319 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 10563380264 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 10563380264 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 759721901 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 759721901 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 10563380264 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3122279956 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 13685660219 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 400 # Number of system calls
-system.cpu.numCycles 262786135 # number of cpu cycles simulated
+system.cpu.numCycles 262786136 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 132071193 # Number of instructions committed
-system.cpu.committedOps 221362961 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 220339550 # Number of integer alu accesses
+system.cpu.committedOps 221362962 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 220339552 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
-system.cpu.num_int_insts 220339550 # number of integer instructions
+system.cpu.num_int_insts 220339552 # number of integer instructions
system.cpu.num_fp_insts 2162459 # number of float instructions
-system.cpu.num_int_register_reads 616958548 # number of times the integer registers were read
-system.cpu.num_int_register_writes 257597200 # number of times the integer registers were written
+system.cpu.num_int_register_reads 616958553 # number of times the integer registers were read
+system.cpu.num_int_register_writes 257597201 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
-system.cpu.num_mem_refs 77165302 # number of memory refs
+system.cpu.num_mem_refs 77165303 # number of memory refs
system.cpu.num_load_insts 56649586 # Number of load instructions
-system.cpu.num_store_insts 20515716 # Number of store instructions
+system.cpu.num_store_insts 20515717 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 262786135 # Number of busy cycles
+system.cpu.num_busy_cycles 262786136 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
index 15a5712..c487d8f 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -10,7 +10,7 @@
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -61,21 +61,22 @@
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=2
size=262144
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
@@ -90,7 +91,7 @@
[system.cpu.dtb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.cpu.toL2Bus.slave[3]
@@ -99,21 +100,22 @@
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=2
size=131072
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
@@ -122,7 +124,7 @@
[system.cpu.interrupts]
type=X86LocalApic
-clock=1
+clock=500
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@@ -139,30 +141,31 @@
[system.cpu.itb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=20
size=2097152
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
@@ -172,10 +175,10 @@
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@@ -213,9 +216,9 @@
[system.physmem]
type=SimpleMemory
-clock=1
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr
index ac4ad20..f5691fd 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
index 623b8af..ea7ae2f 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
@@ -3,8 +3,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 22:29:00
-gem5 started Sep 10 2012 22:57:57
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 01:16:52
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav
@@ -26,4 +26,4 @@
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 250980994000 because target called exit()
+122 123 124 Exiting @ tick 250953956000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
index 82f5663..37f9d19 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.250954 # Number of seconds simulated
-sim_ticks 250953955000 # Number of ticks simulated
-final_tick 250953955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 250953956000 # Number of ticks simulated
+final_tick 250953956000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 366685 # Simulator instruction rate (inst/s)
-host_op_rate 614596 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 696753053 # Simulator tick rate (ticks/s)
-host_mem_usage 236244 # Number of bytes of host memory used
-host_seconds 360.18 # Real time elapsed on the host
+host_inst_rate 472281 # Simulator instruction rate (inst/s)
+host_op_rate 791585 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 897401473 # Simulator tick rate (ticks/s)
+host_mem_usage 283668 # Number of bytes of host memory used
+host_seconds 279.65 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
-sim_ops 221362961 # Number of ops (including micro ops) simulated
+sim_ops 221362962 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory
system.physmem.bytes_read::total 303040 # Number of bytes read from this memory
@@ -28,35 +28,35 @@
system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 400 # Number of system calls
-system.cpu.numCycles 501907910 # number of cpu cycles simulated
+system.cpu.numCycles 501907912 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 132071193 # Number of instructions committed
-system.cpu.committedOps 221362961 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 220339550 # Number of integer alu accesses
+system.cpu.committedOps 221362962 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 220339552 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
-system.cpu.num_int_insts 220339550 # number of integer instructions
+system.cpu.num_int_insts 220339552 # number of integer instructions
system.cpu.num_fp_insts 2162459 # number of float instructions
-system.cpu.num_int_register_reads 616958548 # number of times the integer registers were read
-system.cpu.num_int_register_writes 257597200 # number of times the integer registers were written
+system.cpu.num_int_register_reads 616958553 # number of times the integer registers were read
+system.cpu.num_int_register_writes 257597201 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
-system.cpu.num_mem_refs 77165302 # number of memory refs
+system.cpu.num_mem_refs 77165303 # number of memory refs
system.cpu.num_load_insts 56649586 # Number of load instructions
-system.cpu.num_store_insts 20515716 # Number of store instructions
+system.cpu.num_store_insts 20515717 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 501907910 # Number of busy cycles
+system.cpu.num_busy_cycles 501907912 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 2836 # number of replacements
-system.cpu.icache.tagsinuse 1455.296654 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1455.296648 # Cycle average of tags in use
system.cpu.icache.total_refs 173489674 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 36959.879421 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1455.296654 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 1455.296648 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.710594 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 173489674 # number of ReadReq hits
@@ -129,22 +129,22 @@
system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 41 # number of replacements
-system.cpu.dcache.tagsinuse 1363.457581 # Cycle average of tags in use
-system.cpu.dcache.total_refs 77195829 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 1363.457576 # Cycle average of tags in use
+system.cpu.dcache.total_refs 77195830 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 40522.744882 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 40522.745407 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 1363.457581 # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data 1363.457576 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.332875 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 56681677 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 56681677 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 20514152 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 20514152 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 77195829 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 77195829 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 77195829 # number of overall hits
-system.cpu.dcache.overall_hits::total 77195829 # number of overall hits
+system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 77195830 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 77195830 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 77195830 # number of overall hits
+system.cpu.dcache.overall_hits::total 77195830 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses
@@ -163,12 +163,12 @@
system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 56682004 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 56682004 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 77197734 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 77197734 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 77197734 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 77197734 # number of overall (read+write) accesses
+system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 77197735 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 77197735 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 77197735 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 77197735 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses
@@ -229,14 +229,14 @@
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 2058.178702 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 2058.178694 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1862 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.588496 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 1829.978594 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 228.178364 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 1829.978587 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 228.178363 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
index 85178b3..26b2b03 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
@@ -30,7 +30,7 @@
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -78,7 +78,6 @@
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
-isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@@ -465,9 +464,6 @@
int_slave=system.membus.master[2]
pio=system.membus.master[1]
-[system.cpu.isa]
-type=X86ISA
-
[system.cpu.itb]
type=X86TLB
children=walker
@@ -528,7 +524,7 @@
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/x86/linux/hello
+executable=tests/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr
index ac4ad20..f5691fd 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
index c8ef021..894b4b4 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:14:29
-gem5 started Oct 30 2012 16:15:47
-gem5 executing on u200540-lin
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 01:12:54
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index e6a1ad3..f54c839 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -4,13 +4,13 @@
sim_ticks 15014000 # Number of ticks simulated
final_tick 15014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 32657 # Simulator instruction rate (inst/s)
-host_op_rate 59148 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 91121721 # Simulator tick rate (ticks/s)
-host_mem_usage 223384 # Number of bytes of host memory used
-host_seconds 0.16 # Real time elapsed on the host
+host_inst_rate 27939 # Simulator instruction rate (inst/s)
+host_op_rate 50607 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 77954156 # Simulator tick rate (ticks/s)
+host_mem_usage 273052 # Number of bytes of host memory used
+host_seconds 0.19 # Real time elapsed on the host
sim_insts 5380 # Number of instructions simulated
-sim_ops 9745 # Number of ops (including micro ops) simulated
+sim_ops 9746 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory
system.physmem.bytes_read::total 28736 # Number of bytes read from this memory
@@ -210,16 +210,16 @@
system.cpu.fetch.CacheLines 1880 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 18583 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.378572 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.879282 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.378787 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.879591 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 14745 79.35% 79.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 189 1.02% 80.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 157 0.84% 81.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 193 1.04% 82.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 162 0.87% 83.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 175 0.94% 84.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 261 1.40% 85.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 171 0.92% 84.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 265 1.43% 85.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 161 0.87% 86.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 2540 13.67% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
@@ -233,44 +233,44 @@
system.cpu.decode.RunCycles 3547 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1830 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 24449 # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts 24452 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1830 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 9798 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 2386 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 485 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 3325 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 759 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 22967 # Number of instructions processed by rename
+system.cpu.rename.RenamedInsts 22970 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 39 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 640 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 25104 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 55188 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 55172 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 25107 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 55203 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 55187 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 11060 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 14044 # Number of HB maps that are undone due to squashing
+system.cpu.rename.CommittedMaps 11061 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 14046 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 31 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 2021 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2205 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1755 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1757 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 20454 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 17349 # Number of instructions issued
+system.cpu.iq.iqInstsAdded 20458 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 35 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 17350 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 213 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 9974 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 13873 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedInstsExamined 9975 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 13877 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 23 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 18583 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.933595 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.794406 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.933649 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.794423 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 13202 71.04% 71.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1386 7.46% 78.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 1042 5.61% 84.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1385 7.45% 78.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 1043 5.61% 84.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 691 3.72% 87.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 742 3.99% 91.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 623 3.35% 95.17% # Number of insts issued each cycle
@@ -315,8 +315,8 @@
system.cpu.iq.fu_full::MemWrite 21 11.80% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 5 0.03% 0.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 13962 80.48% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 13964 80.48% 80.51% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.51% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.51% # Type of FU issued
@@ -345,28 +345,28 @@
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.51% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 1900 10.95% 91.46% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1482 8.54% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 1899 10.95% 91.45% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1483 8.55% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 17349 # Type of FU issued
-system.cpu.iq.rate 0.577742 # Inst issue rate
+system.cpu.iq.FU_type_0::total 17350 # Type of FU issued
+system.cpu.iq.rate 0.577775 # Inst issue rate
system.cpu.iq.fu_busy_cnt 178 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.010260 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 53664 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 30472 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 16003 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate 0.010259 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 53666 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 30475 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 16004 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 17518 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 17520 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 157 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 158 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1153 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 821 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 822 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
@@ -375,44 +375,44 @@
system.cpu.iew.iewSquashCycles 1830 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1703 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 20491 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispatchedInsts 20493 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 33 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2205 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1755 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispStoreInsts 1757 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 601 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 657 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 16425 # Number of executed instructions
+system.cpu.iew.iewExecutedInsts 16426 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 1777 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 924 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3140 # number of memory reference insts executed
+system.cpu.iew.exec_refs 3141 # number of memory reference insts executed
system.cpu.iew.exec_branches 1630 # Number of branches executed
-system.cpu.iew.exec_stores 1363 # Number of stores executed
-system.cpu.iew.exec_rate 0.546971 # Inst execution rate
-system.cpu.iew.wb_sent 16197 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 16007 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 10178 # num instructions producing a value
-system.cpu.iew.wb_consumers 15727 # num instructions consuming a value
+system.cpu.iew.exec_stores 1364 # Number of stores executed
+system.cpu.iew.exec_rate 0.547005 # Inst execution rate
+system.cpu.iew.wb_sent 16198 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 16008 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 10179 # num instructions producing a value
+system.cpu.iew.wb_consumers 15729 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.533051 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.647167 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.533085 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.647149 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 10745 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 10746 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 566 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 16753 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.581687 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.458321 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.581747 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.458276 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 13226 78.95% 78.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1316 7.86% 86.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 596 3.56% 90.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 13224 78.94% 78.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1319 7.87% 86.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 595 3.55% 90.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 710 4.24% 94.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 351 2.10% 96.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 138 0.82% 97.52% # Number of insts commited each cycle
@@ -424,32 +424,32 @@
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 16753 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5380 # Number of instructions committed
-system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps 9746 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 1986 # Number of memory references committed
+system.cpu.commit.refs 1987 # Number of memory references committed
system.cpu.commit.loads 1052 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 1208 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 9650 # Number of committed integer instructions.
+system.cpu.commit.int_insts 9652 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 221 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 37022 # The number of ROB reads
-system.cpu.rob.rob_writes 42839 # The number of ROB writes
+system.cpu.rob.rob_reads 37024 # The number of ROB reads
+system.cpu.rob.rob_writes 42843 # The number of ROB writes
system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 11446 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5380 # Number of Instructions Simulated
-system.cpu.committedOps 9745 # Number of Ops (including micro ops) Simulated
+system.cpu.committedOps 9746 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 5380 # Number of Instructions Simulated
system.cpu.cpi 5.581599 # CPI: Cycles Per Instruction
system.cpu.cpi_total 5.581599 # CPI: Total CPI of All Threads
system.cpu.ipc 0.179160 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.179160 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 28874 # number of integer regfile reads
-system.cpu.int_regfile_writes 17232 # number of integer regfile writes
+system.cpu.int_regfile_reads 28877 # number of integer regfile reads
+system.cpu.int_regfile_writes 17233 # number of integer regfile writes
system.cpu.fp_regfile_reads 4 # number of floating regfile reads
-system.cpu.misc_regfile_reads 7155 # number of misc regfile reads
+system.cpu.misc_regfile_reads 7157 # number of misc regfile reads
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 144.838361 # Cycle average of tags in use
system.cpu.icache.total_refs 1482 # Total number of references to valid blocks.
@@ -534,6 +534,110 @@
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 83.281408 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 15.861111 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 83.281408 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.020332 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.020332 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 1425 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1425 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 859 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 2284 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2284 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2284 # number of overall hits
+system.cpu.dcache.overall_hits::total 2284 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses
+system.cpu.dcache.overall_misses::total 202 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 6336000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 6336000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4220500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 4220500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 10556500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 10556500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 10556500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 10556500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1551 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1551 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 2486 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2486 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2486 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2486 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081238 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.081238 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.081255 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.081255 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.081255 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.081255 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50285.714286 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 50285.714286 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55532.894737 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55532.894737 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 52259.900990 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 52259.900990 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 55 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3735000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 3735000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4068500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4068500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7803500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7803500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7803500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7803500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045777 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045777 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.059131 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.059131 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.633803 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.633803 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53532.894737 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53532.894737 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 178.021325 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
@@ -659,109 +763,5 @@
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38465.853333 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 83.281408 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 15.861111 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 83.281408 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.020332 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.020332 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 1426 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1426 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 2284 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2284 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2284 # number of overall hits
-system.cpu.dcache.overall_hits::total 2284 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses
-system.cpu.dcache.overall_misses::total 202 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 6336000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 6336000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4220500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4220500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 10556500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 10556500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 10556500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 10556500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1552 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1552 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2486 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2486 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2486 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2486 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081186 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.081186 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.081255 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.081255 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.081255 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.081255 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50285.714286 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 50285.714286 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55532.894737 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55532.894737 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 52259.900990 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 52259.900990 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 55 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3735000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 3735000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4068500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4068500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7803500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 7803500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7803500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 7803500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045747 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045747 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.059131 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.059131 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.633803 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.633803 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53532.894737 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53532.894737 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
index d417ce7..dd6c42c 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
@@ -10,7 +10,7 @@
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -68,13 +68,13 @@
[system.cpu.dtb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
-clock=1
+clock=500
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@@ -91,7 +91,7 @@
[system.cpu.itb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.membus.slave[3]
@@ -129,9 +129,9 @@
[system.physmem]
type=SimpleMemory
-clock=1
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr
index ac4ad20..f5691fd 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
index a8facaf..acc9eb2 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
@@ -3,11 +3,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 21:50:34
-gem5 started Sep 10 2012 21:50:39
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 01:20:22
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 5614000 because target called exit()
+Exiting @ tick 5614500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
index 67f8970..da7f097 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
@@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000006 # Number of seconds simulated
-sim_ticks 5614000 # Number of ticks simulated
-final_tick 5614000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 5614500 # Number of ticks simulated
+final_tick 5614500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 59958 # Simulator instruction rate (inst/s)
-host_op_rate 108572 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 62528382 # Simulator tick rate (ticks/s)
-host_mem_usage 261084 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 95396 # Simulator instruction rate (inst/s)
+host_op_rate 172737 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 99466308 # Simulator tick rate (ticks/s)
+host_mem_usage 263448 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
-sim_ops 9746 # Number of ops (including micro ops) simulated
+sim_ops 9747 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7064 # Number of bytes read from this memory
system.physmem.bytes_read::total 61976 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 54912 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 54912 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 7110 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7110 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 7112 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7112 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 6864 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1052 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7916 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 934 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 934 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 9781261133 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1258282864 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 11039543997 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 9781261133 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 9781261133 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1266476665 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1266476665 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 9781261133 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2524759530 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 12306020663 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_writes::cpu.data 935 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 935 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 9780390061 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1258170808 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 11038560869 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 9780390061 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 9780390061 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1266720100 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1266720100 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 9780390061 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2524890907 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 12305280969 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 11229 # number of cpu cycles simulated
+system.cpu.numCycles 11230 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 5381 # Number of instructions committed
-system.cpu.committedOps 9746 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 9651 # Number of integer alu accesses
+system.cpu.committedOps 9747 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 9653 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls
-system.cpu.num_int_insts 9651 # number of integer instructions
+system.cpu.num_int_insts 9653 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 24812 # number of times the integer registers were read
-system.cpu.num_int_register_writes 11060 # number of times the integer registers were written
+system.cpu.num_int_register_reads 24817 # number of times the integer registers were read
+system.cpu.num_int_register_writes 11061 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 1986 # number of memory refs
+system.cpu.num_mem_refs 1987 # number of memory refs
system.cpu.num_load_insts 1052 # Number of load instructions
-system.cpu.num_store_insts 934 # Number of store instructions
+system.cpu.num_store_insts 935 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 11229 # Number of busy cycles
+system.cpu.num_busy_cycles 11230 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
index d97af8c..33bd113 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
@@ -130,7 +130,7 @@
[system.dir_cntrl0.directory]
type=RubyDirectoryMemory
map_levels=4
-numa_high_bit=6
+numa_high_bit=5
size=134217728
use_map=false
version=0
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
index 5f61ae7..87c404f 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Sep/10/2012 21:50:40
+Real time: Dec/30/2012 01:12:43
Profiler Stats
--------------
@@ -7,18 +7,18 @@
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.48
-Virtual_time_in_minutes: 0.008
-Virtual_time_in_hours: 0.000133333
-Virtual_time_in_days: 5.55556e-06
+Virtual_time_in_seconds: 0.51
+Virtual_time_in_minutes: 0.0085
+Virtual_time_in_hours: 0.000141667
+Virtual_time_in_days: 5.90278e-06
Ruby_current_time: 121759
Ruby_start_time: 0
Ruby_cycles: 121759
-mbytes_resident: 57.9453
-mbytes_total: 275.082
-resident_ratio: 0.210662
+mbytes_resident: 60.1836
+mbytes_total: 277.391
+resident_ratio: 0.217006
ruby_cycles_executed: [ 121760 ]
@@ -29,17 +29,17 @@
Busy Bank Count:0
-sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8851 average: 1 | standard deviation: 0 | 0 8851 ]
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8852 average: 1 | standard deviation: 0 | 0 8852 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
-miss_latency: [binsize: 1 max: 125 count: 8850 average: 12.7581 | standard deviation: 22.8706 | 0 0 0 7473 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 314 433 491 10 7 5 9 5 11 0 1 0 1 0 0 0 1 1 0 0 1 0 0 2 0 0 0 9 16 40 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency: [binsize: 1 max: 125 count: 8851 average: 12.7565 | standard deviation: 22.8681 | 0 0 0 7474 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 313 433 492 10 6 5 9 6 11 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 9 16 39 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_LD: [binsize: 1 max: 101 count: 1044 average: 33.113 | standard deviation: 31.8551 | 0 0 0 545 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 2 97 201 150 1 3 2 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 3 5 22 0 0 1 0 0 0 0 0 1 ]
-miss_latency_ST: [binsize: 1 max: 92 count: 934 average: 20.1188 | standard deviation: 28.2308 | 0 0 0 680 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 62 106 3 0 0 2 0 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 2 3 9 ]
-miss_latency_IFETCH: [binsize: 1 max: 125 count: 6864 average: 8.66288 | standard deviation: 18.0056 | 0 0 0 6241 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 158 170 234 6 4 3 7 4 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_ST: [binsize: 1 max: 92 count: 935 average: 20.0877 | standard deviation: 28.194 | 0 0 0 681 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 62 106 3 0 0 2 0 3 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 3 9 ]
+miss_latency_IFETCH: [binsize: 1 max: 125 count: 6864 average: 8.66404 | standard deviation: 18.01 | 0 0 0 6241 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 157 170 235 6 3 3 7 5 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 8 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_RMW_Read: [binsize: 1 max: 65 count: 8 average: 10.75 | standard deviation: 21.9219 | 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_L1Cache: [binsize: 1 max: 3 count: 7473 average: 3 | standard deviation: 0 | 0 0 0 7473 ]
-miss_latency_Directory: [binsize: 1 max: 125 count: 1377 average: 65.7153 | standard deviation: 6.33839 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 314 433 491 10 7 5 9 5 11 0 1 0 1 0 0 0 1 1 0 0 1 0 0 2 0 0 0 9 16 40 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_L1Cache: [binsize: 1 max: 3 count: 7474 average: 3 | standard deviation: 0 | 0 0 0 7474 ]
+miss_latency_Directory: [binsize: 1 max: 125 count: 1377 average: 65.7124 | standard deviation: 6.32886 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 313 433 492 10 6 5 9 6 11 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 9 16 39 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -52,10 +52,10 @@
imcomplete_dir_Times: 1376
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 545 average: 3 | standard deviation: 0 | 0 0 0 545 ]
miss_latency_LD_Directory: [binsize: 1 max: 101 count: 499 average: 66.002 | standard deviation: 7.00186 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 2 97 201 150 1 3 2 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 3 5 22 0 0 1 0 0 0 0 0 1 ]
-miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 680 average: 3 | standard deviation: 0 | 0 0 0 680 ]
-miss_latency_ST_Directory: [binsize: 1 max: 92 count: 254 average: 65.9488 | standard deviation: 6.5357 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 62 106 3 0 0 2 0 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 2 3 9 ]
+miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 681 average: 3 | standard deviation: 0 | 0 0 0 681 ]
+miss_latency_ST_Directory: [binsize: 1 max: 92 count: 254 average: 65.9016 | standard deviation: 6.43269 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 62 106 3 0 0 2 0 3 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 3 9 ]
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 6241 average: 3 | standard deviation: 0 | 0 0 0 6241 ]
-miss_latency_IFETCH_Directory: [binsize: 1 max: 125 count: 623 average: 65.3917 | standard deviation: 5.66183 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 158 170 234 6 4 3 7 4 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_IFETCH_Directory: [binsize: 1 max: 125 count: 623 average: 65.4045 | standard deviation: 5.68761 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 157 170 235 6 3 3 7 5 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 8 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_RMW_Read_L1Cache: [binsize: 1 max: 3 count: 7 average: 3 | standard deviation: 0 | 0 0 0 7 ]
miss_latency_RMW_Read_Directory: [binsize: 1 max: 65 count: 1 average: 65 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
@@ -89,10 +89,10 @@
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 11940
-page_faults: 0
+page_reclaims: 12527
+page_faults: 3
swaps: 0
-block_inputs: 24
+block_inputs: 1360
block_outputs: 88
Network Stats
@@ -154,7 +154,7 @@
- Event Counts -
Load [1044 ] 1044
Ifetch [6864 ] 6864
-Store [942 ] 942
+Store [943 ] 943
Data [1377 ] 1377
Fwd_GETX [0 ] 0
Inv [0 ] 0
@@ -173,7 +173,7 @@
M Load [545 ] 545
M Ifetch [6241 ] 6241
-M Store [687 ] 687
+M Store [688 ] 688
M Fwd_GETX [0 ] 0
M Inv [0 ] 0
M Replacement [1373 ] 1373
@@ -194,16 +194,16 @@
memory_reads: 1377
memory_writes: 1373
memory_refreshes: 846
- memory_total_request_delays: 1965
- memory_delays_per_request: 0.714545
+ memory_total_request_delays: 1964
+ memory_delays_per_request: 0.714182
memory_delays_in_input_queue: 0
- memory_delays_behind_head_of_bank_queue: 3
- memory_delays_stalled_at_head_of_bank_queue: 1962
- memory_stalls_for_bank_busy: 830
+ memory_delays_behind_head_of_bank_queue: 4
+ memory_delays_stalled_at_head_of_bank_queue: 1960
+ memory_stalls_for_bank_busy: 826
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
memory_stalls_for_arbitration: 62
- memory_stalls_for_bus: 1039
+ memory_stalls_for_bus: 1041
memory_stalls_for_tfaw: 0
memory_stalls_for_read_write_turnaround: 31
memory_stalls_for_read_read_turnaround: 0
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr
index ac4ad20..723b376 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr
@@ -1,4 +1,7 @@
+Warning: rounding error > tolerance
+ 0.072760 rounded to 0
+Warning: rounding error > tolerance
+ 0.072760 rounded to 0
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
index 33d7b7d..55cf80c 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
@@ -3,8 +3,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 21:50:34
-gem5 started Sep 10 2012 21:50:39
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 01:12:43
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
index 6f71154..3695896 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
@@ -4,35 +4,35 @@
sim_ticks 121759 # Number of ticks simulated
final_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 21174 # Simulator instruction rate (inst/s)
-host_op_rate 38347 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 479042 # Simulator tick rate (ticks/s)
-host_mem_usage 281688 # Number of bytes of host memory used
-host_seconds 0.25 # Real time elapsed on the host
+host_inst_rate 28531 # Simulator instruction rate (inst/s)
+host_op_rate 51675 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 645460 # Simulator tick rate (ticks/s)
+host_mem_usage 284052 # Number of bytes of host memory used
+host_seconds 0.19 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
-sim_ops 9746 # Number of ops (including micro ops) simulated
+sim_ops 9747 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7064 # Number of bytes read from this memory
system.physmem.bytes_read::total 61976 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 54912 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 54912 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 7110 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7110 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 7112 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7112 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 6864 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1052 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7916 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 934 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 934 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data 935 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 935 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 450989249 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 58016245 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 509005494 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 450989249 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 450989249 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 58394041 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 58394041 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 58410467 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 58410467 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 450989249 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 116410286 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 567399535 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 116426712 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 567415961 # Total bandwidth to/from this memory (bytes/s)
system.l1_cntrl0.cacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.cacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.cacheMemory.num_tag_array_reads 0 # number of tag array reads
@@ -44,20 +44,20 @@
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 5381 # Number of instructions committed
-system.cpu.committedOps 9746 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 9651 # Number of integer alu accesses
+system.cpu.committedOps 9747 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 9653 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls
-system.cpu.num_int_insts 9651 # number of integer instructions
+system.cpu.num_int_insts 9653 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 24812 # number of times the integer registers were read
-system.cpu.num_int_register_writes 11060 # number of times the integer registers were written
+system.cpu.num_int_register_reads 24817 # number of times the integer registers were read
+system.cpu.num_int_register_writes 11061 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 1986 # number of memory refs
+system.cpu.num_mem_refs 1987 # number of memory refs
system.cpu.num_load_insts 1052 # Number of load instructions
-system.cpu.num_store_insts 934 # Number of store instructions
+system.cpu.num_store_insts 935 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 121759 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
index 45681eb..f8e4933 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -10,7 +10,7 @@
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -61,22 +61,22 @@
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
-response_latency=1000
+response_latency=2
size=262144
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
@@ -91,7 +91,7 @@
[system.cpu.dtb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.cpu.toL2Bus.slave[3]
@@ -100,22 +100,22 @@
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
-response_latency=1000
+response_latency=2
size=131072
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
@@ -124,7 +124,7 @@
[system.cpu.interrupts]
type=X86LocalApic
-clock=1
+clock=500
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@@ -141,31 +141,31 @@
[system.cpu.itb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
-response_latency=10000
+response_latency=20
size=2097152
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
@@ -175,10 +175,10 @@
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@@ -217,7 +217,7 @@
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr
index ac4ad20..f5691fd 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
index 6c9c7da..dd8505c 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
@@ -3,11 +3,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 21:50:34
-gem5 started Sep 10 2012 21:50:39
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 01:20:12
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 29676000 because target called exit()
+Exiting @ tick 28357000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
index bc10302..ce11ecf 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000028 # Number of seconds simulated
-sim_ticks 28356000 # Number of ticks simulated
-final_tick 28356000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 28357000 # Number of ticks simulated
+final_tick 28357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 134366 # Simulator instruction rate (inst/s)
-host_op_rate 243261 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 707485860 # Simulator tick rate (ticks/s)
-host_mem_usage 226568 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
+host_inst_rate 86866 # Simulator instruction rate (inst/s)
+host_op_rate 157296 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 457476490 # Simulator tick rate (ticks/s)
+host_mem_usage 271900 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
-sim_ops 9746 # Number of ops (including micro ops) simulated
+sim_ops 9747 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
system.physmem.bytes_read::total 23104 # Number of bytes read from this memory
@@ -19,46 +19,46 @@
system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
system.physmem.num_reads::total 361 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 512343067 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 302440401 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 814783467 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 512343067 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 512343067 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 512343067 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 302440401 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 814783467 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 512324999 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 302429735 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 814754734 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 512324999 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 512324999 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 512324999 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 302429735 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 814754734 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 56712 # number of cpu cycles simulated
+system.cpu.numCycles 56714 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 5381 # Number of instructions committed
-system.cpu.committedOps 9746 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 9651 # Number of integer alu accesses
+system.cpu.committedOps 9747 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 9653 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls
-system.cpu.num_int_insts 9651 # number of integer instructions
+system.cpu.num_int_insts 9653 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 24812 # number of times the integer registers were read
-system.cpu.num_int_register_writes 11060 # number of times the integer registers were written
+system.cpu.num_int_register_reads 24817 # number of times the integer registers were read
+system.cpu.num_int_register_writes 11061 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 1986 # number of memory refs
+system.cpu.num_mem_refs 1987 # number of memory refs
system.cpu.num_load_insts 1052 # Number of load instructions
-system.cpu.num_store_insts 934 # Number of store instructions
+system.cpu.num_store_insts 935 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 56712 # Number of busy cycles
+system.cpu.num_busy_cycles 56714 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 105.556077 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 105.553131 # Cycle average of tags in use
system.cpu.icache.total_refs 6637 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 29.109649 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 105.556077 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.051541 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.051541 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst 105.553131 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.051540 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.051540 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits
@@ -129,22 +129,22 @@
system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 80.800961 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1852 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 80.799099 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1853 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 13.820896 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 13.828358 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 80.800961 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.019727 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.019727 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data 80.799099 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.019726 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 997 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 997 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 855 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 855 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1852 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1852 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1852 # number of overall hits
-system.cpu.dcache.overall_hits::total 1852 # number of overall hits
+system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 1853 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1853 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1853 # number of overall hits
+system.cpu.dcache.overall_hits::total 1853 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses
@@ -163,20 +163,20 @@
system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1052 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1052 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 1986 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 1986 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 1986 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 1986 # number of overall (read+write) accesses
+system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 1987 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 1987 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 1987 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 1987 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052281 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.052281 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084582 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.084582 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.067472 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.067472 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.067472 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.067472 # miss rate for overall accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.067438 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.067438 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.067438 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.067438 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
@@ -211,12 +211,12 @@
system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052281 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052281 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084582 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084582 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067472 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.067472 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067472 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.067472 # mshr miss rate for overall accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067438 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.067438 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067438 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.067438 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
@@ -227,14 +227,14 @@
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 134.040949 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 134.037527 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 105.564188 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 28.476761 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.003222 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst 105.561241 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 28.476285 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.004091 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
