tree c8f05c9f521bec9880b6db5e796f500cae4799c5
parent 272e4aa26d8c99ea2043a12e49ac25b2e81fc7ac
author Jan-Peter Larsson <jan-peter.larsson@arm.com> 1545321356 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> 1546608280 +0000

dev, arm: Warn on PL011 DMA disable

The PL011 spec specifies a DMACR register at offset 0x48, which isn't
implemented in the model. Currently any attempt to access the register
results in a panic.

This change swaps the panic for a warning only when software writes into
DMACR to disable DMA, keeping the panic otherwise.

Change-Id: I04586b52df8d5d174536276fd7ae19e77ff4681a
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15279
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>