tree b509597b23d792734f55c33b8125eebfbd9cd3a5
parent c6f5db8743f19b02a38146d9cf2a829883387008
author Giacomo Gabrielli <giacomo.gabrielli@arm.com> 1539702248 +0100
committer Giacomo Gabrielli <giacomo.gabrielli@arm.com> 1548867474 +0000

arch,cpu: Add vector predicate registers

Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector
Extension (SVE), introduce the notion of a predicate register file.
This changeset adds this feature across architectures and CPU models.

Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13715
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>