tree 5dff2562a62c9d7973186c1e16042c3108007c55
parent 7d71f6641fcb660de0f003e2c028b464d7116ca1
author Gabor Dozsa <gabor.dozsa@arm.com> 1529942366 +0100
committer Gabor Dozsa <gabor.dozsa@arm.com> 1550837780 +0000

cpu-o3: Add cache read ports limit to LSQ

This change introduces cache read ports to limit the number of
per-cycle loads. Previously only the number of per-cycle stores
could be limited.

Change-Id: I39bbd984056c5a696725ee2db462a55b2079e2d4
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13517
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>