)]}'
{
  "commit": "3d15150d715521b8ff9778dbc90061dc9ab72b8e",
  "tree": "2bd6860cf7fe886ed4157b2ed4134c19aba68a07",
  "parents": [
    "204e932607aa582cd7036b08e20521c2c6c49941"
  ],
  "author": {
    "name": "Giacomo Travaglini",
    "email": "giacomo.travaglini@arm.com",
    "time": "Thu Jan 10 17:26:00 2019 +0000"
  },
  "committer": {
    "name": "Giacomo Travaglini",
    "email": "giacomo.travaglini@arm.com",
    "time": "Fri Jan 25 12:55:27 2019 +0000"
  },
  "message": "cpu, arch, arch-arm: Wire unused VecElem code in the O3 model\n\nVecElem code had been introduced in order to simulate change of renaming\nfor vector registers. Most of the work is happening on the rename_map\nswitchRenameMode. Change of renaming can happen after a squash in the\npipeline.\nThis patch is also changing the interface to the ISA part so that\na PCState is used instead of ISA in order to check if rename mode\nhas changed.\n\nChange-Id: I8af795d771b958e0a0d459abfeceff5f16b4b5d4\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/15601\n",
  "tree_diff": [
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