tree 2bd6860cf7fe886ed4157b2ed4134c19aba68a07
parent 204e932607aa582cd7036b08e20521c2c6c49941
author Giacomo Travaglini <giacomo.travaglini@arm.com> 1547141160 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> 1548420927 +0000

cpu, arch, arch-arm: Wire unused VecElem code in the O3 model

VecElem code had been introduced in order to simulate change of renaming
for vector registers. Most of the work is happening on the rename_map
switchRenameMode. Change of renaming can happen after a squash in the
pipeline.
This patch is also changing the interface to the ISA part so that
a PCState is used instead of ISA in order to check if rename mode
has changed.

Change-Id: I8af795d771b958e0a0d459abfeceff5f16b4b5d4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15601