diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 52c42cb..b4e8536 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -87,10 +87,6 @@
     id_aa64afr1_el1 = Param.UInt64(0x0000000000000000,
         "AArch64 Auxiliary Feature Register 1")
 
-    # Initial vector register rename mode
-    vecRegRenameMode = Param.VecRegRenameMode('Full',
-        "Initial rename mode for vecregs")
-
     # 1 CTX CMPs | 2 WRPs | 2 BRPs | !PMU | !Trace | Debug v8-A
     id_aa64dfr0_el1 = Param.UInt64(0x0000000000101006,
         "AArch64 Debug Feature Register 0")
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 6cbf8db..97de97e 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -62,7 +62,7 @@
     : SimObject(p),
       system(NULL),
       _decoderFlavour(p->decoderFlavour),
-      _vecRegRenameMode(p->vecRegRenameMode),
+      _vecRegRenameMode(Enums::Full),
       pmu(p->pmu),
       impdefAsNop(p->impdef_nop)
 {
@@ -103,6 +103,10 @@
         haveGICv3CPUInterface = true;
     }
 
+    // Initial rename mode depends on highestEL
+    const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) =
+        highestELIs64 ? Enums::Full : Enums::Elem;
+
     initializeMiscRegMetadata();
     preUnflattenMiscReg();