)]}' { "commit": "51becd2475748fb5515f261254c48827b3b5c2ba", "tree": "2aabad4aad0ee7528ec437783b3077080ddb657a", "parents": [ "6379bebd41899ca74ac146e8073aee0bd1781b3f" ], "author": { "name": "Rekai Gonzalez-Alberquilla", "email": "rekai.gonzalezalberquilla@arm.com", "time": "Mon Feb 13 09:41:44 2017 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Thu Jan 24 09:46:34 2019 +0000" }, "message": "cpu-o3: O3 LSQ Generalisation\n\nThis patch does a large modification of the LSQ in the O3 model. The\nmain goal of the patch is to remove the \u0027an operation can be served with\none or two memory requests\u0027 assumption that is present in the LSQ\nand the instruction with the req, reqLow, reqHigh triplet, and\ngeneralising it to operations that can be addressed with one request,\nand operations that require many requests, embodied in the\nSingleDataRequest and the SplitDataRequest.\n\nThis modification has been done mimicking the minor model to an extent,\nshifting the responsibilities of dealing with VtoP translation and\ntracking the status and resources from the DynInst to the LSQ via the\nLSQRequest. The LSQRequest models the information concerning the\noperation, handles the creation of fragments for translation and request\nas well as assembling/splitting the data accordingly.\n\nWith this modifications, the implementation of vector ISAs, particularly\non the memory side, become more rich, as the new model permits a\ndissociation of the ISA characteristics as vector length, from the\nmicroarchitectural characteristics that govern how contiguous loads are\nexecuting, allowing exploration of different LSQ to DL1 bus widths to\nunderstand the tradeoffs in complexity and performance.\n\nPart of the complexities introduced stem from the fact that gem5 keeps a\nlarge amount of metadata regarding, in particular, memory operations,\nthus, when an instruction is squashed while some operation as TLB lookup\nor cache access is ongoing, when the relevant structure communicates to\nthe LSQ that the operation is over, it tries to access some pieces of\ndata that should have died when the instruction is squashed, leading to\nasserts, panics, or memory corruption. To ensure the correct behaviour,\nthe LSQRequest rely on assesing who is their owner, and self-destroying\nif they detect their owner is done with the request, and there will be\nno subsequent action. For example, in the case of an instruction\nsquashed whal the TLB is doing a walk to serve the translation, when the\ntranslation is served by the TLB, the LSQRequest detects that the\ninstruction was squashed, and as the translation is done, no one else\nexpect to access its information, and therefore, it self-destructs.\nHaving destroyed the LSQRequest earlier, would lead to wrong behaviour\nas the TLB walk may access some fields of it.\n\nAdditional authors:\n- Gabor Dozsa \u003cgabor.dozsa@arm.com\u003e\n\nChange-Id: I9578a1a3f6b899c390cdd886856a24db68ff7d0c\nSigned-off-by: Giacomo Gabrielli \u003cgiacomo.gabrielli@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/13516\nReviewed-by: Anthony Gutierrez \u003canthony.gutierrez@amd.com\u003e\nMaintainer: Anthony Gutierrez \u003canthony.gutierrez@amd.com\u003e\n", "tree_diff": [ { "type": "modify", "old_id": "197e418328012ea4a1ce0f524909f60da4f81382", "old_mode": 33188, "old_path": "src/base/refcnt.hh", "new_id": "53bb1ae7bc14f4aa8dca6a866a458ca2e35a3cf5", "new_mode": 33188, "new_path": "src/base/refcnt.hh" }, { "type": "modify", "old_id": "c2a14089a5c8c9327e722601350e4bd81f9402ca", "old_mode": 33188, "old_path": "src/cpu/base_dyn_inst.hh", "new_id": "d81b58bdf142ed8510a62d3a7d8fca04ff6b10f1", "new_mode": 33188, "new_path": "src/cpu/base_dyn_inst.hh" }, { "type": "modify", "old_id": "cd4740de5c5a0cb753b9ba72921812669b57168e", "old_mode": 33188, "old_path": "src/cpu/base_dyn_inst_impl.hh", "new_id": "d8473f7d51ab0e6ec1c658c3603eca54b99ef7c5", "new_mode": 33188, "new_path": "src/cpu/base_dyn_inst_impl.hh" }, { "type": "modify", "old_id": "600c89aa5bc3f7aab31479289c61d849f4603594", "old_mode": 33188, "old_path": "src/cpu/o3/cpu.cc", "new_id": "7261f0c9eb2309517af0dd72dfcafebfd8698faa", "new_mode": 33188, "new_path": "src/cpu/o3/cpu.cc" }, { "type": "modify", "old_id": "90024bc84062d98a06d1fe462593443650af9855", "old_mode": 33188, "old_path": "src/cpu/o3/cpu.hh", "new_id": "1159850f82f976d424972400fe83ec5940e113ce", "new_mode": 33188, "new_path": "src/cpu/o3/cpu.hh" }, { "type": "modify", "old_id": "e706b09a187304e2dcd04475987a988c4407de7a", "old_mode": 33188, "old_path": "src/cpu/o3/iew_impl.hh", "new_id": "3d5d848864d8015ef7f65d0f6d5e0bdacf3d46bd", "new_mode": 33188, "new_path": "src/cpu/o3/iew_impl.hh" }, { "type": "modify", "old_id": "a8895f8ffe84b84b9fab228ee57f00bd2e613589", "old_mode": 33188, "old_path": "src/cpu/o3/inst_queue_impl.hh", "new_id": "4a55a91ead97292e6df624d06d2d6cf9094eaed5", "new_mode": 33188, "new_path": "src/cpu/o3/inst_queue_impl.hh" }, { "type": "modify", "old_id": "2b2d39bf741d111112dfaa51460f0f53ad86210c", "old_mode": 33188, "old_path": "src/cpu/o3/lsq.hh", "new_id": "003726c7c47324dbbe80d95b5765c11318ee4307", "new_mode": 33188, "new_path": "src/cpu/o3/lsq.hh" }, { "type": "modify", "old_id": "edc3f469bc56556d85d1f761277f921c309bdba6", "old_mode": 33188, "old_path": "src/cpu/o3/lsq_impl.hh", "new_id": "8a221a8d5e7ed1469b31666d0d6fb92c0fd64dea", "new_mode": 33188, "new_path": "src/cpu/o3/lsq_impl.hh" }, { "type": "modify", "old_id": "48a06b386a098d02c77a9c28deb728c52ee2e0da", "old_mode": 33188, "old_path": "src/cpu/o3/lsq_unit.hh", "new_id": "5b90da4f509346f6f5464adf3e79bbf93a9570e8", "new_mode": 33188, "new_path": "src/cpu/o3/lsq_unit.hh" }, { "type": "modify", "old_id": "13b1487684bc7112b5b24888928c60aab7587d19", "old_mode": 33188, "old_path": "src/cpu/o3/lsq_unit_impl.hh", "new_id": "9756a9ef144e8219f868c8e19cf7cc4c4e2331aa", "new_mode": 33188, "new_path": "src/cpu/o3/lsq_unit_impl.hh" }, { "type": "modify", "old_id": "a4a201398ba7603b638e38ad0e958365c4c9bba5", "old_mode": 33188, "old_path": "src/cpu/o3/probe/elastic_trace.cc", "new_id": "36d8297d1baa0698a5a5beebc12b9b8099c57128", "new_mode": 33188, "new_path": "src/cpu/o3/probe/elastic_trace.cc" } ] }