)]}'
{
  "commit": "529d0cdbfe77a4ad655fe57f2d5320dbb760ef13",
  "tree": "8c2433849ffe84bf3278140ea9a260e74ace202e",
  "parents": [
    "07eca72e1a51910e8ff785c224bf3820183d3664"
  ],
  "author": {
    "name": "Jason Lowe-Power",
    "email": "jason@lowepower.com",
    "time": "Thu Apr 04 14:10:16 2019 -0700"
  },
  "committer": {
    "name": "Jason Lowe-Power",
    "email": "jason@lowepower.com",
    "time": "Fri Apr 05 17:36:37 2019 +0000"
  },
  "message": "mem: Reverse order of write/read mem queue check\n\nFor atomic RMW instructions that go directly to memory, we want to put\nthem on the write queue instead of the read queue. Swap the if/else\ncondition to accomplish this.\n\nNote: This is ignoring the read latency of the RMW, but these\ninstructions should usually be handled in caches anyway.\n\nChange-Id: I62dbfff3a16ac470f1ebdb489abe878962b20bb6\nSigned-off-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17828\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "dd03cf1133ec90adf1fa2cee6a5e0a197ee60f6d",
      "old_mode": 33188,
      "old_path": "src/mem/dram_ctrl.cc",
      "new_id": "e89a47a724df9b7cb9fef134c3d8a318f03cd5f5",
      "new_mode": 33188,
      "new_path": "src/mem/dram_ctrl.cc"
    }
  ]
}