stats: update for O3 changes
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.
30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
index bff2388..4b7f3d4 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
@@ -1,154 +1,154 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 2.550603 # Number of seconds simulated
-sim_ticks 2550603285500 # Number of ticks simulated
-final_tick 2550603285500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.550237 # Number of seconds simulated
+sim_ticks 2550237191000 # Number of ticks simulated
+final_tick 2550237191000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 56179 # Simulator instruction rate (inst/s)
-host_op_rate 72287 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2375661490 # Simulator tick rate (ticks/s)
-host_mem_usage 471120 # Number of bytes of host memory used
-host_seconds 1073.64 # Real time elapsed on the host
-sim_insts 60315997 # Number of instructions simulated
-sim_ops 77609994 # Number of ops (including micro ops) simulated
+host_inst_rate 66377 # Simulator instruction rate (inst/s)
+host_op_rate 85409 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2806608319 # Simulator tick rate (ticks/s)
+host_mem_usage 421988 # Number of bytes of host memory used
+host_seconds 908.65 # Real time elapsed on the host
+sim_insts 60314055 # Number of instructions simulated
+sim_ops 77607027 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 1984 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 487168 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 5091220 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 310848 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4002308 # Number of bytes read from this memory
-system.physmem.bytes_read::total 131004952 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 487168 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 310848 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 798016 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3785472 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1521388 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 1494684 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6801544 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker 2240 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 507520 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 5298200 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 292352 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 3795584 # Number of bytes read from this memory
+system.physmem.bytes_read::total 131007192 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 507520 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 292352 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 799872 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3786240 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 1521400 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 1494672 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6802312 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 31 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 7612 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 79585 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 4857 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 62537 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15293452 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59148 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 380347 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 373671 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813166 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47483091 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 778 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 191001 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1996085 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 301 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 121872 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1569161 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51362340 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 191001 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 121872 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 312873 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1484148 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 596482 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 586012 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2666641 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1484148 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47483091 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 778 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 191001 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 2592566 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 301 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 121872 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 2155173 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54028981 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15293452 # Number of read requests accepted
-system.physmem.writeReqs 813166 # Number of write requests accepted
-system.physmem.readBursts 15293452 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 813166 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 977025792 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 1755136 # Total number of bytes read from write queue
-system.physmem.bytesWritten 6829888 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 131004952 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 6801544 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 27424 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 706426 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 4680 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 955870 # Per bank write bursts
-system.physmem.perBankRdBursts::1 953353 # Per bank write bursts
-system.physmem.perBankRdBursts::2 953267 # Per bank write bursts
-system.physmem.perBankRdBursts::3 953402 # Per bank write bursts
-system.physmem.perBankRdBursts::4 955744 # Per bank write bursts
-system.physmem.perBankRdBursts::5 953745 # Per bank write bursts
-system.physmem.perBankRdBursts::6 953482 # Per bank write bursts
-system.physmem.perBankRdBursts::7 953247 # Per bank write bursts
-system.physmem.perBankRdBursts::8 956258 # Per bank write bursts
-system.physmem.perBankRdBursts::9 953771 # Per bank write bursts
-system.physmem.perBankRdBursts::10 953551 # Per bank write bursts
-system.physmem.perBankRdBursts::11 953111 # Per bank write bursts
-system.physmem.perBankRdBursts::12 956206 # Per bank write bursts
-system.physmem.perBankRdBursts::13 953857 # Per bank write bursts
-system.physmem.perBankRdBursts::14 953612 # Per bank write bursts
-system.physmem.perBankRdBursts::15 953552 # Per bank write bursts
-system.physmem.perBankWrBursts::0 6609 # Per bank write bursts
-system.physmem.perBankWrBursts::1 6381 # Per bank write bursts
-system.physmem.perBankWrBursts::2 6537 # Per bank write bursts
-system.physmem.perBankWrBursts::3 6560 # Per bank write bursts
-system.physmem.perBankWrBursts::4 6488 # Per bank write bursts
+system.physmem.num_reads::cpu0.dtb.walker 35 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 7930 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 82820 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 4568 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 59306 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15293487 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59160 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 380350 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 373668 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 813178 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47489907 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 878 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 199009 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 2077532 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 276 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 114637 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 1488326 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51370591 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 199009 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 114637 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 313646 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1484662 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 596572 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 586091 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2667325 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1484662 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47489907 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 878 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 199009 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 2674104 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 276 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 114637 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 2074417 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 54037916 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15293487 # Number of read requests accepted
+system.physmem.writeReqs 813178 # Number of write requests accepted
+system.physmem.readBursts 15293487 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 813178 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 977052352 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 1730816 # Total number of bytes read from write queue
+system.physmem.bytesWritten 6829312 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 131007192 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 6802312 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 27044 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 706441 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 4687 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 955866 # Per bank write bursts
+system.physmem.perBankRdBursts::1 953274 # Per bank write bursts
+system.physmem.perBankRdBursts::2 953247 # Per bank write bursts
+system.physmem.perBankRdBursts::3 953514 # Per bank write bursts
+system.physmem.perBankRdBursts::4 955750 # Per bank write bursts
+system.physmem.perBankRdBursts::5 953800 # Per bank write bursts
+system.physmem.perBankRdBursts::6 953588 # Per bank write bursts
+system.physmem.perBankRdBursts::7 953504 # Per bank write bursts
+system.physmem.perBankRdBursts::8 956261 # Per bank write bursts
+system.physmem.perBankRdBursts::9 953859 # Per bank write bursts
+system.physmem.perBankRdBursts::10 953506 # Per bank write bursts
+system.physmem.perBankRdBursts::11 952990 # Per bank write bursts
+system.physmem.perBankRdBursts::12 956201 # Per bank write bursts
+system.physmem.perBankRdBursts::13 953861 # Per bank write bursts
+system.physmem.perBankRdBursts::14 953718 # Per bank write bursts
+system.physmem.perBankRdBursts::15 953504 # Per bank write bursts
+system.physmem.perBankWrBursts::0 6593 # Per bank write bursts
+system.physmem.perBankWrBursts::1 6395 # Per bank write bursts
+system.physmem.perBankWrBursts::2 6535 # Per bank write bursts
+system.physmem.perBankWrBursts::3 6562 # Per bank write bursts
+system.physmem.perBankWrBursts::4 6485 # Per bank write bursts
system.physmem.perBankWrBursts::5 6754 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6745 # Per bank write bursts
-system.physmem.perBankWrBursts::7 6685 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7023 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6801 # Per bank write bursts
-system.physmem.perBankWrBursts::10 6470 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6120 # Per bank write bursts
-system.physmem.perBankWrBursts::12 7060 # Per bank write bursts
-system.physmem.perBankWrBursts::13 6677 # Per bank write bursts
-system.physmem.perBankWrBursts::14 6963 # Per bank write bursts
-system.physmem.perBankWrBursts::15 6844 # Per bank write bursts
+system.physmem.perBankWrBursts::6 6752 # Per bank write bursts
+system.physmem.perBankWrBursts::7 6692 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7013 # Per bank write bursts
+system.physmem.perBankWrBursts::9 6813 # Per bank write bursts
+system.physmem.perBankWrBursts::10 6467 # Per bank write bursts
+system.physmem.perBankWrBursts::11 6119 # Per bank write bursts
+system.physmem.perBankWrBursts::12 7057 # Per bank write bursts
+system.physmem.perBankWrBursts::13 6685 # Per bank write bursts
+system.physmem.perBankWrBursts::14 6965 # Per bank write bursts
+system.physmem.perBankWrBursts::15 6821 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2550602119500 # Total gap between requests
+system.physmem.totGap 2550236004000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 38 # Read request sizes (log2)
system.physmem.readPktSize::3 15138816 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 154598 # Read request sizes (log2)
+system.physmem.readPktSize::6 154633 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 754018 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 59148 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1066844 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1005139 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 964469 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1068011 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 971384 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1033822 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2692544 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 2602827 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 3401172 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 112530 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 102949 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 95927 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 92392 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 19066 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 18545 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 18331 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 57 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 13 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 59160 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 1068642 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 1003556 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 964678 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 1068028 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 971433 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1034228 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2693278 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 2602966 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 3400925 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 112135 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 102170 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 95874 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 92374 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 19109 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 18588 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 18396 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 38 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 14 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
@@ -161,43 +161,43 @@
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 297 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 298 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 293 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 289 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 287 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 282 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 280 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 278 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 275 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 272 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 268 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 265 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 263 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 263 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 288 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 286 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 283 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 279 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 260 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::26 5943 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 5910 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 6309 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 5883 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 5894 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 5982 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 5778 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 98 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 67 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 33 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::26 5934 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 5931 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 6266 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 5878 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 5861 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 5998 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 5786 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 113 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 83 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
@@ -225,95 +225,96 @@
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1010962 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 973.187598 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 908.669037 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 201.227455 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 22588 2.23% 2.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 20116 1.99% 4.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 8785 0.87% 5.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2331 0.23% 5.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2167 0.21% 5.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1761 0.17% 5.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 9115 0.90% 6.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 858 0.08% 6.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 943241 93.30% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1010962 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6071 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 2514.580135 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 47785.198367 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-65535 6044 99.56% 99.56% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.57% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.70% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-262143 6 0.10% 99.80% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 1011151 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 973.031391 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 908.214038 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 201.586844 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 22832 2.26% 2.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 19987 1.98% 4.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 8899 0.88% 5.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2276 0.23% 5.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2117 0.21% 5.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1805 0.18% 5.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 9141 0.90% 6.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 764 0.08% 6.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 943330 93.29% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1011151 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6075 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 2512.992263 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 47101.457482 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-65535 6047 99.54% 99.54% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.56% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.69% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::196608-262143 7 0.12% 99.80% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::393216-458751 1 0.02% 99.82% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::589824-655359 2 0.03% 99.85% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.87% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 7 0.12% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::983040-1.04858e+06 2 0.03% 99.88% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.10% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6071 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6071 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.578158 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.392553 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 2.387042 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1 4 0.07% 0.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2 4 0.07% 0.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::3 2 0.03% 0.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4 7 0.12% 0.28% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 6075 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6075 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.565103 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.376946 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 2.337614 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1 6 0.10% 0.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2 5 0.08% 0.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::3 2 0.03% 0.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4 4 0.07% 0.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::5 2 0.03% 0.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::6 2 0.03% 0.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::7 3 0.05% 0.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8 4 0.07% 0.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::9 6 0.10% 0.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::10 2 0.03% 0.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::11 3 0.05% 0.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::13 2 0.03% 0.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::7 2 0.03% 0.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8 4 0.07% 0.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::9 5 0.08% 0.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::10 2 0.03% 0.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::11 3 0.05% 0.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12 3 0.05% 0.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::13 1 0.02% 0.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::14 4 0.07% 0.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::15 12 0.20% 0.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 2739 45.12% 46.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 35 0.58% 46.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 1542 25.40% 72.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 1308 21.55% 93.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 93 1.53% 95.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 45 0.74% 95.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 49 0.81% 96.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 58 0.96% 97.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 25 0.41% 98.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 17 0.28% 98.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 20 0.33% 98.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 16 0.26% 98.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28 13 0.21% 99.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29 14 0.23% 99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30 14 0.23% 99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31 16 0.26% 99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32 10 0.16% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6071 # Writes before turning the bus around for reads
-system.physmem.totQLat 393355196000 # Total ticks spent queuing
-system.physmem.totMemAccLat 679593221000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 76330140000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 25766.70 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::15 11 0.18% 0.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 2721 44.79% 45.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 38 0.63% 46.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 1583 26.06% 72.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 1297 21.35% 93.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 91 1.50% 95.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 44 0.72% 95.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 54 0.89% 96.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 48 0.79% 97.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 29 0.48% 98.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 18 0.30% 98.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 20 0.33% 98.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27 17 0.28% 99.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28 13 0.21% 99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29 16 0.26% 99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30 12 0.20% 99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31 10 0.16% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32 8 0.13% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6075 # Writes before turning the bus around for reads
+system.physmem.totQLat 393209260500 # Total ticks spent queuing
+system.physmem.totMemAccLat 679455066750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 76332215000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 25756.44 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44516.70 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 383.06 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 44506.44 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 383.12 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.68 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 51.36 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 51.37 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 3.01 # Data bus utilization in percentage
system.physmem.busUtilRead 2.99 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 6.51 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 15.34 # Average write queue length when enqueuing
-system.physmem.readRowHits 14270645 # Number of row buffer hits during reads
-system.physmem.writeRowHits 91138 # Number of row buffer hits during writes
+system.physmem.avgRdQLen 6.37 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 14.37 # Average write queue length when enqueuing
+system.physmem.readRowHits 14270960 # Number of row buffer hits during reads
+system.physmem.writeRowHits 91040 # Number of row buffer hits during writes
system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 85.38 # Row buffer hit rate for writes
-system.physmem.avgGap 158357.40 # Average gap between requests
+system.physmem.writeRowHitRate 85.29 # Row buffer hit rate for writes
+system.physmem.avgGap 158334.21 # Average gap between requests
system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2202343950500 # Time in different power states
-system.physmem.memoryStateTime::REF 85170020000 # Time in different power states
+system.physmem.memoryStateTime::IDLE 2202305646000 # Time in different power states
+system.physmem.memoryStateTime::REF 85157800000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 263082705750 # Time in different power states
+system.physmem.memoryStateTime::ACT 262767276500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
@@ -327,283 +328,289 @@
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 54969203 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 16346092 # Transaction distribution
-system.membus.trans_dist::ReadResp 16346092 # Transaction distribution
+system.membus.throughput 54978267 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 16346128 # Transaction distribution
+system.membus.trans_dist::ReadResp 16346128 # Transaction distribution
system.membus.trans_dist::WriteReq 763361 # Transaction distribution
system.membus.trans_dist::WriteResp 763361 # Transaction distribution
-system.membus.trans_dist::Writeback 59148 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4680 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4680 # Transaction distribution
-system.membus.trans_dist::ReadExReq 131444 # Transaction distribution
-system.membus.trans_dist::ReadExResp 131444 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383060 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::Writeback 59160 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4685 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4687 # Transaction distribution
+system.membus.trans_dist::ReadExReq 131439 # Transaction distribution
+system.membus.trans_dist::ReadExResp 131439 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383052 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885816 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4272670 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885912 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 4272758 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 34550302 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390486 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total 34550390 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390470 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16695968 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total 19094102 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16698976 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total 19097094 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 140204630 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 140204630 # Total data (bytes)
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+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015261 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.251119 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000355 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009692 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.193285 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.091673 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 89364.285714 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58891.705069 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61505.752051 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70750 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60247.646673 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64344.497068 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 60973.392226 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.566614 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.688361 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61669.274080 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61089.105156 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 61412.836106 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84241.935484 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59068.588204 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61615.745339 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 63645.833333 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59405.033972 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61214.590057 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 61268.145063 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84241.935484 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59068.588204 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61615.745339 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 63645.833333 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59405.033972 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61214.590057 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 61268.145063 # average overall mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.737463 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.343879 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61530.156287 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59331.574060 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 60610.807088 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 89364.285714 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58891.705069 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61528.344756 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70750 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60247.646673 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59701.172833 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 60664.341591 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 89364.285714 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58891.705069 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61528.344756 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70750 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60247.646673 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59701.172833 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 60664.341591 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
@@ -778,46 +797,46 @@
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.toL2Bus.throughput 58427348 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 2677396 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2677395 # Transaction distribution
+system.toL2Bus.throughput 58447524 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 2676676 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2676675 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 763361 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 763361 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 607907 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 2938 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 2945 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 246147 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 246147 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1969203 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5796633 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 38454 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149595 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 7953885 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62977408 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85532246 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 56372 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 254604 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 148820630 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 148820630 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 204356 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 4962673723 # Layer occupancy (ticks)
+system.toL2Bus.trans_dist::Writeback 608464 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 2946 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 2964 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 246266 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 246266 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967872 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5798454 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37749 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149111 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 7953186 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62935104 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85607366 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55020 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 253376 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 148850866 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 148850866 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 204184 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 4964883974 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 4436346984 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 4433375902 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 4483051170 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 4485758372 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 24406904 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 24044394 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 86367392 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 86236537 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.throughput 48420315 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 16322169 # Transaction distribution
-system.iobus.trans_dist::ReadResp 16322169 # Transaction distribution
+system.iobus.throughput 48427259 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 16322165 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16322165 # Transaction distribution
system.iobus.trans_dist::WriteReq 8177 # Transaction distribution
system.iobus.trans_dist::WriteResp 8177 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7932 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
@@ -839,12 +858,12 @@
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2383060 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2383052 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 32660692 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 32660684 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15864 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
@@ -866,14 +885,14 @@
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 2390486 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 2390470 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 123501014 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 123501014 # Total data (bytes)
+system.iobus.tot_pkt_size::total 123500998 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 123500998 # Total data (bytes)
system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 3971000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
@@ -919,19 +938,19 @@
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2374883000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 2374875000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 38146923291 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 38148865049 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
-system.cpu0.branchPred.lookups 7527303 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 6005482 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 376664 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 4812068 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 3910560 # Number of BTB hits
+system.cpu0.branchPred.lookups 7661485 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 6126508 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 381527 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 4905065 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 3983490 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 81.265685 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 724420 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 38989 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 81.211768 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 723596 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 38982 # Number of incorrect RAS predictions.
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
@@ -955,25 +974,25 @@
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 25762472 # DTB read hits
-system.cpu0.dtb.read_misses 39475 # DTB read misses
-system.cpu0.dtb.write_hits 6143291 # DTB write hits
-system.cpu0.dtb.write_misses 10324 # DTB write misses
+system.cpu0.dtb.read_hits 25785436 # DTB read hits
+system.cpu0.dtb.read_misses 39736 # DTB read misses
+system.cpu0.dtb.write_hits 6191742 # DTB write hits
+system.cpu0.dtb.write_misses 10170 # DTB write misses
system.cpu0.dtb.flush_tlb 514 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 5580 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1376 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 262 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 5474 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1453 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 639 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 25801947 # DTB read accesses
-system.cpu0.dtb.write_accesses 6153615 # DTB write accesses
+system.cpu0.dtb.perms_faults 628 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 25825172 # DTB read accesses
+system.cpu0.dtb.write_accesses 6201912 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 31905763 # DTB hits
-system.cpu0.dtb.misses 49799 # DTB misses
-system.cpu0.dtb.accesses 31955562 # DTB accesses
+system.cpu0.dtb.hits 31977178 # DTB hits
+system.cpu0.dtb.misses 49906 # DTB misses
+system.cpu0.dtb.accesses 32027084 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
@@ -995,694 +1014,696 @@
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 5893431 # ITB inst hits
-system.cpu0.itb.inst_misses 7431 # ITB inst misses
+system.cpu0.itb.inst_hits 5958651 # ITB inst hits
+system.cpu0.itb.inst_misses 7224 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 514 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2617 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 2573 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1506 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1518 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 5900862 # ITB inst accesses
-system.cpu0.itb.hits 5893431 # DTB hits
-system.cpu0.itb.misses 7431 # DTB misses
-system.cpu0.itb.accesses 5900862 # DTB accesses
-system.cpu0.numCycles 242264674 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 5965875 # ITB inst accesses
+system.cpu0.itb.hits 5958651 # DTB hits
+system.cpu0.itb.misses 7224 # DTB misses
+system.cpu0.itb.accesses 5965875 # DTB accesses
+system.cpu0.numCycles 242096947 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 15531926 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 45587183 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 7527303 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 4634980 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 10285875 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 2434733 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 89107 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles 50171859 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 1648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles 2068 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles 54478 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 1474048 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 435 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 5891523 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 366856 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 3025 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 79291736 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.723314 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.072188 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 15548527 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 46430150 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 7661485 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 4707086 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 10443980 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 2504010 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 87505 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles 47991707 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 1669 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles 1947 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles 50069 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 1492171 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 279 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 5956718 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 371320 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 2975 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 77361996 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.753757 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.110815 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 69012854 87.04% 87.04% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 680232 0.86% 87.89% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 874808 1.10% 89.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 1172230 1.48% 90.48% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 1090891 1.38% 91.85% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 557599 0.70% 92.56% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 1295199 1.63% 94.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 379880 0.48% 94.67% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 4228043 5.33% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 66925381 86.51% 86.51% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 685980 0.89% 87.40% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 883677 1.14% 88.54% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 1195178 1.54% 90.08% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 1096516 1.42% 91.50% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 566437 0.73% 92.23% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 1314357 1.70% 93.93% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 386846 0.50% 94.43% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4307624 5.57% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 79291736 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.031071 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.188171 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 16635366 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 51194908 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 9213198 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 653944 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1592125 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 1010665 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 90813 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 54600074 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 300654 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1592125 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 17527482 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 20299787 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 27625200 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 8910460 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 3334547 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 52031373 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 331 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 485563 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 2176301 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents 182 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 53736698 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 241285167 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 220106334 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 4864 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 39390817 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 14345881 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 590593 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 539084 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 6947132 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 10055649 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 6962422 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1056834 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 1358453 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 48348288 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1003135 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 62086915 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 89013 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 9905639 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 24691410 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 254686 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 79291736 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.783019 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.501466 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 77361996 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.031646 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.191783 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 16313273 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 49370536 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 9491475 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 529288 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1655237 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 1021533 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 91523 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 55531280 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 303986 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1655237 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 17162522 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 7654348 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 28580121 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 9244360 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 13063308 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 52889125 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 1160 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 8605902 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 9933616 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 1829408 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents 705 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 54696180 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 245103090 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 223663577 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 5274 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 39761499 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 14934681 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 590339 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 538925 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 5812671 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 10214201 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 7053988 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1084092 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 1355038 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 49147671 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1004891 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 62507144 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 106564 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 10354652 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 26208427 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 256708 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 77361996 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.807983 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.536259 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 56790483 71.62% 71.62% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 7331291 9.25% 80.87% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 3517102 4.44% 85.30% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2900884 3.66% 88.96% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 6182474 7.80% 96.76% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1488398 1.88% 98.64% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 785922 0.99% 99.63% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 230106 0.29% 99.92% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 65076 0.08% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 55228815 71.39% 71.39% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 6921867 8.95% 80.34% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 3371546 4.36% 84.70% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2828196 3.66% 88.35% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 6343832 8.20% 96.55% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1429149 1.85% 98.40% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 903697 1.17% 99.57% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 264810 0.34% 99.91% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 70084 0.09% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 79291736 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 77361996 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 31039 0.70% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 1 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 4198728 94.33% 95.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 221343 4.97% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 34065 0.76% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 2 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 4230863 93.99% 94.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 236461 5.25% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 14970 0.02% 0.02% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 29137192 46.93% 46.95% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 47374 0.08% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 1226 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 26440432 42.59% 89.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 6445693 10.38% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 14977 0.02% 0.02% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 29471794 47.15% 47.17% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 48326 0.08% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 1252 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 26467836 42.34% 89.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 6502932 10.40% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 62086915 # Type of FU issued
-system.cpu0.iq.rate 0.256277 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 4451111 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.071692 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 208044448 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 59266351 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 43285904 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 10871 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 5830 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 4924 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 66517304 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 5752 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 316537 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 62507144 # Type of FU issued
+system.cpu0.iq.rate 0.258191 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 4501391 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.072014 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 207022163 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 60516960 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 43741315 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 11807 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 6284 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 5315 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 66987291 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 6267 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 331575 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 2144033 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 4052 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 15721 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 849604 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 2258680 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 3312 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 16640 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 890724 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 17082730 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 349385 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 17025951 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 348422 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1592125 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 15682380 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 239912 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 49471978 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 105539 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 10055649 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 6962422 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 704937 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 56286 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 4027 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 15721 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 184221 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 145235 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 329456 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 61023718 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 26110824 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 1063197 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1655237 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 6199849 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 752551 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 50264845 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 98291 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 10214201 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 7053988 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 705061 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 147463 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 536075 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 16640 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 186895 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 147787 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 334682 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 61435794 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 26133192 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 1071350 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 120555 # number of nop insts executed
-system.cpu0.iew.exec_refs 32498156 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 5982225 # Number of branches executed
-system.cpu0.iew.exec_stores 6387332 # Number of stores executed
-system.cpu0.iew.exec_rate 0.251889 # Inst execution rate
-system.cpu0.iew.wb_sent 60528797 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 43290828 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 23369621 # num instructions producing a value
-system.cpu0.iew.wb_consumers 42956226 # num instructions consuming a value
+system.cpu0.iew.exec_nop 112283 # number of nop insts executed
+system.cpu0.iew.exec_refs 32576038 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 6024055 # Number of branches executed
+system.cpu0.iew.exec_stores 6442846 # Number of stores executed
+system.cpu0.iew.exec_rate 0.253765 # Inst execution rate
+system.cpu0.iew.wb_sent 60932314 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 43746630 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 24175990 # num instructions producing a value
+system.cpu0.iew.wb_consumers 44857309 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.178692 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.544033 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.180699 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.538953 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 9786876 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 748449 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 287258 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 77699611 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.504830 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.472024 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 10244306 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 748183 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 291383 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 75706759 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.522606 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.501619 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 63277588 81.44% 81.44% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 7407512 9.53% 90.97% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 1967451 2.53% 93.50% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 1105852 1.42% 94.93% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 852897 1.10% 96.03% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 576328 0.74% 96.77% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 737114 0.95% 97.72% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 349768 0.45% 98.17% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1425101 1.83% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 61320530 81.00% 81.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 7333121 9.69% 90.68% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 1910409 2.52% 93.21% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 1174950 1.55% 94.76% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 814971 1.08% 95.84% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 569506 0.75% 96.59% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 771340 1.02% 97.61% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 344904 0.46% 98.06% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1467028 1.94% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 77699611 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 30084753 # Number of instructions committed
-system.cpu0.commit.committedOps 39225066 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 75706759 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 30422123 # Number of instructions committed
+system.cpu0.commit.committedOps 39564795 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 14024434 # Number of memory references committed
-system.cpu0.commit.loads 7911616 # Number of loads committed
-system.cpu0.commit.membars 209739 # Number of memory barriers committed
-system.cpu0.commit.branches 5192960 # Number of branches committed
-system.cpu0.commit.fp_insts 4874 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 34907078 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 509367 # Number of function calls committed.
+system.cpu0.commit.refs 14118785 # Number of memory references committed
+system.cpu0.commit.loads 7955521 # Number of loads committed
+system.cpu0.commit.membars 210845 # Number of memory barriers committed
+system.cpu0.commit.branches 5215430 # Number of branches committed
+system.cpu0.commit.fp_insts 5270 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 35234514 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 505825 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 25154804 64.13% 64.13% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 44602 0.11% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 1226 0.00% 64.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 7911616 20.17% 84.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 6112818 15.58% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 25399613 64.20% 64.20% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult 45146 0.11% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.31% # Class of committed instruction
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-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087219 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.082999 # mshr miss rate for demand accesses
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-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.082999 # mshr miss rate for overall accesses
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-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11865.395630 # average overall mshr miss latency
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-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12113.798603 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11865.395630 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11994.970857 # average overall mshr miss latency
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system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
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system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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-system.cpu0.dcache.tags.total_refs 21526419 # Total number of references to valid blocks.
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-system.cpu0.dcache.tags.avg_refs 33.429439 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 43468250 # Cycle when the warmup percentage was hit.
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-system.cpu0.dcache.tags.occ_blocks::cpu1.data 257.173192 # Average occupied blocks per requestor
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+system.cpu0.dcache.tags.warmup_cycle 42479250 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 190 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
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system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 82392993 # number of LoadLockedReq miss cycles
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-system.cpu0.dcache.overall_miss_latency::total 160025112228 # number of overall miss cycles
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-system.cpu0.dcache.ReadReq_accesses::cpu1.data 7140342 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 14520118 # number of ReadReq accesses(hits+misses)
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-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 132401 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 256654 # number of LoadLockedReq accesses(hits+misses)
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-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 128133 # number of StoreCondReq accesses(hits+misses)
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-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14564.877994 # average ReadReq miss latency
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-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 47922.572947 # average WriteReq miss latency
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-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13440.945024 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13860.574333 # average LoadLockedReq miss latency
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-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency
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+system.cpu0.dcache.overall_mshr_misses::cpu1.data 307032 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 635314 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2672225710 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2597817092 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5270042802 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6526900100 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4738022235 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11264922335 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 84662502 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63153752 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147816254 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 111499 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 111499 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 222998 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9199125810 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7335839327 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 16534965137 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9199125810 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7335839327 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 16534965137 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91653477500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90683023500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336501000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13720132000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13077337591 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26797469591 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105373609500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103760361091 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209133970591 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025718 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027438 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026558 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025278 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023337 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024365 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053418 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.041675 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047412 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000075 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000071 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000073 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025532 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025783 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.025653 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025532 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025783 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.025653 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13961.180069 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13334.379210 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13645.006931 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47684.069756 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42224.222536 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45224.487372 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12623.006113 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11528.614823 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12131.001559 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12388.777778 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 12388.777778 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12388.777778 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28022.023169 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23892.751658 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26026.445407 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28022.023169 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23892.751658 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26026.445407 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
@@ -1693,15 +1714,15 @@
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 7300035 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 5887077 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 345091 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 4651296 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 3771120 # Number of BTB hits
+system.cpu1.branchPred.lookups 7344792 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 5924572 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 342317 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 4758265 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 3794052 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 81.076758 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 673548 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 34495 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 79.736038 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 685317 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 35371 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
@@ -1725,25 +1746,25 @@
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 25450161 # DTB read hits
-system.cpu1.dtb.read_misses 36388 # DTB read misses
-system.cpu1.dtb.write_hits 5568332 # DTB write hits
-system.cpu1.dtb.write_misses 8538 # DTB write misses
+system.cpu1.dtb.read_hits 25350014 # DTB read hits
+system.cpu1.dtb.read_misses 36246 # DTB read misses
+system.cpu1.dtb.write_hits 5533315 # DTB write hits
+system.cpu1.dtb.write_misses 8540 # DTB write misses
system.cpu1.dtb.flush_tlb 510 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 5495 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 2244 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 247 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 5471 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 1908 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 249 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 710 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 25486549 # DTB read accesses
-system.cpu1.dtb.write_accesses 5576870 # DTB write accesses
+system.cpu1.dtb.read_accesses 25386260 # DTB read accesses
+system.cpu1.dtb.write_accesses 5541855 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 31018493 # DTB hits
-system.cpu1.dtb.misses 44926 # DTB misses
-system.cpu1.dtb.accesses 31063419 # DTB accesses
+system.cpu1.dtb.hits 30883329 # DTB hits
+system.cpu1.dtb.misses 44786 # DTB misses
+system.cpu1.dtb.accesses 30928115 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
@@ -1765,125 +1786,126 @@
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 5679651 # ITB inst hits
-system.cpu1.itb.inst_misses 6870 # ITB inst misses
+system.cpu1.itb.inst_hits 5683844 # ITB inst hits
+system.cpu1.itb.inst_misses 6848 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 510 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 2692 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 2653 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1570 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1514 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 5686521 # ITB inst accesses
-system.cpu1.itb.hits 5679651 # DTB hits
-system.cpu1.itb.misses 6870 # DTB misses
-system.cpu1.itb.accesses 5686521 # DTB accesses
-system.cpu1.numCycles 236844574 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 5690692 # ITB inst accesses
+system.cpu1.itb.hits 5683844 # DTB hits
+system.cpu1.itb.misses 6848 # DTB misses
+system.cpu1.itb.accesses 5690692 # DTB accesses
+system.cpu1.numCycles 235812118 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 14466322 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 45074741 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 7300035 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 4444668 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 9928510 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 2284755 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 83810 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles 49428019 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 1085 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles 1865 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles 44064 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 1232877 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 132 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 5677454 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 353029 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 3058 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 76760101 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.724873 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.076516 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 14488159 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 45028124 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 7344792 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 4479369 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 9950354 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 2325910 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 82893 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles 46948697 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 1099 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles 1893 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles 45519 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 1268155 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 161 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 5681743 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 353393 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 2950 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 74402978 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.748631 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.104884 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 66839787 87.08% 87.08% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 628644 0.82% 87.90% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 837705 1.09% 88.99% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 1128430 1.47% 90.46% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1025116 1.34% 91.79% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 549692 0.72% 92.51% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1265677 1.65% 94.16% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 371391 0.48% 94.64% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 4113659 5.36% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 64461074 86.64% 86.64% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 633258 0.85% 87.49% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 845202 1.14% 88.62% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 1118143 1.50% 90.13% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1030578 1.39% 91.51% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 551741 0.74% 92.25% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1296054 1.74% 94.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 370486 0.50% 94.49% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 4096442 5.51% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 76760101 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.030822 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.190314 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 15575790 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 50164874 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 8875530 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 651724 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 1490012 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 958602 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 85804 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 53028773 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 286820 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 1490012 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 16419373 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 19259514 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 27698423 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 8639214 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 3251470 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 50560580 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 221 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 607469 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 2007282 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents 572 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 52946210 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 233908561 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 213841042 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 5698 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 39345682 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 13600527 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 580708 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 537933 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 6505084 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 9729570 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 6369599 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 877361 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1114434 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 47034811 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 984793 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 60942495 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 91566 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 9279731 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 23349761 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 250555 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 76760101 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.793935 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.504235 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 74402978 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.031147 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.190949 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 15290128 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 48029788 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 9010807 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 535995 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 1534066 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 962796 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 84486 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 53087117 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 281620 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 1534066 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 16089413 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 6996685 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 28422508 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 8819964 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 12538212 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 50579819 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 715 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 8590875 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 9852379 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 1395671 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents 1301 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 52976488 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 233969396 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 213834273 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 5207 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 38971918 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 14004569 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 583497 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 540607 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 5363476 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 9768473 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 6353478 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 903299 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 1144541 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 47001226 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 985413 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 60595640 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 98989 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 9593116 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 24473464 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 250944 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 74402978 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.814425 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.533021 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 54532875 71.04% 71.04% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 7326090 9.54% 80.59% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 3469207 4.52% 85.11% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 2884980 3.76% 88.87% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 6118042 7.97% 96.84% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1370862 1.79% 98.62% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 772587 1.01% 99.63% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 222613 0.29% 99.92% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 62845 0.08% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 52794785 70.96% 70.96% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 6823804 9.17% 80.13% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 3272663 4.40% 84.53% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 2786608 3.75% 88.27% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 6272134 8.43% 96.70% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1319081 1.77% 98.48% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 820611 1.10% 99.58% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 247257 0.33% 99.91% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 66035 0.09% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 76760101 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 74402978 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 29035 0.66% 0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 5 0.00% 0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 29526 0.66% 0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 4 0.00% 0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.66% # attempts to use FU when none available
@@ -1911,182 +1933,182 @@
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 4177111 94.84% 95.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 198082 4.50% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 4196905 94.38% 95.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 220217 4.95% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 13548 0.02% 0.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 28887832 47.40% 47.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 46127 0.08% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 14 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 887 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 26105748 42.84% 90.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 5888317 9.66% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 13541 0.02% 0.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 28679065 47.33% 47.35% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 45344 0.07% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 858 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 26009717 42.92% 90.35% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 5847084 9.65% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 60942495 # Type of FU issued
-system.cpu1.iq.rate 0.257310 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 4404233 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.072269 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 203173539 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 57307144 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 42269826 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 12116 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 6726 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 5381 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 65326800 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 6380 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 306796 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 60595640 # Type of FU issued
+system.cpu1.iq.rate 0.256966 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 4446652 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.073382 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 200172970 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 57588554 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 41991709 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 11520 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 6240 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 4992 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 65022566 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 6185 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 323560 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 1984154 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 3003 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 15089 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 749009 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2067890 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 2468 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 15600 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 783792 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 17027364 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 331342 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 16950409 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 331839 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 1490012 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 14823463 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 222107 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 48121220 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 96425 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 9729570 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 6369599 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 709638 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 48371 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 4239 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 15089 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 167591 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 133565 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 301156 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 59912848 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 25789830 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 1029647 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 1534066 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 5578937 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 735039 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 48101549 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 89840 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 9768473 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 6353478 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 710230 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 138266 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 531900 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 15600 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 167974 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 132221 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 300195 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 59563474 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 25690610 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1032166 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 101616 # number of nop insts executed
-system.cpu1.iew.exec_refs 31626536 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 5854246 # Number of branches executed
-system.cpu1.iew.exec_stores 5836706 # Number of stores executed
-system.cpu1.iew.exec_rate 0.252963 # Inst execution rate
-system.cpu1.iew.wb_sent 59450905 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 42275207 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 23556720 # num instructions producing a value
-system.cpu1.iew.wb_consumers 42880647 # num instructions consuming a value
+system.cpu1.iew.exec_nop 114910 # number of nop insts executed
+system.cpu1.iew.exec_refs 31485549 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 5840798 # Number of branches executed
+system.cpu1.iew.exec_stores 5794939 # Number of stores executed
+system.cpu1.iew.exec_rate 0.252589 # Inst execution rate
+system.cpu1.iew.wb_sent 59096440 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 41996701 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 23719594 # num instructions producing a value
+system.cpu1.iew.wb_consumers 43668575 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.178493 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.549356 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.178094 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.543173 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 9147109 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 734238 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 260548 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 75270089 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.511960 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.483838 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 9469311 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 734469 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 259123 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 72868911 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.524128 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.502288 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 60996835 81.04% 81.04% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 7463530 9.92% 90.95% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 1923766 2.56% 93.51% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1066165 1.42% 94.93% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 822611 1.09% 96.02% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 493470 0.66% 96.67% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 696092 0.92% 97.60% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 369554 0.49% 98.09% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1438066 1.91% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 58802570 80.70% 80.70% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 7335717 10.07% 90.76% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 1834357 2.52% 93.28% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1110131 1.52% 94.80% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 806352 1.11% 95.91% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 478738 0.66% 96.57% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 708592 0.97% 97.54% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 352493 0.48% 98.02% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1439961 1.98% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 75270089 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 30381625 # Number of instructions committed
-system.cpu1.commit.committedOps 38535309 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 72868911 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 30042313 # Number of instructions committed
+system.cpu1.commit.committedOps 38192613 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 13366006 # Number of memory references committed
-system.cpu1.commit.loads 7745416 # Number of loads committed
-system.cpu1.commit.membars 193947 # Number of memory barriers committed
-system.cpu1.commit.branches 5114433 # Number of branches committed
-system.cpu1.commit.fp_insts 5338 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 34292499 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 482077 # Number of function calls committed.
+system.cpu1.commit.refs 13270269 # Number of memory references committed
+system.cpu1.commit.loads 7700583 # Number of loads committed
+system.cpu1.commit.membars 192827 # Number of memory barriers committed
+system.cpu1.commit.branches 5091642 # Number of branches committed
+system.cpu1.commit.fp_insts 4942 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 33962282 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 485556 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 25125071 65.20% 65.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 43345 0.11% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 887 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 7745416 20.10% 85.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 5620590 14.59% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 24878693 65.14% 65.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 42793 0.11% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc 858 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead 7700583 20.16% 85.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite 5569686 14.58% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 38535309 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 1438066 # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total 38192613 # Class of committed instruction
+system.cpu1.commit.bw_lim_events 1439961 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 120626402 # The number of ROB reads
-system.cpu1.rob.rob_writes 96898257 # The number of ROB writes
-system.cpu1.timesIdled 866184 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 160084473 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 2317121408 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 30313431 # Number of Instructions Simulated
-system.cpu1.committedOps 38467115 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 7.813189 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 7.813189 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.127989 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.127989 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 271901021 # number of integer regfile reads
-system.cpu1.int_regfile_writes 43646883 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 45279 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 42402 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 133121444 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 593543 # number of misc regfile writes
+system.cpu1.rob.rob_reads 118199712 # The number of ROB reads
+system.cpu1.rob.rob_writes 96901530 # The number of ROB writes
+system.cpu1.timesIdled 866503 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 161409140 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 2317329341 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 29966199 # Number of Instructions Simulated
+system.cpu1.committedOps 38116499 # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi 7.869270 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 7.869270 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.127077 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.127077 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 270334360 # number of integer regfile reads
+system.cpu1.int_regfile_writes 43344614 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 45048 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 42280 # number of floating regfile writes
+system.cpu1.misc_regfile_reads 130449609 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 594503 # number of misc regfile writes
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
@@ -2103,17 +2125,17 @@
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734475259291 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1734475259291 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734475259291 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1734475259291 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734330533049 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1734330533049 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734330533049 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1734330533049 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 83062 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 83063 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
