regressions: stats update due to decoder changes
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
index 219ef17..e4ef930 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
@@ -10,7 +10,7 @@
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
atags_addr=256
-boot_loader=/projects/pd/randd/dist/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
@@ -19,7 +19,7 @@
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
@@ -65,7 +65,7 @@
[system.cf0.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
index a24f5a9..1c087a7 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
@@ -4,11 +4,11 @@
sim_ticks 2523500318000 # Number of ticks simulated
final_tick 2523500318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 54734 # Simulator instruction rate (inst/s)
-host_op_rate 70403 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2279341302 # Simulator tick rate (ticks/s)
-host_mem_usage 401036 # Number of bytes of host memory used
-host_seconds 1107.12 # Real time elapsed on the host
+host_inst_rate 64209 # Simulator instruction rate (inst/s)
+host_op_rate 82591 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2673913922 # Simulator tick rate (ticks/s)
+host_mem_usage 441476 # Number of bytes of host memory used
+host_seconds 943.75 # Real time elapsed on the host
sim_insts 60596849 # Number of instructions simulated
sim_ops 77944928 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
@@ -584,7 +584,7 @@
system.cpu.int_regfile_writes 87979072 # number of integer regfile writes
system.cpu.fp_regfile_reads 8318 # number of floating regfile reads
system.cpu.fp_regfile_writes 2932 # number of floating regfile writes
-system.cpu.misc_regfile_reads 122823412 # number of misc regfile reads
+system.cpu.misc_regfile_reads 30426999 # number of misc regfile reads
system.cpu.misc_regfile_writes 912865 # number of misc regfile writes
system.cpu.icache.replacements 980837 # number of replacements
system.cpu.icache.tagsinuse 511.007226 # Cycle average of tags in use
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
index e8e271d..523f8a1 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
@@ -12,6 +12,8 @@
warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: LCD dual screen mode not supported
+warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
+warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index 2681ab2..3f5cdc3 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -4,11 +4,11 @@
sim_ticks 2593146078000 # Number of ticks simulated
final_tick 2593146078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 66425 # Simulator instruction rate (inst/s)
-host_op_rate 85503 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2731005239 # Simulator tick rate (ticks/s)
-host_mem_usage 409388 # Number of bytes of host memory used
-host_seconds 949.52 # Real time elapsed on the host
+host_inst_rate 77303 # Simulator instruction rate (inst/s)
+host_op_rate 99505 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3178225665 # Simulator tick rate (ticks/s)
+host_mem_usage 449664 # Number of bytes of host memory used
+host_seconds 815.91 # Real time elapsed on the host
sim_insts 63072130 # Number of instructions simulated
sim_ops 81187111 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
@@ -1007,7 +1007,7 @@
system.cpu0.int_regfile_writes 34853003 # number of integer regfile writes
system.cpu0.fp_regfile_reads 3246 # number of floating regfile reads
system.cpu0.fp_regfile_writes 906 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 46878729 # number of misc regfile reads
+system.cpu0.misc_regfile_reads 13342715 # number of misc regfile reads
system.cpu0.misc_regfile_writes 527371 # number of misc regfile writes
system.cpu0.icache.replacements 399233 # number of replacements
system.cpu0.icache.tagsinuse 511.592262 # Cycle average of tags in use
@@ -1577,7 +1577,7 @@
system.cpu1.int_regfile_writes 56596470 # number of integer regfile writes
system.cpu1.fp_regfile_reads 4905 # number of floating regfile reads
system.cpu1.fp_regfile_writes 2328 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 81326805 # number of misc regfile reads
+system.cpu1.misc_regfile_reads 18962770 # number of misc regfile reads
system.cpu1.misc_regfile_writes 430176 # number of misc regfile writes
system.cpu1.icache.replacements 614989 # number of replacements
system.cpu1.icache.tagsinuse 498.619037 # Cycle average of tags in use
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
index fbd26bc..842d69c 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
@@ -10,7 +10,7 @@
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
atags_addr=256
-boot_loader=/projects/pd/randd/dist/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
@@ -19,11 +19,12 @@
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
memories=system.physmem system.realview.nvmem
+midr_regval=890224640
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
@@ -64,12 +65,12 @@
[system.cf0.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -117,7 +118,6 @@
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
-isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@@ -497,23 +497,6 @@
[system.cpu.interrupts]
type=ArmInterrupts
-[system.cpu.isa]
-type=ArmISA
-fpsid=1090793632
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=3
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=4027589137
-id_pfr0=49
-id_pfr1=1
-midr=890224640
-
[system.cpu.itb]
type=ArmTLB
children=walker
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
index 3ee89fc..affb69a 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
@@ -11,6 +11,8 @@
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: LCD dual screen mode not supported
+warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
+warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index 6a79df0..0468c16 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -4,11 +4,11 @@
sim_ticks 2523500318000 # Number of ticks simulated
final_tick 2523500318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 66325 # Simulator instruction rate (inst/s)
-host_op_rate 85314 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2762063576 # Simulator tick rate (ticks/s)
-host_mem_usage 400896 # Number of bytes of host memory used
-host_seconds 913.63 # Real time elapsed on the host
+host_inst_rate 76318 # Simulator instruction rate (inst/s)
+host_op_rate 98167 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3178196363 # Simulator tick rate (ticks/s)
+host_mem_usage 441472 # Number of bytes of host memory used
+host_seconds 794.00 # Real time elapsed on the host
sim_insts 60596849 # Number of instructions simulated
sim_ops 77944928 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
@@ -539,7 +539,7 @@
system.cpu.int_regfile_writes 87979071 # number of integer regfile writes
system.cpu.fp_regfile_reads 8318 # number of floating regfile reads
system.cpu.fp_regfile_writes 2932 # number of floating regfile writes
-system.cpu.misc_regfile_reads 122823412 # number of misc regfile reads
+system.cpu.misc_regfile_reads 30426999 # number of misc regfile reads
system.cpu.misc_regfile_writes 912865 # number of misc regfile writes
system.cpu.icache.replacements 980837 # number of replacements
system.cpu.icache.tagsinuse 511.007226 # Cycle average of tags in use
@@ -633,6 +633,168 @@
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 643459 # number of replacements
+system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use
+system.cpu.dcache.total_refs 21664123 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 643971 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 33.641457 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 13804735 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 13804735 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 7290056 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 7290056 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 280491 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 280491 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 285728 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 285728 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 21094791 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 21094791 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 21094791 # number of overall hits
+system.cpu.dcache.overall_hits::total 21094791 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 731455 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 731455 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2960577 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2960577 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 13626 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 13626 # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data 3692032 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3692032 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3692032 # number of overall misses
+system.cpu.dcache.overall_misses::total 3692032 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 9566755000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 9566755000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 105515855226 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 105515855226 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181290500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 181290500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total 192000 # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 115082610226 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 115082610226 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 115082610226 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 115082610226 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 14536190 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 14536190 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 10250633 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10250633 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 294117 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 294117 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 285740 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 285740 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 24786823 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 24786823 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 24786823 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 24786823 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050320 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.050320 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288819 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.288819 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046329 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046329 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000042 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000042 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.148951 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.148951 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.148951 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.148951 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13079.075268 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13079.075268 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35640.300937 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 35640.300937 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13304.748275 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13304.748275 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31170.534336 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31170.534336 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 30622 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 13737 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 255 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.827733 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 53.870588 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 607749 # number of writebacks
+system.cpu.dcache.writebacks::total 607749 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345667 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 345667 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711644 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2711644 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1415 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1415 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3057311 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3057311 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3057311 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3057311 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385788 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 385788 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248933 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 248933 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 634721 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 634721 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 634721 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 634721 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768255000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768255000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8227495919 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8227495919 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141520500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141520500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12995750919 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 12995750919 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12995750919 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 12995750919 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182357111500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182357111500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 27981839814 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 27981839814 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210338951314 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 210338951314 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026540 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026540 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024285 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024285 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041517 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041517 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000042 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000042 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025607 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.025607 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12359.780501 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12359.780501 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33051.045538 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33051.045538 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11589.591352 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11589.591352 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 64388 # number of replacements
system.cpu.l2cache.tagsinuse 51373.602635 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1911501 # Total number of references to valid blocks.
@@ -896,168 +1058,6 @@
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 643459 # number of replacements
-system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use
-system.cpu.dcache.total_refs 21664123 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 643971 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 33.641457 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 13804735 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 13804735 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 7290056 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 7290056 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 280491 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 280491 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 285728 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 285728 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 21094791 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 21094791 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 21094791 # number of overall hits
-system.cpu.dcache.overall_hits::total 21094791 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 731455 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 731455 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 2960577 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2960577 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 13626 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 13626 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 3692032 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3692032 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3692032 # number of overall misses
-system.cpu.dcache.overall_misses::total 3692032 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 9566755000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 9566755000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 105515855226 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 105515855226 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181290500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 181290500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 192000 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 115082610226 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 115082610226 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 115082610226 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 115082610226 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 14536190 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 14536190 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 10250633 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 10250633 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 294117 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 294117 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 285740 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 285740 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 24786823 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 24786823 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 24786823 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 24786823 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050320 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.050320 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288819 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.288819 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046329 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046329 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000042 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000042 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.148951 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.148951 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.148951 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.148951 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13079.075268 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13079.075268 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35640.300937 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 35640.300937 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13304.748275 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13304.748275 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31170.534336 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31170.534336 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 30622 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 13737 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 255 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.827733 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 53.870588 # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 607749 # number of writebacks
-system.cpu.dcache.writebacks::total 607749 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345667 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 345667 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711644 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2711644 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1415 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1415 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3057311 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3057311 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3057311 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3057311 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385788 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 385788 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248933 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 248933 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 634721 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 634721 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 634721 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 634721 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768255000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768255000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8227495919 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8227495919 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141520500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141520500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12995750919 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 12995750919 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12995750919 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 12995750919 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182357111500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182357111500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 27981839814 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 27981839814 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210338951314 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 210338951314 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026540 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026540 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024285 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024285 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041517 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041517 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000042 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000042 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.025607 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.025607 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12359.780501 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12359.780501 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33051.045538 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33051.045538 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11589.591352 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11589.591352 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
index d2efc88..8b98b78 100644
--- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@
sim_ticks 164568389500 # Number of ticks simulated
final_tick 164568389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 155967 # Simulator instruction rate (inst/s)
-host_op_rate 164807 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 45026221 # Simulator tick rate (ticks/s)
-host_mem_usage 230908 # Number of bytes of host memory used
-host_seconds 3654.95 # Real time elapsed on the host
+host_inst_rate 195675 # Simulator instruction rate (inst/s)
+host_op_rate 206765 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 56489453 # Simulator tick rate (ticks/s)
+host_mem_usage 277972 # Number of bytes of host memory used
+host_seconds 2913.26 # Real time elapsed on the host
sim_insts 570052720 # Number of instructions simulated
sim_ops 602360926 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 47104 # Number of bytes read from this memory
@@ -502,7 +502,7 @@
system.cpu.int_regfile_reads 3204362065 # number of integer regfile reads
system.cpu.int_regfile_writes 663044095 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 901644614 # number of misc regfile reads
+system.cpu.misc_regfile_reads 234776328 # number of misc regfile reads
system.cpu.misc_regfile_writes 3110 # number of misc regfile writes
system.cpu.icache.replacements 60 # number of replacements
system.cpu.icache.tagsinuse 685.359263 # Cycle average of tags in use
@@ -588,6 +588,132 @@
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47143.901220 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 47143.901220 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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@@ -735,131 +861,5 @@
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-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
index 31bcf27..f5f3830 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -30,7 +30,7 @@
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -78,7 +78,6 @@
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
-isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@@ -458,23 +457,6 @@
[system.cpu.interrupts]
type=ArmInterrupts
-[system.cpu.isa]
-type=ArmISA
-fpsid=1090793632
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=3
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=4027589137
-id_pfr0=49
-id_pfr1=1
-midr=890224640
-
[system.cpu.itb]
type=ArmTLB
children=walker
@@ -536,9 +518,9 @@
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index c26c8db..fae2b58 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@
sim_ticks 26786364500 # Number of ticks simulated
final_tick 26786364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 151377 # Simulator instruction rate (inst/s)
-host_op_rate 152464 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 44755705 # Simulator tick rate (ticks/s)
-host_mem_usage 363280 # Number of bytes of host memory used
-host_seconds 598.50 # Real time elapsed on the host
+host_inst_rate 184396 # Simulator instruction rate (inst/s)
+host_op_rate 185720 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 54518089 # Simulator tick rate (ticks/s)
+host_mem_usage 410024 # Number of bytes of host memory used
+host_seconds 491.33 # Real time elapsed on the host
sim_insts 90599358 # Number of instructions simulated
sim_ops 91249911 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory
@@ -496,7 +496,7 @@
system.cpu.int_regfile_writes 120555497 # number of integer regfile writes
system.cpu.fp_regfile_reads 176 # number of floating regfile reads
system.cpu.fp_regfile_writes 427 # number of floating regfile writes
-system.cpu.misc_regfile_reads 181219036 # number of misc regfile reads
+system.cpu.misc_regfile_reads 29099412 # number of misc regfile reads
system.cpu.misc_regfile_writes 11608 # number of misc regfile writes
system.cpu.icache.replacements 4 # number of replacements
system.cpu.icache.tagsinuse 632.599736 # Cycle average of tags in use
@@ -582,6 +582,132 @@
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49748.307172 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 49748.307172 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 943495 # number of replacements
+system.cpu.dcache.tagsinuse 3673.924289 # Cycle average of tags in use
+system.cpu.dcache.total_refs 28145440 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 947591 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 29.702097 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 7941416000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 3673.924289 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.896954 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.896954 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 23596473 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 23596473 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 4537302 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 4537302 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 28133775 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 28133775 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 28133775 # number of overall hits
+system.cpu.dcache.overall_hits::total 28133775 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1173127 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1173127 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 197679 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 197679 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 1370806 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1370806 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1370806 # number of overall misses
+system.cpu.dcache.overall_misses::total 1370806 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880183500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 13880183500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 5370097404 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 5370097404 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 19250280904 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 19250280904 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 19250280904 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 19250280904 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 24769600 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 24769600 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 29504581 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 29504581 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 29504581 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 29504581 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047362 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.047362 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041749 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.041749 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.046461 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.046461 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.046461 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.046461 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782492 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782492 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14043.038113 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14043.038113 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 152379 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 23821 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.396835 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks
+system.cpu.dcache.writebacks::total 942892 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269039 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 269039 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154172 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 154172 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 423211 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 423211 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 423211 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 423211 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904088 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 904088 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43507 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 43507 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 947595 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 947595 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 947595 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 947595 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9989577500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 9989577500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 957542952 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 957542952 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947120452 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10947120452 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947120452 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10947120452 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036500 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036500 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009188 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009188 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.341989 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.341989 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 10757.788342 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1831577 # Total number of references to valid blocks.
@@ -743,131 +869,5 @@
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29151.213847 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29551.495939 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 943495 # number of replacements
-system.cpu.dcache.tagsinuse 3673.924289 # Cycle average of tags in use
-system.cpu.dcache.total_refs 28145440 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 947591 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 29.702097 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 7941416000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 3673.924289 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.896954 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.896954 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 23596473 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 23596473 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 4537302 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 4537302 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 28133775 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 28133775 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 28133775 # number of overall hits
-system.cpu.dcache.overall_hits::total 28133775 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1173127 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1173127 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 197679 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 197679 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 1370806 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1370806 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1370806 # number of overall misses
-system.cpu.dcache.overall_misses::total 1370806 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880183500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 13880183500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 5370097404 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 5370097404 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 19250280904 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 19250280904 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 19250280904 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 19250280904 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 24769600 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 24769600 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 29504581 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 29504581 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 29504581 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 29504581 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047362 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.047362 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041749 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.041749 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.046461 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.046461 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.046461 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.046461 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782492 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782492 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14043.038113 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14043.038113 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 152379 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 23821 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.396835 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks
-system.cpu.dcache.writebacks::total 942892 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269039 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 269039 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154172 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 154172 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 423211 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 423211 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 423211 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 423211 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904088 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 904088 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43507 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 43507 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 947595 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 947595 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 947595 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 947595 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9989577500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 9989577500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 957542952 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 957542952 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947120452 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10947120452 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947120452 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10947120452 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036500 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036500 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009188 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009188 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.341989 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.341989 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index 7f80803..114baeb 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -1,90 +1,90 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.206020 # Number of seconds simulated
-sim_ticks 206019870500 # Number of ticks simulated
-final_tick 206019870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.206025 # Number of seconds simulated
+sim_ticks 206024606500 # Number of ticks simulated
+final_tick 206024606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 121571 # Simulator instruction rate (inst/s)
-host_op_rate 136951 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 49210675 # Simulator tick rate (ticks/s)
-host_mem_usage 259828 # Number of bytes of host memory used
-host_seconds 4186.49 # Real time elapsed on the host
-sim_insts 508955243 # Number of instructions simulated
-sim_ops 573341803 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 217536 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9265600 # Number of bytes read from this memory
-system.physmem.bytes_read::total 9483136 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 217536 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 217536 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6247936 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6247936 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3399 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 144775 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 148174 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 97624 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 97624 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1055898 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 44974303 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 46030201 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1055898 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1055898 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 30326861 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 30326861 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 30326861 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1055898 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 44974303 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 76357062 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 148175 # Total number of read requests seen
-system.physmem.writeReqs 97624 # Total number of write requests seen
-system.physmem.cpureqs 245816 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 9483136 # Total number of bytes read from memory
-system.physmem.bytesWritten 6247936 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 9483136 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6247936 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 95 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 17 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 9231 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 9188 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 9343 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 8790 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 9223 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 8971 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 9240 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 9470 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 9143 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 10294 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 9679 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 9702 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 9116 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 8946 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 9014 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 8730 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 5976 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 6116 # Track writes on a per bank basis
+host_inst_rate 152686 # Simulator instruction rate (inst/s)
+host_op_rate 172002 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 61807337 # Simulator tick rate (ticks/s)
+host_mem_usage 303988 # Number of bytes of host memory used
+host_seconds 3333.34 # Real time elapsed on the host
+sim_insts 508955238 # Number of instructions simulated
+sim_ops 573341798 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 217280 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9266560 # Number of bytes read from this memory
+system.physmem.bytes_read::total 9483840 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 217280 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 217280 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6249216 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6249216 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 3395 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 144790 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 148185 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 97644 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 97644 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1054631 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 44977928 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 46032560 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1054631 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1054631 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 30332377 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 30332377 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 30332377 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1054631 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 44977928 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 76364937 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 148186 # Total number of read requests seen
+system.physmem.writeReqs 97644 # Total number of write requests seen
+system.physmem.cpureqs 245841 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 9483840 # Total number of bytes read from memory
+system.physmem.bytesWritten 6249216 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 9483840 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6249216 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 83 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 11 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 9219 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 9199 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 9344 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 8811 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 9228 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 8973 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 9239 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 9440 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 9127 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 10272 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 9693 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 9714 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 9129 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 8954 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 9005 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 8756 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 5972 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 6125 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 6116 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 5942 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 6120 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 5953 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 6022 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 6372 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 5971 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 6671 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 6280 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 6315 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 6042 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 6059 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 5905 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 5764 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 5945 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 6129 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 5951 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 6023 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 6373 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 5964 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 6647 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 6290 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 6322 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 6045 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 6065 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 5899 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 5778 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 206019849500 # Total gap between requests
+system.physmem.totGap 206024585500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 148175 # Categorize read packet sizes
+system.physmem.readPktSize::6 148186 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -93,7 +93,7 @@
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 97624 # categorize write packet sizes
+system.physmem.writePktSize::6 97644 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
@@ -102,15 +102,15 @@
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 17 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 11 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 138261 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 9196 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 546 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 138148 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 9303 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 576 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
@@ -138,31 +138,31 @@
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 4239 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 4242 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 4240 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 4246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 4246 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 4245 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 4245 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 4244 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 4244 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 4244 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 4244 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 4244 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 4244 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 4244 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 4244 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 4244 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 4244 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 4244 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 4245 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
@@ -171,14 +171,14 @@
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 1627412180 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 4699930180 # Sum of mem lat for all requests
-system.physmem.totBusLat 592320000 # Total cycles spent in databus access
-system.physmem.totBankLat 2480198000 # Total cycles spent in bank access
-system.physmem.avgQLat 10990.09 # Average queueing delay per request
-system.physmem.avgBankLat 16749.04 # Average bank access latency per request
+system.physmem.totQLat 1634901672 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 4710633672 # Sum of mem lat for all requests
+system.physmem.totBusLat 592412000 # Total cycles spent in databus access
+system.physmem.totBankLat 2483320000 # Total cycles spent in bank access
+system.physmem.avgQLat 11038.95 # Average queueing delay per request
+system.physmem.avgBankLat 16767.52 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 31739.13 # Average memory access latency
+system.physmem.avgMemAccLat 31806.47 # Average memory access latency
system.physmem.avgRdBW 46.03 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 30.33 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 46.03 # Average consumed read bandwidth in MB/s
@@ -186,12 +186,12 @@
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.48 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.02 # Average read queue length over time
-system.physmem.avgWrQLen 8.48 # Average write queue length over time
-system.physmem.readRowHits 128585 # Number of row buffer hits during reads
-system.physmem.writeRowHits 35174 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 36.03 # Row buffer hit rate for writes
-system.physmem.avgGap 838163.90 # Average gap between requests
+system.physmem.avgWrQLen 8.63 # Average write queue length over time
+system.physmem.readRowHits 128528 # Number of row buffer hits during reads
+system.physmem.writeRowHits 35061 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 86.78 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 35.91 # Row buffer hit rate for writes
+system.physmem.avgGap 838077.47 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -235,454 +235,576 @@
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
-system.cpu.numCycles 412039742 # number of cpu cycles simulated
+system.cpu.numCycles 412049214 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 182071983 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 142381295 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 7268299 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 93564777 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 88700041 # Number of BTB hits
+system.cpu.BPredUnit.lookups 182068030 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 142371650 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 7270692 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 93491623 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 88706856 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 12685099 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 116083 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 117148048 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 763048101 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 182071983 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 101385140 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 170894035 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 35686363 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 89221488 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 506 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 45 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 113043343 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 2441081 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 404881843 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.113466 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.961359 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 12684721 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 116337 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 117167260 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 763059580 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 182068030 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 101391577 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 170902348 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 35691223 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 89206735 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 90 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 447 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 62 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 113060023 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 2443326 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 404896941 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.113484 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.961332 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 234000478 57.79% 57.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 14180958 3.50% 61.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 22900692 5.66% 66.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 22746852 5.62% 72.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 20902415 5.16% 77.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 13082439 3.23% 80.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 13044714 3.22% 84.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 11995563 2.96% 87.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 52027732 12.85% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 234007224 57.79% 57.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 14183787 3.50% 61.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 22898202 5.66% 66.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 22746913 5.62% 72.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 20897614 5.16% 77.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 13086335 3.23% 80.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 13059349 3.23% 84.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 11995905 2.96% 87.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 52021612 12.85% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 404881843 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.441880 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.851880 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 127553544 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 83254868 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 161072807 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 5457053 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 27543571 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 26128616 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 76844 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 833018746 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 296404 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 27543571 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 135629156 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 9608106 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 57992007 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 158279608 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 15829395 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 804332023 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 1038 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 3062506 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 8833795 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 346 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 960234545 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3519895125 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3519893415 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1710 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 672200323 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 288034222 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 3037420 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 3037417 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 49050394 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 170961338 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 74175754 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 28008123 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 15620624 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 757949088 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 4467543 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 668974363 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1389643 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 187239707 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 479750925 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 746407 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 404881843 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.652271 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.728361 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 404896941 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.441860 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.851865 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 127568061 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 83247236 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 161078099 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 5457696 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 27545849 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 26128375 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 76880 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 833033782 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 297363 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 27545849 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 135637511 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 9603466 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 58001862 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 158291644 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 15816609 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 804360707 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 1150 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 3056892 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 8825253 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 274 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 960209661 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3520079656 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3520077996 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1660 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 672200315 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 288009346 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 3037560 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 3037556 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 48985402 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 170961044 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 74192431 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 27929541 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 15655992 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 757955551 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 4467760 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 669035735 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1391656 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 187243555 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 479554620 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 746625 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 404896941 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.652361 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.728633 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 145293299 35.89% 35.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 75809300 18.72% 54.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 69100310 17.07% 71.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 53699574 13.26% 84.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 30880132 7.63% 92.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 16168967 3.99% 96.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 9289317 2.29% 98.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3363096 0.83% 99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1277848 0.32% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 145342748 35.90% 35.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 75751868 18.71% 54.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 69103679 17.07% 71.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 53697004 13.26% 84.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 30880919 7.63% 92.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 16180758 4.00% 96.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 9302044 2.30% 98.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3357601 0.83% 99.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1280320 0.32% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 404881843 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 404896941 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 478346 4.98% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 6550639 68.20% 73.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2576691 26.82% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 478504 4.99% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 6546722 68.33% 73.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 2556023 26.68% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 449945039 67.26% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 383598 0.06% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 120 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 154114870 23.04% 90.35% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 64530733 9.65% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 449967918 67.26% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 383484 0.06% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 154140670 23.04% 90.35% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 64543544 9.65% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 668974363 # Type of FU issued
-system.cpu.iq.rate 1.623568 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 9605676 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.014359 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1753825613 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 950462588 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 649623996 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 275 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 376 # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total 669035735 # Type of FU issued
+system.cpu.iq.rate 1.623679 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 9581249 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.014321 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1753941049 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 950473417 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 649676758 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 267 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 364 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 678579900 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 139 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 8555633 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses 678616849 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 135 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 8574736 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 44188279 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 40573 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 810259 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 16571773 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 44187986 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 40720 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 810577 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 16588451 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 19511 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 4184 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 19568 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 4004 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 27543571 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 4982601 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 373964 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 763975241 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1120254 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 170961338 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 74175754 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 2978807 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 219858 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 11158 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 810259 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 4340256 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4003229 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 8343485 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 659478369 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 150829210 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 9495994 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 27545849 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 4988149 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 372803 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 763982304 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 1114436 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 170961044 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 74192431 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 2979014 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 218503 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 11510 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 810577 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 4341639 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 4005453 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 8347092 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 659537182 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 150855099 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 9498553 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1558610 # number of nop insts executed
-system.cpu.iew.exec_refs 214064543 # number of memory reference insts executed
-system.cpu.iew.exec_branches 139194602 # Number of branches executed
-system.cpu.iew.exec_stores 63235333 # Number of stores executed
-system.cpu.iew.exec_rate 1.600521 # Inst execution rate
-system.cpu.iew.wb_sent 654596597 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 649624012 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 375406719 # num instructions producing a value
-system.cpu.iew.wb_consumers 646267574 # num instructions consuming a value
+system.cpu.iew.exec_nop 1558993 # number of nop insts executed
+system.cpu.iew.exec_refs 214102413 # number of memory reference insts executed
+system.cpu.iew.exec_branches 139198797 # Number of branches executed
+system.cpu.iew.exec_stores 63247314 # Number of stores executed
+system.cpu.iew.exec_rate 1.600627 # Inst execution rate
+system.cpu.iew.wb_sent 654653382 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 649676774 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 375457821 # num instructions producing a value
+system.cpu.iew.wb_consumers 646369335 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.576605 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.580884 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.576697 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.580872 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 189315872 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 3721136 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 7194171 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 377338273 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.522999 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.206666 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 189322511 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 3721135 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 7196542 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 377351093 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.522947 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.207142 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 165593996 43.88% 43.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 102356552 27.13% 71.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 34023160 9.02% 80.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 18860248 5.00% 85.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 16133947 4.28% 89.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 7612237 2.02% 91.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 6942439 1.84% 93.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3075088 0.81% 93.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 22740606 6.03% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 165639440 43.90% 43.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 102355544 27.12% 71.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 34004026 9.01% 80.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 18854456 5.00% 85.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 16118319 4.27% 89.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 7599031 2.01% 91.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 6941679 1.84% 93.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3068571 0.81% 93.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 22770027 6.03% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 377338273 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 510299127 # Number of instructions committed
-system.cpu.commit.committedOps 574685687 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 377351093 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 510299122 # Number of instructions committed
+system.cpu.commit.committedOps 574685682 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 184377040 # Number of memory references committed
-system.cpu.commit.loads 126773059 # Number of loads committed
+system.cpu.commit.refs 184377038 # Number of memory references committed
+system.cpu.commit.loads 126773058 # Number of loads committed
system.cpu.commit.membars 1488542 # Number of memory barriers committed
-system.cpu.commit.branches 122291805 # Number of branches committed
+system.cpu.commit.branches 122291804 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 473701709 # Number of committed integer instructions.
+system.cpu.commit.int_insts 473701705 # Number of committed integer instructions.
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 22740606 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 22770027 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1118592088 # The number of ROB reads
-system.cpu.rob.rob_writes 1555667472 # The number of ROB writes
-system.cpu.timesIdled 306583 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 7157899 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 508955243 # Number of Instructions Simulated
-system.cpu.committedOps 573341803 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 508955243 # Number of Instructions Simulated
-system.cpu.cpi 0.809580 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.809580 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.235209 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.235209 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3078155858 # number of integer regfile reads
-system.cpu.int_regfile_writes 757766233 # number of integer regfile writes
+system.cpu.rob.rob_reads 1118582121 # The number of ROB reads
+system.cpu.rob.rob_writes 1555682986 # The number of ROB writes
+system.cpu.timesIdled 306922 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 7152273 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 508955238 # Number of Instructions Simulated
+system.cpu.committedOps 573341798 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 508955238 # Number of Instructions Simulated
+system.cpu.cpi 0.809598 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.809598 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.235181 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.235181 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3078487600 # number of integer regfile reads
+system.cpu.int_regfile_writes 757812476 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 990216760 # number of misc regfile reads
-system.cpu.misc_regfile_writes 4464092 # number of misc regfile writes
-system.cpu.icache.replacements 14932 # number of replacements
-system.cpu.icache.tagsinuse 1085.088818 # Cycle average of tags in use
-system.cpu.icache.total_refs 113022367 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 16785 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 6733.533929 # Average number of references to valid blocks.
+system.cpu.misc_regfile_reads 213834943 # number of misc regfile reads
+system.cpu.misc_regfile_writes 4464090 # number of misc regfile writes
+system.cpu.icache.replacements 14939 # number of replacements
+system.cpu.icache.tagsinuse 1085.691077 # Cycle average of tags in use
+system.cpu.icache.total_refs 113039002 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 16794 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 6730.915922 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1085.088818 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.529829 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.529829 # Average percentage of cache occupancy
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@@ -691,195 +813,69 @@
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+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3396 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43497 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 46893 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 11 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101293 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 101293 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3396 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 144790 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 148186 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3396 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 144790 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 148186 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 150961260 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1989439233 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2140400493 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 110011 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 110011 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4107848419 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4107848419 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 150961260 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6097287652 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 6248248912 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 150961260 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6097287652 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 6248248912 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.202408 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051304 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054236 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.126437 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.126437 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290320 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290320 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.202408 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120988 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.122114 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.202408 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120988 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.122114 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44452.667845 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45737.389544 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45644.349754 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40439.801652 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40439.801652 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43336.997353 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42062.885312 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42092.120688 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43336.997353 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42062.885312 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42092.120688 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40554.119426 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40554.119426 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44452.667845 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42111.248374 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42164.907022 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44452.667845 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42111.248374 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42164.907022 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1192198 # number of replacements
-system.cpu.dcache.tagsinuse 4054.757782 # Cycle average of tags in use
-system.cpu.dcache.total_refs 191677610 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1196294 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 160.226173 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 4661028000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4054.757782 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.989931 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.989931 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 136219311 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 136219311 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 50992877 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 50992877 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233119 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 2233119 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 2232045 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 2232045 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 187212188 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 187212188 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 187212188 # number of overall hits
-system.cpu.dcache.overall_hits::total 187212188 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1693600 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1693600 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 3246429 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 3246429 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 39 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 39 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 4940029 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 4940029 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 4940029 # number of overall misses
-system.cpu.dcache.overall_misses::total 4940029 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 25893319000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 25893319000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 58743058946 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 58743058946 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 632500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 632500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 84636377946 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 84636377946 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 84636377946 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 84636377946 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 137912911 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 137912911 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233158 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 2233158 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232045 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 2232045 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 192152217 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 192152217 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 192152217 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 192152217 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012280 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.012280 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059854 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.059854 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000017 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000017 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.025709 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.025709 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.025709 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.025709 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15288.922414 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15288.922414 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18094.669234 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 18094.669234 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16217.948718 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16217.948718 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 17132.769453 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 17132.769453 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 17132.769453 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 17132.769453 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 16010 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 16009 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1643 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 605 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.744370 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 26.461157 # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1110628 # number of writebacks
-system.cpu.dcache.writebacks::total 1110628 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 845499 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 845499 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2898153 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2898153 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 39 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 39 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3743652 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3743652 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3743652 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3743652 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848101 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 848101 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348276 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 348276 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1196377 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1196377 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1196377 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1196377 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11475197000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 11475197000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257593997 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257593997 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19732790997 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 19732790997 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19732790997 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 19732790997 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006150 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006150 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006421 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006226 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.006226 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006226 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.006226 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13530.460405 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13530.460405 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23709.913968 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23709.913968 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16493.789998 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 16493.789998 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16493.789998 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 16493.789998 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index e8af9a7..210b47f 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@
sim_ticks 68267465500 # Number of ticks simulated
final_tick 68267465500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 130031 # Simulator instruction rate (inst/s)
-host_op_rate 166236 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 32510221 # Simulator tick rate (ticks/s)
-host_mem_usage 238756 # Number of bytes of host memory used
-host_seconds 2099.88 # Real time elapsed on the host
+host_inst_rate 160764 # Simulator instruction rate (inst/s)
+host_op_rate 205527 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 40194170 # Simulator tick rate (ticks/s)
+host_mem_usage 285344 # Number of bytes of host memory used
+host_seconds 1698.44 # Real time elapsed on the host
sim_insts 273048375 # Number of instructions simulated
sim_ops 349076099 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 193920 # Number of bytes read from this memory
@@ -496,7 +496,7 @@
system.cpu.int_regfile_writes 232713829 # number of integer regfile writes
system.cpu.fp_regfile_reads 188383123 # number of floating regfile reads
system.cpu.fp_regfile_writes 132609484 # number of floating regfile writes
-system.cpu.misc_regfile_reads 973808735 # number of misc regfile reads
+system.cpu.misc_regfile_reads 567370356 # number of misc regfile reads
system.cpu.misc_regfile_writes 34426415 # number of misc regfile writes
system.cpu.icache.replacements 13908 # number of replacements
system.cpu.icache.tagsinuse 1849.811927 # Cycle average of tags in use
@@ -582,6 +582,132 @@
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18468.059323 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18468.059323 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 1414 # number of replacements
+system.cpu.dcache.tagsinuse 3122.405383 # Cycle average of tags in use
+system.cpu.dcache.total_refs 170873491 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 4624 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 36953.609645 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 3122.405383 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.762306 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.762306 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 88815229 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 88815229 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 82031562 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 82031562 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 13475 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 13475 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 13225 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 13225 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 170846791 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 170846791 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 170846791 # number of overall hits
+system.cpu.dcache.overall_hits::total 170846791 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 4046 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 4046 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 21103 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 21103 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 25149 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 25149 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 25149 # number of overall misses
+system.cpu.dcache.overall_misses::total 25149 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 164690000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 164690000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 831954164 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 831954164 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 996644164 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 996644164 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 996644164 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 996644164 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 88819275 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 88819275 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13477 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 13477 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 13225 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 13225 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 170871940 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 170871940 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 170871940 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 170871940 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.399407 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.399407 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 39629.574297 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 39629.574297 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 13562 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 431 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.466357 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks
+system.cpu.dcache.writebacks::total 1040 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2234 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 2234 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 20525 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 20525 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 20525 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 20525 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1812 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1812 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 4624 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 4624 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 4624 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 4624 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79757000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 79757000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131966500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 131966500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211723500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 211723500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211723500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 211723500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.004415 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.004415 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46929.765292 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46929.765292 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45787.954152 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 45787.954152 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45787.954152 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 45787.954152 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 3959.582107 # Cycle average of tags in use
system.cpu.l2cache.total_refs 13162 # Total number of references to valid blocks.
@@ -727,131 +853,5 @@
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34915.655730 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35424.311635 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1414 # number of replacements
-system.cpu.dcache.tagsinuse 3122.405383 # Cycle average of tags in use
-system.cpu.dcache.total_refs 170873491 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 4624 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 36953.609645 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 3122.405383 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.762306 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.762306 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 88815229 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 88815229 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 82031562 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 82031562 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 13475 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 13475 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 13225 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 13225 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 170846791 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 170846791 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 170846791 # number of overall hits
-system.cpu.dcache.overall_hits::total 170846791 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 4046 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 4046 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 21103 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 21103 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 25149 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 25149 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 25149 # number of overall misses
-system.cpu.dcache.overall_misses::total 25149 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 164690000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 164690000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 831954164 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 831954164 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 996644164 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 996644164 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 996644164 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 996644164 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 88819275 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 88819275 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13477 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 13477 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 13225 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 13225 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 170871940 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 170871940 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 170871940 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 170871940 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.399407 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.399407 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 39629.574297 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 39629.574297 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 13562 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 431 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.466357 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks
-system.cpu.dcache.writebacks::total 1040 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2234 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 2234 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 20525 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 20525 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 20525 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 20525 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1812 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1812 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 4624 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 4624 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 4624 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 4624 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79757000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 79757000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131966500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 131966500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211723500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 211723500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211723500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 211723500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.004415 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.004415 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46929.765292 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46929.765292 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45787.954152 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 45787.954152 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45787.954152 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 45787.954152 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index 65535d5..2c9a289 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@
sim_ticks 624867585500 # Number of ticks simulated
final_tick 624867585500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 92987 # Simulator instruction rate (inst/s)
-host_op_rate 126636 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 41971725 # Simulator tick rate (ticks/s)
-host_mem_usage 253512 # Number of bytes of host memory used
-host_seconds 14887.82 # Real time elapsed on the host
+host_inst_rate 118271 # Simulator instruction rate (inst/s)
+host_op_rate 161069 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 53384157 # Simulator tick rate (ticks/s)
+host_mem_usage 298364 # Number of bytes of host memory used
+host_seconds 11705.11 # Real time elapsed on the host
sim_insts 1384379060 # Number of instructions simulated
sim_ops 1885333812 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 155584 # Number of bytes read from this memory
@@ -502,7 +502,7 @@
system.cpu.int_regfile_writes 2224868034 # number of integer regfile writes
system.cpu.fp_regfile_reads 68796296 # number of floating regfile reads
system.cpu.fp_regfile_writes 49549961 # number of floating regfile writes
-system.cpu.misc_regfile_reads 3658188004 # number of misc regfile reads
+system.cpu.misc_regfile_reads 1363964167 # number of misc regfile reads
system.cpu.misc_regfile_writes 13776290 # number of misc regfile writes
system.cpu.icache.replacements 22546 # number of replacements
system.cpu.icache.tagsinuse 1642.542137 # Cycle average of tags in use
@@ -588,6 +588,132 @@
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system.cpu.l2cache.tagsinuse 32688.524201 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1109720 # Total number of references to valid blocks.
@@ -751,131 +877,5 @@
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.141550 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.706738 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45265.706738 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index 69c6238..0ed850d 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@
sim_ticks 26292466000 # Number of ticks simulated
final_tick 26292466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 115195 # Simulator instruction rate (inst/s)
-host_op_rate 163465 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 42703788 # Simulator tick rate (ticks/s)
-host_mem_usage 260928 # Number of bytes of host memory used
-host_seconds 615.69 # Real time elapsed on the host
+host_inst_rate 139577 # Simulator instruction rate (inst/s)
+host_op_rate 198063 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 51742306 # Simulator tick rate (ticks/s)
+host_mem_usage 305460 # Number of bytes of host memory used
+host_seconds 508.14 # Real time elapsed on the host
sim_insts 70925094 # Number of instructions simulated
sim_ops 100644341 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 298432 # Number of bytes read from this memory
@@ -503,7 +503,7 @@
system.cpu.int_regfile_writes 103318196 # number of integer regfile writes
system.cpu.fp_regfile_reads 686 # number of floating regfile reads
system.cpu.fp_regfile_writes 582 # number of floating regfile writes
-system.cpu.misc_regfile_reads 143076838 # number of misc regfile reads
+system.cpu.misc_regfile_reads 49170129 # number of misc regfile reads
system.cpu.misc_regfile_writes 38826 # number of misc regfile writes
system.cpu.icache.replacements 30543 # number of replacements
system.cpu.icache.tagsinuse 1820.333452 # Cycle average of tags in use
@@ -589,6 +589,132 @@
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17656.139734 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 17656.139734 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 158306 # number of replacements
+system.cpu.dcache.tagsinuse 4072.986675 # Cycle average of tags in use
+system.cpu.dcache.total_refs 44343623 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 162402 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 273.048503 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 280868000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4072.986675 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.994382 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.994382 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 26038019 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 26038019 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 18265169 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 18265169 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 20453 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 20453 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 19412 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 19412 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 44303188 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 44303188 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 44303188 # number of overall hits
+system.cpu.dcache.overall_hits::total 44303188 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 124631 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 124631 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1584732 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1584732 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 1709363 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1709363 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1709363 # number of overall misses
+system.cpu.dcache.overall_misses::total 1709363 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 4670085000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 4670085000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 120039172981 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 120039172981 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 743000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 743000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 124709257981 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 124709257981 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 124709257981 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 124709257981 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 26162650 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 26162650 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20493 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 20493 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 19412 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 19412 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 46012551 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 46012551 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 46012551 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 46012551 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079836 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.079836 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001952 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001952 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.037150 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.037150 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.037150 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.037150 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.295264 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 37471.295264 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18575 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18575 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72956.568020 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72956.568020 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 4330 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 648 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.605839 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 43.200000 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 129052 # number of writebacks
+system.cpu.dcache.writebacks::total 129052 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69229 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 69229 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477415 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1477415 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1546644 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1546644 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1546644 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1546644 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55402 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 55402 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107317 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 107317 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 162719 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 162719 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 162719 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2060277500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2060277500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8253592492 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8253592492 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10313869992 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10313869992 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10313869992 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10313869992 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.782030 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.782030 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 95650 # number of replacements
system.cpu.l2cache.tagsinuse 30136.955692 # Cycle average of tags in use
system.cpu.l2cache.total_refs 89930 # Total number of references to valid blocks.
@@ -756,131 +882,5 @@
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66158.128182 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65394.171374 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 158306 # number of replacements
-system.cpu.dcache.tagsinuse 4072.986675 # Cycle average of tags in use
-system.cpu.dcache.total_refs 44343623 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 162402 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 273.048503 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 280868000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4072.986675 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.994382 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.994382 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 26038019 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 26038019 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 18265169 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 18265169 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 20453 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 20453 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 19412 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 19412 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 44303188 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 44303188 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 44303188 # number of overall hits
-system.cpu.dcache.overall_hits::total 44303188 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 124631 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 124631 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1584732 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1584732 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 1709363 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1709363 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1709363 # number of overall misses
-system.cpu.dcache.overall_misses::total 1709363 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 4670085000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 4670085000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 120039172981 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 120039172981 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 743000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 743000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 124709257981 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 124709257981 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 124709257981 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 124709257981 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 26162650 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 26162650 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20493 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 20493 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 19412 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 19412 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 46012551 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 46012551 # number of demand (read+write) accesses
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-system.cpu.dcache.overall_accesses::total 46012551 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079836 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.079836 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001952 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001952 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.037150 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.037150 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.037150 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.037150 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.295264 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 37471.295264 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18575 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18575 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 72956.568020 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 72956.568020 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 4330 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 648 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.605839 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 43.200000 # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 129052 # number of writebacks
-system.cpu.dcache.writebacks::total 129052 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69229 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 69229 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477415 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1477415 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1546644 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1546644 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1546644 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1546644 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55402 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 55402 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107317 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 107317 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 162719 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 162719 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 162719 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2060277500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2060277500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8253592492 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8253592492 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10313869992 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10313869992 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10313869992 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10313869992 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.782030 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.782030 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index 2a9784b..312dc86 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@
sim_ticks 506342716000 # Number of ticks simulated
final_tick 506342716000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 134396 # Simulator instruction rate (inst/s)
-host_op_rate 149928 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 44057957 # Simulator tick rate (ticks/s)
-host_mem_usage 522896 # Number of bytes of host memory used
-host_seconds 11492.65 # Real time elapsed on the host
+host_inst_rate 168217 # Simulator instruction rate (inst/s)
+host_op_rate 187658 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 55145312 # Simulator tick rate (ticks/s)
+host_mem_usage 540496 # Number of bytes of host memory used
+host_seconds 9181.97 # Real time elapsed on the host
sim_insts 1544563043 # Number of instructions simulated
sim_ops 1723073855 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 47744 # Number of bytes read from this memory
@@ -502,7 +502,7 @@
system.cpu.int_regfile_writes 1936551418 # number of integer regfile writes
system.cpu.fp_regfile_reads 155 # number of floating regfile reads
system.cpu.fp_regfile_writes 154 # number of floating regfile writes
-system.cpu.misc_regfile_reads 2914618242 # number of misc regfile reads
+system.cpu.misc_regfile_reads 737521382 # number of misc regfile reads
system.cpu.misc_regfile_writes 132 # number of misc regfile writes
system.cpu.icache.replacements 22 # number of replacements
system.cpu.icache.tagsinuse 625.107966 # Cycle average of tags in use
@@ -588,6 +588,132 @@
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53966.451613 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53966.451613 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 9598051 # number of replacements
+system.cpu.dcache.tagsinuse 4087.935978 # Cycle average of tags in use
+system.cpu.dcache.total_refs 655966956 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 9602147 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 68.314613 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 3423729000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4087.935978 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.998031 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.998031 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 488912900 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 488912900 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 167053904 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 167053904 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 87 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 87 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 65 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 65 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 655966804 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 655966804 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 655966804 # number of overall hits
+system.cpu.dcache.overall_hits::total 655966804 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 11479195 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 11479195 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 5532143 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 5532143 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 17011338 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 17011338 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 17011338 # number of overall misses
+system.cpu.dcache.overall_misses::total 17011338 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 299504228000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 299504228000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 217114926916 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 217114926916 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 187000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 516619154916 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 516619154916 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 516619154916 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 516619154916 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 500392095 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 500392095 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 90 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 90 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 65 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 65 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 672978142 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 672978142 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 672978142 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 672978142 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022940 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.022940 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032054 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.032054 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.033333 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.033333 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.025278 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.025278 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.025278 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.025278 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26091.048022 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 26091.048022 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39246.080030 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39246.080030 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62333.333333 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62333.333333 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 30369.107646 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30369.107646 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 30369.107646 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 30369.107646 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 19754018 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 992148 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 1171998 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 64543 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.854993 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 15.371892 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 3781955 # number of writebacks
+system.cpu.dcache.writebacks::total 3781955 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3770552 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 3770552 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3638638 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 3638638 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 7409190 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 7409190 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 7409190 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 7409190 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708643 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 7708643 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893505 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1893505 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 9602148 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 9602148 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 9602148 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 9602148 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 170578712500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 170578712500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71843645589 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 71843645589 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 242422358089 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 242422358089 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 242422358089 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 242422358089 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015405 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015405 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.014268 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.014268 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22128.241313 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22128.241313 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37942.147282 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37942.147282 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25246.680023 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25246.680023 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25246.680023 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25246.680023 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2214170 # number of replacements
system.cpu.l2cache.tagsinuse 31523.647608 # Cycle average of tags in use
system.cpu.l2cache.total_refs 9246689 # Total number of references to valid blocks.
@@ -735,131 +861,5 @@
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57222.037086 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57216.963806 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 9598051 # number of replacements
-system.cpu.dcache.tagsinuse 4087.935978 # Cycle average of tags in use
-system.cpu.dcache.total_refs 655966956 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 9602147 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 68.314613 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 3423729000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4087.935978 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.998031 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.998031 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 488912900 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 488912900 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 167053904 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 167053904 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 87 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 87 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 65 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 65 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 655966804 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 655966804 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 655966804 # number of overall hits
-system.cpu.dcache.overall_hits::total 655966804 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 11479195 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 11479195 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 5532143 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 5532143 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 17011338 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 17011338 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 17011338 # number of overall misses
-system.cpu.dcache.overall_misses::total 17011338 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 299504228000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 299504228000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 217114926916 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 217114926916 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 187000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 516619154916 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 516619154916 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 516619154916 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 516619154916 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 500392095 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 500392095 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 90 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 90 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 65 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 65 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 672978142 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 672978142 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 672978142 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 672978142 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022940 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.022940 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032054 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.032054 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.033333 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.033333 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.025278 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.025278 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.025278 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.025278 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26091.048022 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 26091.048022 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39246.080030 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39246.080030 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62333.333333 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62333.333333 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 30369.107646 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 30369.107646 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 30369.107646 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 30369.107646 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 19754018 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 992148 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1171998 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 64543 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.854993 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 15.371892 # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3781955 # number of writebacks
-system.cpu.dcache.writebacks::total 3781955 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3770552 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 3770552 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3638638 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 3638638 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 7409190 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 7409190 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 7409190 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 7409190 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708643 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 7708643 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893505 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1893505 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 9602148 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 9602148 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 9602148 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 9602148 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 170578712500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 170578712500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71843645589 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 71843645589 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 242422358089 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 242422358089 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 242422358089 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 242422358089 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015405 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015405 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.014268 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.014268 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22128.241313 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22128.241313 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37942.147282 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37942.147282 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25246.680023 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25246.680023 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25246.680023 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25246.680023 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index 3417645..144145b 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@
sim_ticks 74245032000 # Number of ticks simulated
final_tick 74245032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 109443 # Simulator instruction rate (inst/s)
-host_op_rate 119829 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47150577 # Simulator tick rate (ticks/s)
-host_mem_usage 234068 # Number of bytes of host memory used
-host_seconds 1574.64 # Real time elapsed on the host
+host_inst_rate 131550 # Simulator instruction rate (inst/s)
+host_op_rate 144033 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 56674428 # Simulator tick rate (ticks/s)
+host_mem_usage 280244 # Number of bytes of host memory used
+host_seconds 1310.03 # Real time elapsed on the host
sim_insts 172333441 # Number of instructions simulated
sim_ops 188686923 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 131008 # Number of bytes read from this memory
@@ -497,7 +497,7 @@
system.cpu.int_regfile_writes 384939818 # number of integer regfile writes
system.cpu.fp_regfile_reads 2913621 # number of floating regfile reads
system.cpu.fp_regfile_writes 2497505 # number of floating regfile writes
-system.cpu.misc_regfile_reads 464692735 # number of misc regfile reads
+system.cpu.misc_regfile_reads 54528814 # number of misc regfile reads
system.cpu.misc_regfile_writes 832204 # number of misc regfile writes
system.cpu.icache.replacements 2508 # number of replacements
system.cpu.icache.tagsinuse 1347.136586 # Cycle average of tags in use
@@ -583,6 +583,132 @@
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28969.199670 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 28969.199670 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 57 # number of replacements
+system.cpu.dcache.tagsinuse 1406.445400 # Cycle average of tags in use
+system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 1406.445400 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits
+system.cpu.dcache.overall_hits::total 46746842 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses
+system.cpu.dcache.overall_misses::total 9552 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 82596000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 82596000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 375316496 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 375316496 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 375316496 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 375316496 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45060.556465 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 45060.556465 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 39291.927973 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 39291.927973 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
+system.cpu.dcache.writebacks::total 18 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36781000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 36781000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84191498 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 84191498 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84191498 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 84191498 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47705.577173 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47705.577173 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 1961.084973 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2275 # Total number of references to valid blocks.
@@ -742,131 +868,5 @@
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33800.926648 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34107.570788 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 57 # number of replacements
-system.cpu.dcache.tagsinuse 1406.445400 # Cycle average of tags in use
-system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 1406.445400 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits
-system.cpu.dcache.overall_hits::total 46746842 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses
-system.cpu.dcache.overall_misses::total 9552 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 82596000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 82596000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 375316496 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 375316496 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 375316496 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 375316496 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45060.556465 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 45060.556465 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 39291.927973 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 39291.927973 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
-system.cpu.dcache.writebacks::total 18 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36781000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 36781000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84191498 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 84191498 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84191498 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 84191498 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47705.577173 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47705.577173 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index 0b4c661..28f275f 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -4,10 +4,10 @@
sim_ticks 13371000 # Number of ticks simulated
final_tick 13371000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 32660 # Simulator instruction rate (inst/s)
-host_op_rate 40743 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 94998008 # Simulator tick rate (ticks/s)
-host_mem_usage 228356 # Number of bytes of host memory used
+host_inst_rate 32987 # Simulator instruction rate (inst/s)
+host_op_rate 41149 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 95942804 # Simulator tick rate (ticks/s)
+host_mem_usage 272856 # Number of bytes of host memory used
host_seconds 0.14 # Real time elapsed on the host
sim_insts 4596 # Number of instructions simulated
sim_ops 5734 # Number of ops (including micro ops) simulated
@@ -537,7 +537,7 @@
system.cpu.int_regfile_reads 39369 # number of integer regfile reads
system.cpu.int_regfile_writes 8027 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 15007 # number of misc regfile reads
+system.cpu.misc_regfile_reads 2981 # number of misc regfile reads
system.cpu.misc_regfile_writes 26 # number of misc regfile writes
system.cpu.icache.replacements 4 # number of replacements
system.cpu.icache.tagsinuse 147.796211 # Cycle average of tags in use
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
index c182ad1..675d120 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -30,7 +30,7 @@
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -78,7 +78,6 @@
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
-isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@@ -458,23 +457,6 @@
[system.cpu.interrupts]
type=ArmInterrupts
-[system.cpu.isa]
-type=ArmISA
-fpsid=1090793632
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=3
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=4027589137
-id_pfr0=49
-id_pfr1=1
-midr=890224640
-
[system.cpu.itb]
type=ArmTLB
children=walker
@@ -536,7 +518,7 @@
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+executable=tests/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index 76131bc..11fc8e2 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -4,10 +4,10 @@
sim_ticks 13371000 # Number of ticks simulated
final_tick 13371000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 37264 # Simulator instruction rate (inst/s)
-host_op_rate 46486 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 108387516 # Simulator tick rate (ticks/s)
-host_mem_usage 228452 # Number of bytes of host memory used
+host_inst_rate 36978 # Simulator instruction rate (inst/s)
+host_op_rate 46127 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 107546339 # Simulator tick rate (ticks/s)
+host_mem_usage 272728 # Number of bytes of host memory used
host_seconds 0.12 # Real time elapsed on the host
sim_insts 4596 # Number of instructions simulated
sim_ops 5734 # Number of ops (including micro ops) simulated
@@ -492,7 +492,7 @@
system.cpu.int_regfile_reads 39369 # number of integer regfile reads
system.cpu.int_regfile_writes 8027 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 15007 # number of misc regfile reads
+system.cpu.misc_regfile_reads 2981 # number of misc regfile reads
system.cpu.misc_regfile_writes 26 # number of misc regfile writes
system.cpu.icache.replacements 4 # number of replacements
system.cpu.icache.tagsinuse 147.796211 # Cycle average of tags in use
@@ -578,6 +578,130 @@
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 86.861870 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 86.861870 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.021207 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.021207 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 2371 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2371 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2371 # number of overall hits
+system.cpu.dcache.overall_hits::total 2371 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses
+system.cpu.dcache.overall_misses::total 498 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 8138000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 8138000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 23045500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 23045500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 23045500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 23045500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097648 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.097648 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.173580 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 46276.104418 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 46276.104418 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4925000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4925000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7238500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7238500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7238500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7238500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.264151 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46462.264151 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 186.102289 # Cycle average of tags in use
system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
@@ -712,129 +836,5 @@
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 86.861870 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 86.861870 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.021207 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.021207 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 2371 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2371 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2371 # number of overall hits
-system.cpu.dcache.overall_hits::total 2371 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses
-system.cpu.dcache.overall_misses::total 498 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 8138000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 8138000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 23045500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 23045500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 23045500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 23045500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097648 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.097648 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.173580 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 46276.104418 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 46276.104418 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4925000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4925000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7238500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 7238500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7238500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 7238500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.264151 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46462.264151 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index 1c2308a..92d6d9a 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -463,7 +463,7 @@
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index 13ed71f..bb0098d 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -4,11 +4,11 @@
sim_ticks 104830500 # Number of ticks simulated
final_tick 104830500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 100032 # Simulator instruction rate (inst/s)
-host_op_rate 100032 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 10132772 # Simulator tick rate (ticks/s)
-host_mem_usage 236868 # Number of bytes of host memory used
-host_seconds 10.35 # Real time elapsed on the host
+host_inst_rate 112424 # Simulator instruction rate (inst/s)
+host_op_rate 112424 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 11388036 # Simulator tick rate (ticks/s)
+host_mem_usage 275264 # Number of bytes of host memory used
+host_seconds 9.21 # Real time elapsed on the host
sim_insts 1034897 # Number of instructions simulated
sim_ops 1034897 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory
@@ -952,7 +952,7 @@
system.cpu1.int_regfile_writes 197149 # number of integer regfile writes
system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
system.cpu1.misc_regfile_reads 122869 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 646 # number of misc regfile writes
+system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
system.cpu1.icache.replacements 317 # number of replacements
system.cpu1.icache.tagsinuse 85.783317 # Cycle average of tags in use
system.cpu1.icache.total_refs 18178 # Total number of references to valid blocks.
@@ -1426,7 +1426,7 @@
system.cpu2.int_regfile_writes 150022 # number of integer regfile writes
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
system.cpu2.misc_regfile_reads 88362 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 646 # number of misc regfile writes
+system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
system.cpu2.icache.replacements 319 # number of replacements
system.cpu2.icache.tagsinuse 80.119670 # Cycle average of tags in use
system.cpu2.icache.total_refs 24566 # Total number of references to valid blocks.
@@ -1900,7 +1900,7 @@
system.cpu3.int_regfile_writes 198982 # number of integer regfile writes
system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
system.cpu3.misc_regfile_reads 124365 # number of misc regfile reads
-system.cpu3.misc_regfile_writes 646 # number of misc regfile writes
+system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
system.cpu3.icache.replacements 318 # number of replacements
system.cpu3.icache.tagsinuse 83.493816 # Cycle average of tags in use
system.cpu3.icache.total_refs 18731 # Total number of references to valid blocks.
