diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
new file mode 100644
index 0000000..3b827b5
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
@@ -0,0 +1,1265 @@
+[root]
+type=Root
+children=system
+full_system=true
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxAlphaSystem
+children=bridge cpu0 cpu1 cpu2 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
+boot_cpu_frequency=500
+boot_osflags=root=/dev/hda1 console=ttyS0
+clock=1000
+console=/arm/scratch/sysexplr/dist/binaries/console
+init_param=0
+kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux
+load_addr_mask=1099511627775
+mem_mode=atomic
+mem_ranges=0:134217727
+memories=system.physmem
+num_work_ids=16
+pal=/arm/scratch/sysexplr/dist/binaries/ts_osfpal
+readfile=tests/halt.sh
+symbolfile=
+system_rev=1024
+system_type=34
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.bridge]
+type=Bridge
+clock=1000
+delay=50000
+ranges=8796093022208:18446744073709551615
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
+
+[system.cpu0]
+type=AtomicSimpleCPU
+children=dcache dtb icache interrupts isa itb tracer
+checker=Null
+clock=500
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu0.dtb
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+switched_out=false
+system=system
+tracer=system.cpu0.tracer
+width=1
+workload=
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=4
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+size=32768
+system=system
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu0.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu0.icache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=1
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+size=32768
+system=system
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.interrupts]
+type=AlphaInterrupts
+
+[system.cpu0.isa]
+type=AlphaISA
+
+[system.cpu0.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu0.tracer]
+type=ExeTracer
+
+[system.cpu1]
+type=TimingSimpleCPU
+children=dtb interrupts isa itb tracer
+checker=Null
+clock=500
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu1.dtb
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+switched_out=true
+system=system
+tracer=system.cpu1.tracer
+workload=
+
+[system.cpu1.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu1.interrupts]
+type=AlphaInterrupts
+
+[system.cpu1.isa]
+type=AlphaISA
+
+[system.cpu1.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu1.tracer]
+type=ExeTracer
+
+[system.cpu2]
+type=DerivO3CPU
+children=dtb fuPool interrupts isa itb tracer
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+dispatchWidth=8
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu2.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu2.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+interrupts=system.cpu2.interrupts
+isa=system.cpu2.isa
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu2.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+needsTSO=false
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+predType=tournament
+profile=0
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+switched_out=true
+system=system
+tracer=system.cpu2.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=
+
+[system.cpu2.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu2.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
+
+[system.cpu2.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu2.fuPool.FUList0.opList
+
+[system.cpu2.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu2.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
+
+[system.cpu2.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu2.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu2.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2
+
+[system.cpu2.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu2.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu2.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu2.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
+
+[system.cpu2.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu2.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu2.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu2.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu2.fuPool.FUList4.opList
+
+[system.cpu2.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu2.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
+
+[system.cpu2.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu2.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu2.fuPool.FUList6.opList
+
+[system.cpu2.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu2.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
+
+[system.cpu2.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu2.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu2.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu2.fuPool.FUList8.opList
+
+[system.cpu2.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu2.interrupts]
+type=AlphaInterrupts
+
+[system.cpu2.isa]
+type=AlphaISA
+
+[system.cpu2.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu2.tracer]
+type=ExeTracer
+
+[system.disk0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.disk0.image
+
+[system.disk0.image]
+type=CowDiskImage
+children=child
+child=system.disk0.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.disk0.image.child]
+type=RawDiskImage
+image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img
+read_only=true
+
+[system.disk2]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.disk2.image
+
+[system.disk2.image]
+type=CowDiskImage
+children=child
+child=system.disk2.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.disk2.image.child]
+type=RawDiskImage
+image_file=/arm/scratch/sysexplr/dist/disks/linux-bigswap2.img
+read_only=true
+
+[system.intrctrl]
+type=IntrControl
+sys=system
+
+[system.iobus]
+type=NoncoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=true
+width=8
+default=system.tsunami.pciconfig.pio
+master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
+
+[system.iocache]
+type=BaseCache
+addr_ranges=0:134217727
+assoc=8
+block_size=64
+clock=1000
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+size=1024
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[29]
+mem_side=system.membus.slave[2]
+
+[system.l2c]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=8
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+size=4194304
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.membus]
+type=CoherentBus
+children=badaddr_responder
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=8
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.physmem.port
+slave=system.system_port system.l2c.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.membus.default
+
+[system.physmem]
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
+conf_table_reported=false
+in_addr_map=true
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
+null=false
+page_policy=open
+range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
+zero=false
+port=system.membus.master[1]
+
+[system.simple_disk]
+type=SimpleDisk
+children=disk
+disk=system.simple_disk.disk
+system=system
+
+[system.simple_disk.disk]
+type=RawDiskImage
+image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img
+read_only=true
+
+[system.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=CoherentBus
+block_size=64
+clock=500
+header_cycles=1
+use_default_range=false
+width=8
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side
+
+[system.tsunami]
+type=Tsunami
+children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+intrctrl=system.intrctrl
+system=system
+
+[system.tsunami.backdoor]
+type=AlphaBackdoor
+clock=1000
+cpu=system.cpu0
+disk=system.simple_disk
+pio_addr=8804682956800
+pio_latency=100000
+platform=system.tsunami
+system=system
+terminal=system.terminal
+pio=system.iobus.master[24]
+
+[system.tsunami.cchip]
+type=TsunamiCChip
+clock=1000
+pio_addr=8803072344064
+pio_latency=100000
+system=system
+tsunami=system.tsunami
+pio=system.iobus.master[0]
+
+[system.tsunami.ethernet]
+type=NSGigE
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=256
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=4096
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=34
+ExpansionROM=0
+HeaderType=0
+InterruptLine=30
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=52
+MinimumGrant=176
+ProgIF=0
+Revision=0
+Status=656
+SubClassCode=0
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=4107
+clock=2000
+config_latency=20000
+dma_data_free=false
+dma_desc_free=false
+dma_no_allocate=true
+dma_read_delay=0
+dma_read_factor=0
+dma_write_delay=0
+dma_write_factor=0
+hardware_address=00:90:00:00:00:01
+intr_delay=10000000
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.tsunami
+rss=false
+rx_delay=1000000
+rx_fifo_size=524288
+rx_filter=true
+rx_thread=false
+system=system
+tx_delay=1000000
+tx_fifo_size=524288
+tx_thread=false
+config=system.iobus.master[28]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[27]
+
+[system.tsunami.fake_OROM]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=8796093677568
+pio_latency=100000
+pio_size=393216
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[8]
+
+[system.tsunami.fake_ata0]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=8804615848432
+pio_latency=100000
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.tsunami.fake_ata1]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=8804615848304
+pio_latency=100000
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.tsunami.fake_pnp_addr]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=8804615848569
+pio_latency=100000
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[9]
+
+[system.tsunami.fake_pnp_read0]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=8804615848451
+pio_latency=100000
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[11]
+
+[system.tsunami.fake_pnp_read1]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=8804615848515
+pio_latency=100000
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.tsunami.fake_pnp_read2]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=8804615848579
+pio_latency=100000
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[13]
+
+[system.tsunami.fake_pnp_read3]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=8804615848643
+pio_latency=100000
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[14]
+
+[system.tsunami.fake_pnp_read4]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=8804615848707
+pio_latency=100000
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[15]
+
+[system.tsunami.fake_pnp_read5]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=8804615848771
+pio_latency=100000
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[16]
+
+[system.tsunami.fake_pnp_read6]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=8804615848835
+pio_latency=100000
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[17]
+
+[system.tsunami.fake_pnp_read7]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=8804615848899
+pio_latency=100000
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[18]
+
+[system.tsunami.fake_pnp_write]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=8804615850617
+pio_latency=100000
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[10]
+
+[system.tsunami.fake_ppc]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=8804615848891
+pio_latency=100000
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[7]
+
+[system.tsunami.fake_sm_chip]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=8804615848816
+pio_latency=100000
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[2]
+
+[system.tsunami.fake_uart1]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=8804615848696
+pio_latency=100000
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[3]
+
+[system.tsunami.fake_uart2]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=8804615848936
+pio_latency=100000
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[4]
+
+[system.tsunami.fake_uart3]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=8804615848680
+pio_latency=100000
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[5]
+
+[system.tsunami.fake_uart4]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=8804615848944
+pio_latency=100000
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[6]
+
+[system.tsunami.fb]
+type=BadDevice
+clock=1000
+devicename=FrameBuffer
+pio_addr=8804615848912
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.tsunami.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=0
+MinimumGrant=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clock=1000
+config_latency=20000
+ctrl_offset=0
+disks=system.disk0 system.disk2
+io_shift=0
+pci_bus=0
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.tsunami
+system=system
+config=system.iobus.master[26]
+dma=system.iobus.slave[1]
+pio=system.iobus.master[25]
+
+[system.tsunami.io]
+type=TsunamiIO
+clock=1000
+frequency=976562500
+pio_addr=8804615847936
+pio_latency=100000
+system=system
+time=Thu Jan  1 00:00:00 2009
+tsunami=system.tsunami
+year_is_bcd=false
+pio=system.iobus.master[22]
+
+[system.tsunami.pchip]
+type=TsunamiPChip
+clock=1000
+pio_addr=8802535473152
+pio_latency=100000
+system=system
+tsunami=system.tsunami
+pio=system.iobus.master[1]
+
+[system.tsunami.pciconfig]
+type=PciConfigAll
+bus=0
+clock=1000
+pio_latency=30000
+platform=system.tsunami
+size=16777216
+system=system
+pio=system.iobus.default
+
+[system.tsunami.uart]
+type=Uart8250
+clock=1000
+pio_addr=8804615848952
+pio_latency=100000
+platform=system.tsunami
+system=system
+terminal=system.terminal
+pio=system.iobus.master[23]
+
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr
new file mode 100755
index 0000000..3c54e08
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr
@@ -0,0 +1,9 @@
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout
new file mode 100755
index 0000000..94a2dd4
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout
@@ -0,0 +1,6245 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Dec 11 2012 16:31:37
+gem5 started Dec 11 2012 16:31:53
+gem5 executing on e103721-lin
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux
+      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
+info: Entering event queue @ 0.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1000000000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2000000000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2000001000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3000001000.  Starting simulation...
+info: Entering event queue @ 3000043000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3000047500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4000047500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 5000047500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5000048000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 6000048000.  Starting simulation...
+info: Entering event queue @ 7452589500.  Starting simulation...
+info: Entering event queue @ 7452657000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 7452661500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 8452661500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 9452661500.  Starting simulation...
+info: Entering event queue @ 9452675500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 9452679000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 10452679000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 10452683500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 11452683500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 12452683500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 12452684500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 13452684500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 13452690000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 14452690000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 15452690000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 15452691000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 16452691000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 16452704500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 17452704500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 18452704500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 18452705500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 19452705500.  Starting simulation...
+info: Entering event queue @ 19452711000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 19452715500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 20452715500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 21452715500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 21452716000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 22452716000.  Starting simulation...
+info: Entering event queue @ 22452727500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 22452733000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 23452733000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 24452733000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 24452734000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 25452734000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 25452745500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 26452745500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 27452745500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 27452746500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 28452746500.  Starting simulation...
+info: Entering event queue @ 28452758500.  Starting simulation...
+info: Entering event queue @ 28452769000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 28452773500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 29452773500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 30452773500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 30452992500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 31452992500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 31452995500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 32452995500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 33452995500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 33452996500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 34452996500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 34452999500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 35452999500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 36452999500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 36453000500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 37453000500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 37453003500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 38453003500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 39453003500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 39453004500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 40453004500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 40453007500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 41453007500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 42453007500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 42453008500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 43453008500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 43945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 44945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 45945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 46945335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 47851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 48851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 49851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 50851585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 51757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 52757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 53757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 54757835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 55664085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 56664085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 57664085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 58664085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 59570335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 60570335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 61570335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 62570335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 63476585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 64476585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 65476585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 66476585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 67382835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 68382835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 69382835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 70382835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 71289085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 72289085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 73289085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 74289085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 75195335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 76195335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 77195335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 78195335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 79101585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 80101585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 81101585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 82101585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 83007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 84007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 85007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 86007835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 86914085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 87914085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 88914085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 89914085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 90820335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 91820335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 92820335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 93820335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 94726585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 95726585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 96726585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 97726585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 98632835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 99632835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 100632835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 101632835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 102539085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 103539085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 104539085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 105539085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 106445335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 107445335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 108445335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 109445335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 110351585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 111351585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 112351585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 113351585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 114257835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 115257835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 116257835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 117257835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 118164085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 119164085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 120164085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 121164085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 122070335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 123070335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 124070335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 125070335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 125976585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 126976585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 127976585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 128976585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 129882835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 130882835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 131882835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 132882835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 133789085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 134789085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 135789085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 136789085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 137695335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 138695335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 139695335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 140695335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 141601585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 142601585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 143601585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 144601585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 145507835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 146507835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 147507835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 148507835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 149414085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 150414085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 151414085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 152414085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 153320335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 154320335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 155320335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 156320335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 157226585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 158226585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 159226585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 160226585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 161132835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 162132835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 163132835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 164132835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 165039085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 166039085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 167039085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 168039085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 168945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 169945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 170945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 171945335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 172851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 173851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 174851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 175851585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 176757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 177757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 178757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 179757835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 180664085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 181664085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 182664085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 183664085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 184570335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 185570335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 186570335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 187570335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 188476585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 189476585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 190476585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 191476585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 192382835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 193382835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 194382835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 195382835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 196289085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 197289085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 198289085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 199289085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 200195335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 201195335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 202195335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 203195335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 204101585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 205101585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 206101585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 207101585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 208007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 209007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 210007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 211007835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 211914085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 212914085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 213914085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 214914085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 215820335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 216820335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 217820335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 218820335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 219726585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 220726585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 221726585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 222726585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 223632835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 224632835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 225632835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 226632835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 227539085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 228539085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 229539085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 230539085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 231445335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 232445335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 233445335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 234445335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 235351585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 236351585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 237351585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 238351585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 239257835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 240257835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 241257835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 242257835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 243164085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 244164085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 245164085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 246164085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 247070335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 248070335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 249070335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 250070335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 250976585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 251976585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 252976585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 253976585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 254882835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 255882835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 256882835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 257882835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 258789085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 259789085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 260789085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 261789085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 262695335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 263695335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 264695335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 265695335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 266601585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 267601585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 268601585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 269601585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 270507835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 271507835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 272507835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 273507835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 274414085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 275414085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 276414085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 277414085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 278320335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 279320335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 280320335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 281320335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 282226585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 283226585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 284226585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 285226585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 286132835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 287132835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 288132835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 289132835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 290039085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 291039085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 292039085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 293039085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 293945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 294945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 295945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 296945335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 297851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 298851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 299851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 300851585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 301757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 302757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 303757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 304757835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 304758059500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 305758059500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 306758059500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 307758059500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 308593773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 309593773000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 310593773000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 311593773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 312500023000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 313500023000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 314500023000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 315500023000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 316406273000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 317406273000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 318406273000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 319406273000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 320312523000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 321312523000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 322312523000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 323312523000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 324218773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 325218773000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 326218773000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 327218773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 328125023000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 329125023000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 330125023000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 331125023000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 332031273000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 333031273000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 334031273000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 335031273000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 335937523000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 336937523000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 337937523000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 338937523000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 339843773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 340843773000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 341843773000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 342843773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 343750023000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 344750023000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 345750023000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 346750023000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 347656273000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 348656273000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 349656273000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 350656273000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 351562523000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 352562523000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 353562523000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 354562523000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 355468773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 356468773000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 357468773000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 358468773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 359375023000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 360375023000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 361375023000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 362375023000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 363281273000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 364281273000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 365281273000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 366281273000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 367187523000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 368187523000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 369187523000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 370187523000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 371093773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 372093773000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 373093773000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 374093773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 375000023000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 376000023000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 377000023000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 378000023000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 378906273000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 379906273000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 380906273000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 381906273000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 382812523000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 383812523000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 384812523000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 385812523000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 386718773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 387718773000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 388718773000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 389718773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 390625023000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 391625023000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 392625023000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 393625023000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 394531273000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 395531273000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 396531273000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 397531273000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 398437523000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 399437523000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 400437523000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 401437523000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 402343773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 403343773000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 404343773000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 405343773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 406250023000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 407250023000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 408250023000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 409250023000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 410156273000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 411156273000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 412156273000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 413156273000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 414062523000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 415062523000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 416062523000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 417062523000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 417968773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 418968773000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 419968773000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 420968773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 421875023000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 422875023000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 423875023000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 424875023000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 425781273000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 426781273000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 427781273000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 428781273000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 429687523000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 430687523000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 431687523000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 432687523000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 433593773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 434593773000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 435593773000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 436593773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 437500023000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 438500023000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 439500023000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 440500023000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 441406273000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 442406273000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 443406273000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 444406273000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 445312523000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 446312523000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 447312523000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 448312523000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 449218773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 450218773000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 451218773000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 452218773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 453125023000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 454125023000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 455125023000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 456125023000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 457031273000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 458031273000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 459031273000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 460031273000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 460937523000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 461937523000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 462937523000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 463937523000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 464843773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 465843773000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 466843773000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 467843773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 468750023000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 469750023000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 470750023000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 471750023000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 472656273000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 473656273000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 474656273000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 475656273000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 476562523000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 477562523000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 478562523000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 479562523000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 480468773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 481468773000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 482468773000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 483468773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 484375023000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 485375023000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 486375023000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 487375023000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 488281273000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 489281273000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 490281273000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 491281273000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 492187523000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 493187523000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 494187523000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 495187523000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 496093773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 497093773000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 498093773000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 499093773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 500000023000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 501000023000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 502000023000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 503000023000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 503906273000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 504906273000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 505906273000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 506906273000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 507812523000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 508812523000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 509812523000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 510812523000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 511718773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 512718773000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 513718773000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 514718773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 515625023000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 516625023000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 517625023000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 518625023000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 519531273000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 520531273000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 521531273000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 522531273000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 523437523000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 524437523000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 525437523000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 526437523000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 527343773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 528343773000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 529343773000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 530343773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 531250023000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 532250023000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 533250023000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 534250023000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 535156273000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 536156273000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 537156273000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 538156273000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 539062523000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 540062523000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 541062523000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 542062523000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 542968773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 543968773000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 544968773000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 545968773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 546875023000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 547875023000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 548875023000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 549875023000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 550781273000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 551781273000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 552781273000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 553781273000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 554687523000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 555687523000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 556687523000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 557687523000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 558593773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 559593773000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 560593773000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 561593773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 562500023000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 563500023000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 564500023000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 565500023000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 566406273000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 567406273000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 568406273000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 568406301000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 569406301000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 570312523000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 571312523000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 572312523000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 573312523000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 574218773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 575218773000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 576218773000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 577218773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 578125023000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 579125023000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 580125023000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 581125023000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 582031273000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 583031273000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 584031273000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 585031273000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 585937523000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 586937523000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 587937523000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 588937523000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 589843773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 590843773000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 591843773000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 592843773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 593750023000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 594750023000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 595750023000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 596750023000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 597656273000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 598656273000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 599656273000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 600656273000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 601562523000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 602562523000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 603562523000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 604562523000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 605468773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 606468773000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 607468773000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 608468773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 609375023000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 610375023000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 611375023000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 612375023000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 613281273000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 614281273000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 615281273000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 616281273000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 617187523000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 618187523000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 619187523000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 620187523000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 621093773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 622093773000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 623093773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 623093773500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 624093773500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 624216549000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 625216549000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 626216549000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 627216549000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 627929709000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 628929709000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 629929709000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 630929709000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 631835960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 632835960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 633835960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 634835960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 635742210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 636742210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 637742210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 638742210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 639648460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 640648460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 641648460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 642648460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 643554710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 644554710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 645554710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 646554710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 647460960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 648460960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 649460960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 650460960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 651367210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 652367210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 653367210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 654367210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 655273460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 656273460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 657273460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 658273460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 659179710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 660179710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 661179710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 662179710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 663085960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 664085960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 665085960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 666085960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 666992210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 667992210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 668992210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 669992210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 670898460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 671898460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 672898460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 673898460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 674804710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 675804710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 676804710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 677804710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 678710960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 679710960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 680710960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 681710960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 682617210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 683617210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 684617210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 685617210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 686523460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 687523460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 688523460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 689523460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 690429710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 691429710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 692429710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 693429710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 694335960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 695335960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 696335960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 697335960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 698242210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 699242210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 700242210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 701242210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 702148460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 703148460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 704148460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 705148460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 706054710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 707054710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 708054710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 709054710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 709960960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 710960960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 711960960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 712960960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 713867210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 714867210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 715867210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 716867210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 717773460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 718773460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 719773460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 720773460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 721679710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 722679710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 723679710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 724679710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 725585960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 726585960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 727585960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 728585960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 729492210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 730492210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 731492210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 732492210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 733398460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 734398460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 735398460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 735398461500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 736398461500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 737304710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 738304710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 739304710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 740304710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 741210960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 742210960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 743210960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 744210960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 745117210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 746117210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 747117210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 748117210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 749023460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 750023460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 751023460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 752023460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 752929710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 753929710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 754929710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 755929710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 756835960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 757835960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 758835960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 759835960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 760742210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 761742210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 762742210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 763742210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 764648460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 765648460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 766648460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 767648460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 768554710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 769554710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 770554710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 771554710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 772460960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 773460960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 774460960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 775460960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 776367210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 777367210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 778367210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 779367210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 780273460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 781273460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 782273460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 783273460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 784179710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 785179710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 786179710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 787179710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 788085960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 789085960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 790085960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 791085960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 791992210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 792992210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 793992210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 794992210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 795898460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 796898460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 797898460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 798898460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 799804710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 800804710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 801804710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 802804710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 803710960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 804710960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 805710960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 806710960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 807617210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 808617210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 809617210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 810617210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 811523460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 812523460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 813523460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 814523460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 815429710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 816429710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 817429710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 818429710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 819335960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 820335960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 821335960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 822335960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 823242210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 824242210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 825242210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 826242210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 827148460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 828148460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 829148460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 830148460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 831054710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 832054710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 833054710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 834054710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 834960960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 835960960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 836960960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 837960960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 838867210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 839867210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 840867210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 840867211500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 841867211500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 842773460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 843773460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 844773460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 845773460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 846679710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 847679710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 848679710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 849679710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 850585960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 851585960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 852585960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 853585960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 854492210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 855492210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 856492210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 857492210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 858398460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 859398460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 860398460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 861398460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 862304710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 863304710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 864304710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 865304710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 866210960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 867210960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 868210960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 869210960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 870117210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 871117210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 872117210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 873117210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 874023460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 875023460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 876023460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 877023460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 877929710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 878929710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 879929710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 880929710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 881835960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 882835960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 883835960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 884835960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 885742210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 886742210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 887742210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 888742210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 889648460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 890648460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 891648460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 892648460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 893554710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 894554710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 895554710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 896554710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 897460960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 898460960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 899460960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 900460960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 901367210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 902367210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 903367210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 904367210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 905273460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 906273460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 907273460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 908273460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 909179710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 910179710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 911179710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 912179710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 913085960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 914085960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 915085960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 916085960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 916992210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 917992210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 918992210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 919992210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 920898460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 921898460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 922898460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 923898460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 924804710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 925804710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 926804710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 927804710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 928710960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 929710960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 930710960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 931710960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 932617210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 933617210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 934617210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 935617210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 936523460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 937523460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 938523460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 939523460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 940429710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 941429710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 942429710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 943429710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 944335960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 945335960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 946335960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 946335961500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 947335961500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 948242210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 949242210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 950242210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 951242210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 952148460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 953148460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 954148460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 955148460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 956054710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 957054710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 958054710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 959054710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 959960960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 960960960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 961960960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 962960960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 963867210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 964867210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 965867210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 966867210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 967773460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 968773460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 969773460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 970773460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 971679710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 972679710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 973679710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 974679710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 975585960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 976585960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 977585960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 978585960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 979492210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 980492210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 981492210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 982492210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 983398460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 984398460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 985398460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 986398460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 987304710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 988304710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 989304710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 990304710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 991210960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 992210960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 993210960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 994210960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 995117210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 996117210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 997117210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 998117210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 999023460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1000023460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1001023460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1002023460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1002929710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1003929710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1004929710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1005929710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1006835960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1007835960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1008835960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1009835960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1010742210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1011742210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1012742210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1013742210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1014648460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1015648460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1016648460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1017648460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1018554710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1019554710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1020554710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1021554710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1022460960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1023460960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1024460960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1025460960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1026367210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1027367210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1028367210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1029367210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1030273460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1031273460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1032273460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1033273460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1034179710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1035179710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1036179710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1037179710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1038085960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1039085960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1040085960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1041085960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1041992210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1042992210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1043992210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1044992210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1045898460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1046898460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1047898460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1048898460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1049804710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1050804710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1051804710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1052804710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1053710960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1054710960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1055710960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1056710960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1057617210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1058617210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1059617210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1060617210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1061523460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1062523460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1063523460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1064523460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1065429710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1066429710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1067429710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1068429710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1069335960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1070335960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1071335960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1072335960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1073242210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1074242210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1075242210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1076242210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1077148460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1078148460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1079148460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1080148460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1081054710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1082054710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1083054710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1084054710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1084960960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1085960960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1086960960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1087960960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1088867210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1089867210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1090867210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1091867210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1092773460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1093773460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1094773460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1095773460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1096679710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1097679710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1098679710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1099679710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1100585960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1101585960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1102585960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1103585960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1104492210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1105492210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1106492210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1107492210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1108398460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1109398460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1110398460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1111398460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1112304710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1113304710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1114304710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1115304710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1116210960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1117210960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1118210960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1119210960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1120117210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1121117210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1122117210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1123117210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1124023460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1125023460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1126023460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1127023460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1127929710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1128929710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1129929710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1130929710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1131835960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1132835960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1133835960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1134835960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1135742210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1136742210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1137742210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1138742210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1139648460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1140648460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1141648460500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1142648460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1143554710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1144554710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1145554710500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1146554710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1147460960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1148460960500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1149460960500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1150460960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1151367210500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1152367210500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1153367210500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1154367210500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1155273460500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1156273460500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1157273460500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1157273461500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1158273461500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1159361690000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1160361690000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1161361690000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1162361690000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1162361693000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1163361693000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1164361693000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1165361693000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1165361696000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1166361696000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1167361696000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1168361696000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1168945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1169945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1170945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1171945335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1172851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1173851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1174851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1175851585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1176757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1177757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1178757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1179757835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1180664085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1181664085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1182664085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1183664085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1184570335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1185570335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1186570335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1187570335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1188476585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1189476585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1190476585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1191476585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1192382835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1193382835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1194382835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1195382835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1196289085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1197289085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1198289085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1199289085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1200195335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1201195335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1202195335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1203195335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1204101585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1205101585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1206101585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1207101585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1208007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1209007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1210007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1211007835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1211914085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1212914085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1213914085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1214914085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1215820335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1216820335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1217820335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1218820335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1219726585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1220726585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1221726585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1222726585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1223632835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1224632835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1225632835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1226632835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1227539085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1228539085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1229539085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1230539085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1231445335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1232445335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1233445335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1234445335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1235351585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1236351585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1237351585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1238351585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1239257835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1240257835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1241257835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1242257835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1243164085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1244164085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1245164085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1246164085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1247070335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1248070335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1249070335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1250070335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1250976585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1251976585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1252976585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1253976585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1254882835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1255882835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1256882835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1257882835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1258789085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1259789085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1260789085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1261789085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1262695335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1263695335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1264695335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1265695335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1266601585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1267601585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1268601585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1269601585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1270507835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1271507835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1272507835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1273507835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1274414085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1275414085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1276414085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1277414085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1278320335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1279320335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1280320335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1281320335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1282226585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1283226585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1284226585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1285226585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1286132835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1287132835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1288132835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1289132835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1290039085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1291039085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1292039085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1293039085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1293945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1294945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1295945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1296945335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1297851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1298851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1299851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1300851585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1301757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1302757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1303757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1304757835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1305664085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1306664085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1307664085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1308664085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1309570335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1310570335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1311570335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1312570335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1313476585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1314476585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1315476585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1316476585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1317382835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1318382835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1319382835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1320382835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1321289085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1322289085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1323289085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1324289085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1325195335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1326195335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1327195335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1328195335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1329101585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1330101585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1331101585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1332101585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1333007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1334007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1335007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1336007835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1336914085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1337914085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1338914085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1339914085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1340820335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1341820335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1342820335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1343820335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1344726585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1345726585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1346726585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1347726585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1348632835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1349632835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1350632835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1351632835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1352539085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1353539085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1354539085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1355539085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1356445335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1357445335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1358445335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1359445335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1360351585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1361351585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1362351585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1363351585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1364257835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1365257835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1366257835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1367257835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1368164085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1369164085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1370164085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1371164085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1372070335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1373070335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1374070335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1375070335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1375976585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1376976585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1377976585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1378976585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1379882835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1380882835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1381882835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1382882835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1383789085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1384789085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1385789085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1386789085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1387695335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1388695335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1389695335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1390695335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1391601585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1392601585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1393601585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1394601585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1395507835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1396507835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1397507835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1398507835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1399414085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1400414085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1401414085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1402414085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1403320335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1404320335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1405320335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1406320335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1407226585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1408226585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1409226585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1410226585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1411132835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1412132835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1413132835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1414132835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1415039085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1416039085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1417039085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1418039085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1418945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1419945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1420945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1421945335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1422851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1423851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1424851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1425851585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1426757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1427757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1428757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1429757835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1430664085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1431664085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1432664085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1433664085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1434570335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1435570335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1436570335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1437570335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1438476585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1439476585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1440476585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1441476585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1442382835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1443382835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1444382835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1445382835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1446289085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1447289085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1448289085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1449289085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1450195335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1451195335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1452195335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1453195335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1454101585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1455101585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1456101585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1457101585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1458007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1459007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1460007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1461007835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1461914085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1462914085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1463914085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1464914085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1465820335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1466820335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1467820335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1468820335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1469726585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1470726585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1471726585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1472726585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1473632835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1474632835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1475632835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1476632835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1477539085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1478539085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1479539085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1480539085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1481445335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1482445335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1483445335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1484445335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1485351585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1486351585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1487351585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1488351585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1489257835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1490257835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1491257835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1492257835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1493164085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1494164085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1495164085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1496164085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1497070335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1498070335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1499070335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1500070335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1500976585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1501976585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1502976585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1503976585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1504882835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1505882835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1506882835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1507882835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1508789085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1509789085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1510789085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1511789085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1512695335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1513695335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1514695335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1515695335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1516601585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1517601585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1518601585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1519601585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1520507835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1521507835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1522507835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1523507835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1524414085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1525414085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1526414085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1527414085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1528320335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1529320335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1530320335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1531320335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1532226585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1533226585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1534226585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1535226585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1536132835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1537132835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1538132835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1539132835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1540039085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1541039085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1542039085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1543039085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1543945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1544945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1545945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1546945335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1547851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1548851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1549851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1550851585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1551757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1552757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1553757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1554757835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1555664085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1556664085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1557664085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1558664085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1559570335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1560570335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1561570335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1562570335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1563476585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1564476585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1565476585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1566476585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1567382835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1568382835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1569382835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1570382835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1571289085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1572289085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1573289085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1574289085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1575195335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1576195335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1577195335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1578195335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1579101585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1580101585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1581101585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1582101585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1583007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1584007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1585007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1586007835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1586914085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1587914085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1588914085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1589914085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1590820335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1591820335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1592820335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1593820335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1594726585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1595726585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1596726585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1597726585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1598632835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1599632835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1600632835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1601632835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1602539085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1603539085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1604539085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1605539085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1606445335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1607445335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1608445335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1609445335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1610351585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1611351585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1612351585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1613351585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1614257835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1615257835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1616257835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1617257835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1618164085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1619164085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1620164085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1621164085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1622070335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1623070335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1624070335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1625070335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1625976585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1626976585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1627976585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1628976585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1629882835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1630882835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1631882835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1632882835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1633789085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1634789085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1635789085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1636789085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1637695335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1638695335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1639695335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1640695335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1641601585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1642601585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1643601585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1644601585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1645507835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1646507835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1647507835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1648507835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1649414085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1650414085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1651414085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1652414085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1653320335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1654320335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1655320335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1656320335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1657226585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1658226585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1659226585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1660226585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1661132835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1662132835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1663132835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1664132835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1665039085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1666039085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1667039085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1668039085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1668945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1669945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1670945335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1671945335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1672851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1673851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1674851585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1675851585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1676757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1677757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1678757835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1679757835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1680664085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1681664085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1682664085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1683664085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1684570335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1685570335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1686570335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1687570335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1688476585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1689476585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1690476585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1691476585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1692382835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1693382835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1694382835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1694382836500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1695382836500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1696289085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1697289085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1698289085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1699289085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1700195335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1701195335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1702195335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1703195335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1704101585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1705101585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1706101585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1706101586500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1707101586500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1708007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1709007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1710007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1711007835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1711914085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1712914085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1713914085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1714914085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1715820335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1716820335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1717820335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1718820335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1719726585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1720726585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1721726585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1722726585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1723632835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1724632835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1725632835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1726632835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1727539085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1728539085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1729539085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1730539085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1731445335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1732445335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1733445335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1734445335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1735351585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1736351585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1737351585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1738351585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1739257835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1740257835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1741257835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1742257835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1743164085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1744164085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1745164085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1746164085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1747070335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1748070335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1749070335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1750070335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1750976585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1751976585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1752976585500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1753976585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1754882835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1755882835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1756882835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1756882836500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1757882836500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1758789085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1759789085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1760789085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1761789085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1762695335500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1763695335500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1764695335500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1765695335500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1766601585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1767601585500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1768601585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1768601586500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1769601586500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1770507835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1771507835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1772507835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1773507835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1774414085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1775414085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1776414085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1777414085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1777414489000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1778414489000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1779414489000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1780414489000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1781250023000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1782250023000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1783250023000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1783250024000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1784250024000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1785156273000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1786156273000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1787156273000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1788156273000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1789062523000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1790062523000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1791062523000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1792062523000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1792968773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1793968773000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1794968773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1794968774000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1795968774000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1796875023000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1797875023000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1798875023000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1799875023000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1800781273000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1801781273000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1802781273000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1803781273000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1804687523000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1805687523000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1806687523000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1806687524000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1807687524000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1808593773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1809593773000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1810593773000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1811593773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1812500023000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1813500023000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1814500023000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1815500023000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1816406273000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1817406273000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1818406273000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1818406274000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1819406274000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1819406280500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1820406280500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1821406280500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1821406281500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1822406281500.  Starting simulation...
+info: Entering event queue @ 1822406288500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1822406293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1823406293000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1824406293000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1825406293000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1826171898000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1827171898000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1828171898000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1829171898000.  Starting simulation...
+info: Entering event queue @ 1829171911500.  Starting simulation...
+info: Entering event queue @ 1829171916500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1829171921000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1830171921000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1831171921000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1831171922000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1832171922000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1833007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1834007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1835007835500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1836007835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1836914085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1837914085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1838914085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1838914086500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1839914086500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1839914091000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1840914091000.  Starting simulation...
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
new file mode 100644
index 0000000..1c485a6
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
@@ -0,0 +1,1554 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  1.841682                       # Number of seconds simulated
+sim_ticks                                1841681669500                       # Number of ticks simulated
+final_tick                               1841681669500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 340900                       # Simulator instruction rate (inst/s)
+host_op_rate                                   340900                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9082220288                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 309920                       # Number of bytes of host memory used
+host_seconds                                   202.78                       # Real time elapsed on the host
+sim_insts                                    69127289                       # Number of instructions simulated
+sim_ops                                      69127289                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst           474944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         19316864                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide        2652288                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           149888                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          2832832                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           295936                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          2722176                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             28444928                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       474944                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       149888                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       295936                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          920768                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7479680                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7479680                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst              7421                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            301826                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide           41442                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2342                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             44263                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              4624                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             42534                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                444452                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          116870                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               116870                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              257886                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            10488709                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1440145                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               81386                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1538177                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst              160688                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             1478093                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15445084                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         257886                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          81386                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst         160688                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             499960                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4061332                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4061332                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4061332                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             257886                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           10488709                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1440145                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              81386                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1538177                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst             160688                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            1478093                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               19506416                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        111038                       # Total number of read requests seen
+system.physmem.writeReqs                        46173                       # Total number of write requests seen
+system.physmem.cpureqs                         157553                       # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead                      7106432                       # Total number of bytes read from memory
+system.physmem.bytesWritten                   2955072                       # Total number of bytes written to memory
+system.physmem.bytesConsumedRd                7106432                       # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr                2955072                       # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ                        7                       # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite                 41                       # Reqs where no action is needed
+system.physmem.perBankRdReqs::0                  7075                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1                  6835                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2                  6921                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3                  6580                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4                  7013                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5                  7160                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6                  7199                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7                  7176                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8                  6821                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9                  6547                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10                 6956                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11                 7030                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12                 7021                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13                 7068                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14                 6779                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15                 6850                       # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0                  3087                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1                  2885                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2                  2926                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3                  2583                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4                  2986                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5                  3014                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6                  3032                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7                  2994                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8                  2761                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9                  2529                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10                 2745                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11                 2938                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12                 3117                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13                 3088                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14                 2763                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15                 2725                       # Track writes on a per bank basis
+system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry                         141                       # Number of times wr buffer was full causing retry
+system.physmem.totGap                    1840669582000                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::6                  111038                       # Categorize read packet sizes
+system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
+system.physmem.writePktSize::0                      0                       # categorize write packet sizes
+system.physmem.writePktSize::1                      0                       # categorize write packet sizes
+system.physmem.writePktSize::2                      0                       # categorize write packet sizes
+system.physmem.writePktSize::3                      0                       # categorize write packet sizes
+system.physmem.writePktSize::4                      0                       # categorize write packet sizes
+system.physmem.writePktSize::5                      0                       # categorize write packet sizes
+system.physmem.writePktSize::6                  46314                       # categorize write packet sizes
+system.physmem.writePktSize::7                      0                       # categorize write packet sizes
+system.physmem.writePktSize::8                      0                       # categorize write packet sizes
+system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::6                   41                       # categorize neither packet sizes
+system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
+system.physmem.rdQLenPdf::0                     82621                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     10884                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      5829                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      1945                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      1200                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       997                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       753                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       844                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       697                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       809                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      664                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      650                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      686                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      750                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      521                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      613                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      369                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      106                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       53                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       38                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0                      1636                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                      1922                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                      1953                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                      1976                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                      2005                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                      2005                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                      2016                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                      2010                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                      2008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                      2007                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                     2004                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                     2002                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                     2001                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                     1999                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                     1997                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1996                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1995                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     1993                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     1992                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     1989                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     1988                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     1988                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     1986                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                      425                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                      116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                       76                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.totQLat                     1659441821                       # Total cycles spent in queuing delays
+system.physmem.totMemAccLat                3549387821                       # Sum of mem lat for all requests
+system.physmem.totBusLat                    444124000                       # Total cycles spent in databus access
+system.physmem.totBankLat                  1445822000                       # Total cycles spent in bank access
+system.physmem.avgQLat                       14945.75                       # Average queueing delay per request
+system.physmem.avgBankLat                    13021.79                       # Average bank access latency per request
+system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
+system.physmem.avgMemAccLat                  31967.54                       # Average memory access latency
+system.physmem.avgRdBW                           3.86                       # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW                           1.60                       # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW                   3.86                       # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW                   1.60                       # Average consumed write bandwidth in MB/s
+system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
+system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
+system.physmem.avgWrQLen                         0.18                       # Average write queue length over time
+system.physmem.readRowHits                     102865                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     29619                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   92.65                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  64.15                       # Row buffer hit rate for writes
+system.physmem.avgGap                     11708274.75                       # Average gap between requests
+system.l2c.replacements                        337510                       # number of replacements
+system.l2c.tagsinuse                     65417.862524                       # Cycle average of tags in use
+system.l2c.total_refs                         2476071                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        402672                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          6.149102                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                     614754000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        54764.758873                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          2313.964866                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          2687.926844                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst           585.029609                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data           664.408286                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.inst          2261.220547                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.data          2140.553499                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.835644                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.035308                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.041015                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.008927                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.010138                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.inst            0.034503                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.data            0.032662                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.998197                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst             513879                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             491618                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             126890                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data              82632                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst             299640                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data             242724                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1757383                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          835771                       # number of Writeback hits
+system.l2c.Writeback_hits::total               835771                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data               1                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2.data               3                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                   7                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu2.data             1                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                 1                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            91841                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            27111                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data            67748                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               186700                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst              513879                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              583459                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              126890                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              109743                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst              299640                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data              310472                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1944083                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             513879                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             583459                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             126890                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             109743                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst             299640                       # number of overall hits
+system.l2c.overall_hits::cpu2.data             310472                       # number of overall hits
+system.l2c.overall_hits::total                1944083                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst             7421                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data           224850                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             2342                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data            23206                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst             4624                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data            25196                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               287639                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data             8                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data            11                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                19                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          77252                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          21108                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data          17439                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             115799                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst              7421                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            302102                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              2342                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             44314                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst              4624                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data             42635                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                403438                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst             7421                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           302102                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             2342                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            44314                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst             4624                       # number of overall misses
+system.l2c.overall_misses::cpu2.data            42635                       # number of overall misses
+system.l2c.overall_misses::total               403438                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu1.inst    130356500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data   1043168500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst    266603500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data   1103490500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     2543619000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data       292500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       292500                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   1001535000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data   1445654500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   2447189500                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    130356500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   2044703500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst    266603500                       # number of demand (read+write) miss cycles
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+system.l2c.UpgradeReq_miss_rate::total       0.730769                       # miss rate for UpgradeReq accesses
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+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
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+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33194.692738                       # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 47198.902756                       # average overall mshr miss latency
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+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.iocache.replacements                     41685                       # number of replacements
+system.iocache.tagsinuse                     1.255489                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
+system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
+system.iocache.warmup_cycle              1693868794000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::tsunami.ide       1.255489                       # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide      0.078468                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.078468                       # Average percentage of cache occupancy
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+system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
+system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53052.011561                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 53052.011561                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 94898.327132                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 94898.327132                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 94724.824134                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 94724.824134                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 94724.824134                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 94724.824134                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         78884                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 9633                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.188934                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks           41512                       # number of writebacks
+system.iocache.writebacks::total                41512                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::tsunami.ide           69                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total           69                       # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses::tsunami.ide        17280                       # number of WriteReq MSHR misses
+system.iocache.WriteReq_mshr_misses::total        17280                       # number of WriteReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide        17349                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        17349                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide        17349                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        17349                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      5589000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total      5589000                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   3043794338                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   3043794338                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   3049383338                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   3049383338                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   3049383338                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   3049383338                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::tsunami.ide     0.398844                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.398844                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::tsunami.ide     0.415864                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total     0.415864                       # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::tsunami.ide     0.415794                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.415794                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::tsunami.ide     0.415794                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.415794                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide        81000                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total        81000                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176145.505671                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 176145.505671                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 175767.095395                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 175767.095395                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 175767.095395                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 175767.095395                       # average overall mshr miss latency
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
+system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
+system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
+system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
+system.cpu0.dtb.fetch_hits                          0                       # ITB hits
+system.cpu0.dtb.fetch_misses                        0                       # ITB misses
+system.cpu0.dtb.fetch_acv                           0                       # ITB acv
+system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu0.dtb.read_hits                     4863195                       # DTB read hits
+system.cpu0.dtb.read_misses                      5912                       # DTB read misses
+system.cpu0.dtb.read_acv                          109                       # DTB read access violations
+system.cpu0.dtb.read_accesses                  426831                       # DTB read accesses
+system.cpu0.dtb.write_hits                    3494205                       # DTB write hits
+system.cpu0.dtb.write_misses                      658                       # DTB write misses
+system.cpu0.dtb.write_acv                          81                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 163149                       # DTB write accesses
+system.cpu0.dtb.data_hits                     8357400                       # DTB hits
+system.cpu0.dtb.data_misses                      6570                       # DTB misses
+system.cpu0.dtb.data_acv                          190                       # DTB access violations
+system.cpu0.dtb.data_accesses                  589980                       # DTB accesses
+system.cpu0.itb.fetch_hits                    2736814                       # ITB hits
+system.cpu0.itb.fetch_misses                     2973                       # ITB misses
+system.cpu0.itb.fetch_acv                          97                       # ITB acv
+system.cpu0.itb.fetch_accesses                2739787                       # ITB accesses
+system.cpu0.itb.read_hits                           0                       # DTB read hits
+system.cpu0.itb.read_misses                         0                       # DTB read misses
+system.cpu0.itb.read_acv                            0                       # DTB read access violations
+system.cpu0.itb.read_accesses                       0                       # DTB read accesses
+system.cpu0.itb.write_hits                          0                       # DTB write hits
+system.cpu0.itb.write_misses                        0                       # DTB write misses
+system.cpu0.itb.write_acv                           0                       # DTB write access violations
+system.cpu0.itb.write_accesses                      0                       # DTB write accesses
+system.cpu0.itb.data_hits                           0                       # DTB hits
+system.cpu0.itb.data_misses                         0                       # DTB misses
+system.cpu0.itb.data_acv                            0                       # DTB access violations
+system.cpu0.itb.data_accesses                       0                       # DTB accesses
+system.cpu0.numCycles                       928581953                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.committedInsts                   32231633                       # Number of instructions committed
+system.cpu0.committedOps                     32231633                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             30115221                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                167520                       # Number of float alu accesses
+system.cpu0.num_func_calls                     807051                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      4228078                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    30115221                       # number of integer instructions
+system.cpu0.num_fp_insts                       167520                       # number of float instructions
+system.cpu0.num_int_register_reads           41941415                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          22024555                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads               86513                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes              88077                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                      8386802                       # number of memory refs
+system.cpu0.num_load_insts                    4883995                       # Number of load instructions
+system.cpu0.num_store_insts                   3502807                       # Number of store instructions
+system.cpu0.num_idle_cycles              214040611553.999786                       # Number of idle cycles
+system.cpu0.num_busy_cycles              -213112029600.999786                       # Number of busy cycles
+system.cpu0.not_idle_fraction             -229.502661                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                  230.502661                       # Percentage of idle cycles
+system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu0.kern.inst.quiesce                    6419                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    211372                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   74800     40.97%     40.97% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    203      0.11%     41.08% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1878      1.03%     42.11% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                 105685     57.89%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              182566                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    73433     49.30%     49.30% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21                     203      0.14%     49.44% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22                    1878      1.26%     50.70% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   73433     49.30%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               148947                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1818611622000     98.75%     98.75% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               39272500      0.00%     98.75% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              363381500      0.02%     98.77% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            22666637000      1.23%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1841680913000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.981725                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.694829                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.815853                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2                         8      2.45%      2.45% # number of syscalls executed
+system.cpu0.kern.syscall::3                        30      9.20%     11.66% # number of syscalls executed
+system.cpu0.kern.syscall::4                         4      1.23%     12.88% # number of syscalls executed
+system.cpu0.kern.syscall::6                        42     12.88%     25.77% # number of syscalls executed
+system.cpu0.kern.syscall::12                        1      0.31%     26.07% # number of syscalls executed
+system.cpu0.kern.syscall::15                        1      0.31%     26.38% # number of syscalls executed
+system.cpu0.kern.syscall::17                       15      4.60%     30.98% # number of syscalls executed
+system.cpu0.kern.syscall::19                       10      3.07%     34.05% # number of syscalls executed
+system.cpu0.kern.syscall::20                        6      1.84%     35.89% # number of syscalls executed
+system.cpu0.kern.syscall::23                        4      1.23%     37.12% # number of syscalls executed
+system.cpu0.kern.syscall::24                        6      1.84%     38.96% # number of syscalls executed
+system.cpu0.kern.syscall::33                       11      3.37%     42.33% # number of syscalls executed
+system.cpu0.kern.syscall::41                        2      0.61%     42.94% # number of syscalls executed
+system.cpu0.kern.syscall::45                       54     16.56%     59.51% # number of syscalls executed
+system.cpu0.kern.syscall::47                        6      1.84%     61.35% # number of syscalls executed
+system.cpu0.kern.syscall::48                       10      3.07%     64.42% # number of syscalls executed
+system.cpu0.kern.syscall::54                       10      3.07%     67.48% # number of syscalls executed
+system.cpu0.kern.syscall::58                        1      0.31%     67.79% # number of syscalls executed
+system.cpu0.kern.syscall::59                        7      2.15%     69.94% # number of syscalls executed
+system.cpu0.kern.syscall::71                       54     16.56%     86.50% # number of syscalls executed
+system.cpu0.kern.syscall::73                        3      0.92%     87.42% # number of syscalls executed
+system.cpu0.kern.syscall::74                       16      4.91%     92.33% # number of syscalls executed
+system.cpu0.kern.syscall::87                        1      0.31%     92.64% # number of syscalls executed
+system.cpu0.kern.syscall::90                        3      0.92%     93.56% # number of syscalls executed
+system.cpu0.kern.syscall::92                        9      2.76%     96.32% # number of syscalls executed
+system.cpu0.kern.syscall::97                        2      0.61%     96.93% # number of syscalls executed
+system.cpu0.kern.syscall::98                        2      0.61%     97.55% # number of syscalls executed
+system.cpu0.kern.syscall::132                       4      1.23%     98.77% # number of syscalls executed
+system.cpu0.kern.syscall::144                       2      0.61%     99.39% # number of syscalls executed
+system.cpu0.kern.syscall::147                       2      0.61%    100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total                   326                       # number of syscalls executed
+system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.00% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.00% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.00% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 4175      2.17%      2.17% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      54      0.03%      2.20% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.00%      2.21% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               175309     91.20%     93.41% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6782      3.53%     96.94% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.94% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     7      0.00%     96.94% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     9      0.00%     96.94% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     96.95% # number of callpals executed
+system.cpu0.kern.callpal::rti                    5175      2.69%     99.64% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 515      0.27%     99.91% # number of callpals executed
+system.cpu0.kern.callpal::imb                     181      0.09%    100.00% # number of callpals executed
+system.cpu0.kern.callpal::total                192221                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             5922                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1736                       # number of protection mode switches
+system.cpu0.kern.mode_switch::idle               2094                       # number of protection mode switches
+system.cpu0.kern.mode_good::kernel               1905                      
+system.cpu0.kern.mode_good::user                 1736                      
+system.cpu0.kern.mode_good::idle                  169                      
+system.cpu0.kern.mode_switch_good::kernel     0.321682                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::idle      0.080707                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::total     0.390689                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel       29776947000      1.62%      1.62% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          2543344500      0.14%      1.75% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::idle        1809360618000     98.25%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.swap_context                    4176                       # number of times the context was actually changed
+system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
+system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
+system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
+system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
+system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
+system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
+system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
+system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
+system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
+system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
+system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
+system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
+system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
+system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
+system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
+system.cpu0.icache.replacements                954146                       # number of replacements
+system.cpu0.icache.tagsinuse               511.198138                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                41733941                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                954657                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                 43.716163                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle           10235539000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst   257.559886                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_blocks::cpu1.inst    79.204756                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_blocks::cpu2.inst   174.433495                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.503047                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::cpu1.inst     0.154697                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::cpu2.inst     0.340690                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.998434                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst     31717072                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst      7719142                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst      2297727                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       41733941                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     31717072                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst      7719142                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst      2297727                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        41733941                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     31717072                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst      7719142                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst      2297727                       # number of overall hits
+system.cpu0.icache.overall_hits::total       41733941                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       521321                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       129232                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       321175                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       971728                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       521321                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       129232                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       321175                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        971728                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       521321                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       129232                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       321175                       # number of overall misses
+system.cpu0.icache.overall_misses::total       971728                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1794278000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4429709988                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   6223987988                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   1794278000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   4429709988                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   6223987988                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   1794278000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   4429709988                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   6223987988                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     32238393                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst      7848374                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst      2618902                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     42705669                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     32238393                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst      7848374                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst      2618902                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     42705669                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     32238393                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst      7848374                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst      2618902                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     42705669                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016171                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.016466                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.122637                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.022754                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016171                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.016466                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.122637                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.022754                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016171                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.016466                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.122637                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.022754                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13884.161818                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13792.200476                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  6405.072189                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13884.161818                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13792.200476                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  6405.072189                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13884.161818                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13792.200476                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  6405.072189                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         1920                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets          179                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              117                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              1                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.410256                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          179                       # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        16896                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        16896                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        16896                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        16896                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        16896                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        16896                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       129232                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       304279                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       433511                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       129232                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       304279                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       433511                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       129232                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       304279                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       433511                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1535814000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3651354490                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   5187168490                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1535814000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3651354490                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   5187168490                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1535814000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3651354490                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   5187168490                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016466                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.116186                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010151                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016466                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.116186                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.010151                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.016466                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.116186                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.010151                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11884.161818                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12000.021329                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11965.482975                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11884.161818                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12000.021329                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11965.482975                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11884.161818                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12000.021329                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11965.482975                       # average overall mshr miss latency
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.replacements               1392176                       # number of replacements
+system.cpu0.dcache.tagsinuse               511.997817                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                13319375                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs               1392688                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                  9.563790                       # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle              10840000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::cpu0.data   250.475263                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_blocks::cpu1.data    85.370425                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_blocks::cpu2.data   176.152129                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.489209                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::cpu1.data     0.166739                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::cpu2.data     0.344047                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.999996                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data      4041121                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      1096850                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      2424578                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        7562549                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3198610                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data       859334                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data      1312800                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5370744                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       116325                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        19408                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        49694                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       185427                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       125372                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data        21487                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data        53741                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       200600                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      7239731                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      1956184                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data      3737378                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        12933293                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      7239731                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      1956184                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data      3737378                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       12933293                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       706861                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       103630                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data       548850                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1359341                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       169104                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data        48220                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data       560755                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       778079                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9607                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2208                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         7000                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        18815                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu2.data            1                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       875965                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       151850                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data      1109605                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2137420                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       875965                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       151850                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data      1109605                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2137420                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2161032000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   9421132500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  11582164500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1417971000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  15685694174                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  17103665174                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     29185500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    103516500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    132702000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data        13000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total        13000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   3579003000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  25106826674                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  28685829674                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   3579003000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  25106826674                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  28685829674                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      4747982                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      1200480                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      2973428                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8921890                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      3367714                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data       907554                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      1873555                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      6148823                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       125932                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        21616                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        56694                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       204242                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       125372                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        21487                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        53742                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       200601                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data      8115696                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      2108034                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      4846983                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     15070713                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data      8115696                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      2108034                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      4846983                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     15070713                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.148876                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.086324                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.184585                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.152360                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.050213                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.053132                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.299300                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.126541                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.076287                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.102147                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.123470                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.092121                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000019                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000005                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.107935                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.072034                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.228927                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.141826                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.107935                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.072034                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.228927                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.141826                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 20853.343626                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17165.222738                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total  8520.426074                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29406.283700                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 27972.455304                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 21981.913371                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13218.070652                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14788.071429                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  7052.989636                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        13000                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23569.331577                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 22626.814654                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 13420.773490                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23569.331577                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22626.814654                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 13420.773490                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       505614                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets          672                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            16873                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    29.965863                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets           96                       # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.dcache.writebacks::writebacks       835771                       # number of writebacks
+system.cpu0.dcache.writebacks::total           835771                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       286220                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       286220                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       475804                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       475804                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         1462                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1462                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       762024                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       762024                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       762024                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       762024                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       103630                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       262630                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       366260                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        48220                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        84951                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       133171                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2208                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         5538                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         7746                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            1                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       151850                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       347581                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       499431                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       151850                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       347581                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       499431                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   1953772000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4295599000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6249371000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1321531000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2301660126                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   3623191126                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     24769500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     70346000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     95115500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        11000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        11000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3275303000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   6597259126                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   9872562126                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3275303000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   6597259126                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   9872562126                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    289521000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    340019500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    629540500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    358537000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    415967500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    774504500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    648058000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    755987000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1404045000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.086324                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.088326                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.041052                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.053132                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.045342                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.021658                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.102147                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.097682                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.037926                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000019                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000005                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.072034                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.071711                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.033139                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.072034                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.071711                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.033139                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18853.343626                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16356.086510                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17062.663135                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27406.283700                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27093.973302                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27207.058038                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11218.070652                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12702.419646                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12279.305448                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        11000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21569.331577                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18980.494118                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19767.619803                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21569.331577                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18980.494118                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19767.619803                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dtb.fetch_hits                          0                       # ITB hits
+system.cpu1.dtb.fetch_misses                        0                       # ITB misses
+system.cpu1.dtb.fetch_acv                           0                       # ITB acv
+system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu1.dtb.read_hits                     1219761                       # DTB read hits
+system.cpu1.dtb.read_misses                      1488                       # DTB read misses
+system.cpu1.dtb.read_acv                           40                       # DTB read access violations
+system.cpu1.dtb.read_accesses                  143779                       # DTB read accesses
+system.cpu1.dtb.write_hits                     929431                       # DTB write hits
+system.cpu1.dtb.write_misses                      201                       # DTB write misses
+system.cpu1.dtb.write_acv                          24                       # DTB write access violations
+system.cpu1.dtb.write_accesses                  59743                       # DTB write accesses
+system.cpu1.dtb.data_hits                     2149192                       # DTB hits
+system.cpu1.dtb.data_misses                      1689                       # DTB misses
+system.cpu1.dtb.data_acv                           64                       # DTB access violations
+system.cpu1.dtb.data_accesses                  203522                       # DTB accesses
+system.cpu1.itb.fetch_hits                     873235                       # ITB hits
+system.cpu1.itb.fetch_misses                      756                       # ITB misses
+system.cpu1.itb.fetch_acv                          43                       # ITB acv
+system.cpu1.itb.fetch_accesses                 873991                       # ITB accesses
+system.cpu1.itb.read_hits                           0                       # DTB read hits
+system.cpu1.itb.read_misses                         0                       # DTB read misses
+system.cpu1.itb.read_acv                            0                       # DTB read access violations
+system.cpu1.itb.read_accesses                       0                       # DTB read accesses
+system.cpu1.itb.write_hits                          0                       # DTB write hits
+system.cpu1.itb.write_misses                        0                       # DTB write misses
+system.cpu1.itb.write_acv                           0                       # DTB write access violations
+system.cpu1.itb.write_accesses                      0                       # DTB write accesses
+system.cpu1.itb.data_hits                           0                       # DTB hits
+system.cpu1.itb.data_misses                         0                       # DTB misses
+system.cpu1.itb.data_acv                            0                       # DTB access violations
+system.cpu1.itb.data_accesses                       0                       # DTB accesses
+system.cpu1.numCycles                       953535739                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.committedInsts                    7846620                       # Number of instructions committed
+system.cpu1.committedOps                      7846620                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses              7299077                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                 45739                       # Number of float alu accesses
+system.cpu1.num_func_calls                     212215                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts       957639                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                     7299077                       # number of integer instructions
+system.cpu1.num_fp_insts                        45739                       # number of float instructions
+system.cpu1.num_int_register_reads           10142741                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           5309758                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads               24689                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              24953                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                      2156913                       # number of memory refs
+system.cpu1.num_load_insts                    1225031                       # Number of load instructions
+system.cpu1.num_store_insts                    931882                       # Number of store instructions
+system.cpu1.num_idle_cycles              -1658749274.077502                       # Number of idle cycles
+system.cpu1.num_busy_cycles              2612285013.077502                       # Number of busy cycles
+system.cpu1.not_idle_fraction                2.739577                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                   -1.739577                       # Percentage of idle cycles
+system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                         0                       # number of hwrei instructions executed
+system.cpu1.kern.mode_switch::kernel                0                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                  0                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle                  0                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                  0                      
+system.cpu1.kern.mode_good::user                    0                      
+system.cpu1.kern.mode_good::idle                    0                      
+system.cpu1.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::user           nan                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total          nan                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel                 0                       # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                       0                       # number of times the context was actually changed
+system.cpu2.dtb.fetch_hits                          0                       # ITB hits
+system.cpu2.dtb.fetch_misses                        0                       # ITB misses
+system.cpu2.dtb.fetch_acv                           0                       # ITB acv
+system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu2.dtb.read_hits                     3234016                       # DTB read hits
+system.cpu2.dtb.read_misses                     12170                       # DTB read misses
+system.cpu2.dtb.read_acv                          136                       # DTB read access violations
+system.cpu2.dtb.read_accesses                  218383                       # DTB read accesses
+system.cpu2.dtb.write_hits                    2000862                       # DTB write hits
+system.cpu2.dtb.write_misses                     2630                       # DTB write misses
+system.cpu2.dtb.write_acv                         139                       # DTB write access violations
+system.cpu2.dtb.write_accesses                  81465                       # DTB write accesses
+system.cpu2.dtb.data_hits                     5234878                       # DTB hits
+system.cpu2.dtb.data_misses                     14800                       # DTB misses
+system.cpu2.dtb.data_acv                          275                       # DTB access violations
+system.cpu2.dtb.data_accesses                  299848                       # DTB accesses
+system.cpu2.itb.fetch_hits                     374542                       # ITB hits
+system.cpu2.itb.fetch_misses                     5731                       # ITB misses
+system.cpu2.itb.fetch_acv                         284                       # ITB acv
+system.cpu2.itb.fetch_accesses                 380273                       # ITB accesses
+system.cpu2.itb.read_hits                           0                       # DTB read hits
+system.cpu2.itb.read_misses                         0                       # DTB read misses
+system.cpu2.itb.read_acv                            0                       # DTB read access violations
+system.cpu2.itb.read_accesses                       0                       # DTB read accesses
+system.cpu2.itb.write_hits                          0                       # DTB write hits
+system.cpu2.itb.write_misses                        0                       # DTB write misses
+system.cpu2.itb.write_acv                           0                       # DTB write access violations
+system.cpu2.itb.write_accesses                      0                       # DTB write accesses
+system.cpu2.itb.data_hits                           0                       # DTB hits
+system.cpu2.itb.data_misses                         0                       # DTB misses
+system.cpu2.itb.data_acv                            0                       # DTB access violations
+system.cpu2.itb.data_accesses                       0                       # DTB accesses
+system.cpu2.numCycles                        30548805                       # number of cpu cycles simulated
+system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu2.BPredUnit.lookups                 8364028                       # Number of BP lookups
+system.cpu2.BPredUnit.condPredicted           7669410                       # Number of conditional branches predicted
+system.cpu2.BPredUnit.condIncorrect            129868                       # Number of conditional branches incorrect
+system.cpu2.BPredUnit.BTBLookups              6711241                       # Number of BTB lookups
+system.cpu2.BPredUnit.BTBHits                 5709819                       # Number of BTB hits
+system.cpu2.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu2.BPredUnit.usedRAS                  287796                       # Number of times the RAS was used to get a target.
+system.cpu2.BPredUnit.RASInCorrect              15290                       # Number of incorrect RAS predictions.
+system.cpu2.fetch.icacheStallCycles           8565342                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                      34820498                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                    8364028                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches           5997615                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                      8085140                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                 623390                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.BlockedCycles               9684769                       # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles               10169                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             1946                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles        65267                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles        78430                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          219                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  2618903                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes                90402                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples          26897224                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.294576                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.310232                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                18812084     69.94%     69.94% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  275091      1.02%     70.96% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                  443313      1.65%     72.61% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                 4200168     15.62%     88.23% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  736557      2.74%     90.97% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  167312      0.62%     91.59% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  197037      0.73%     92.32% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  432029      1.61%     93.93% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                 1633633      6.07%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::total            26897224                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.273792                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       1.139832                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                 8682356                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles              9793254                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                  7488405                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles               293704                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                393556                       # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved              170875                       # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred                13042                       # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts              34420320                       # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts                40663                       # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles                393556                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                 9037496                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                2819097                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       5808677                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                  7346220                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles              1246237                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts              33260279                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                 2326                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents                233903                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents               407997                       # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RenamedOperands           22331754                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups             41424509                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups        41259136                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups           165373                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps             20496437                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                 1835317                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            510420                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts         61593                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                  3691952                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             3399315                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            2093436                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           371907                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          254715                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                  30727225                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             632539                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                 30272118                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            35753                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        2189784                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined      1100567                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved        445757                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples     26897224                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.125474                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.564893                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           15350394     57.07%     57.07% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            3115885     11.58%     68.65% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            1557090      5.79%     74.44% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            5021564     18.67%     93.11% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4             911830      3.39%     96.50% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5             491728      1.83%     98.33% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6             288005      1.07%     99.40% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             142453      0.53%     99.93% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8              18275      0.07%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total       26897224                       # Number of insts issued each cycle
+system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                  35285     14.01%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     14.01% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                113269     44.96%     58.96% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite               103382     41.04%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
+system.cpu2.iq.FU_type_0::No_OpClass             2456      0.01%      0.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu             24555706     81.12%     81.12% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               20320      0.07%     81.19% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     81.19% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd               8506      0.03%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv               1228      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             3366886     11.12%     92.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            2024055      6.69%     99.03% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess            292961      0.97%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::total              30272118                       # Type of FU issued
+system.cpu2.iq.rate                          0.990943                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                     251936                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.008322                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads          87492046                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes         33437480                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses     29866501                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads             237103                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes            115982                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses       112325                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses              30398156                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                 123442                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          190063                       # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
+system.cpu2.iew.lsq.thread0.squashedLoads       422258                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses          952                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         4004                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       162752                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
+system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu2.iew.lsq.thread0.rescheduledLoads         4980                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked        23112                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
+system.cpu2.iew.iewSquashCycles                393556                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                2038103                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles               212197                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts           32647760                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts           228888                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              3399315                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             2093436                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            561709                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                150503                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents                 2400                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          4004                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect         66845                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       130356                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              197201                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts             30107405                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              3254707                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           164713                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
+system.cpu2.iew.exec_nop                      1287996                       # number of nop insts executed
+system.cpu2.iew.exec_refs                     5262746                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                 6765344                       # Number of branches executed
+system.cpu2.iew.exec_stores                   2008039                       # Number of stores executed
+system.cpu2.iew.exec_rate                    0.985551                       # Inst execution rate
+system.cpu2.iew.wb_sent                      30012235                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                     29978826                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                 17295143                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                 20538847                       # num instructions consuming a value
+system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
+system.cpu2.iew.wb_rate                      0.981342                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.842070                       # average fanout of values written-back
+system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu2.commit.commitSquashedInsts        2374409                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         186782                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           183048                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples     26503668                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.140514                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.850633                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     16405527     61.90%     61.90% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      2337415      8.82%     70.72% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1218938      4.60%     75.32% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3      4753611     17.94%     93.25% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       502619      1.90%     95.15% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       186793      0.70%     95.85% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       180491      0.68%     96.54% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7       181897      0.69%     97.22% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8       736377      2.78%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::total     26503668                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts            30227806                       # Number of instructions committed
+system.cpu2.commit.committedOps              30227806                       # Number of ops (including micro ops) committed
+system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
+system.cpu2.commit.refs                       4907741                       # Number of memory references committed
+system.cpu2.commit.loads                      2977057                       # Number of loads committed
+system.cpu2.commit.membars                      65125                       # Number of memory barriers committed
+system.cpu2.commit.branches                   6615814                       # Number of branches committed
+system.cpu2.commit.fp_insts                    111064                       # Number of committed floating point instructions.
+system.cpu2.commit.int_insts                 28762873                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              231817                       # Number of function calls committed.
+system.cpu2.commit.bw_lim_events               736377                       # number cycles where commit BW limit reached
+system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
+system.cpu2.rob.rob_reads                    58294713                       # The number of ROB reads
+system.cpu2.rob.rob_writes                   65597739                       # The number of ROB writes
+system.cpu2.timesIdled                         244101                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                        3651581                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  1745276463                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                   29049036                       # Number of Instructions Simulated
+system.cpu2.committedOps                     29049036                       # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total             29049036                       # Number of Instructions Simulated
+system.cpu2.cpi                              1.051629                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.051629                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.950906                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.950906                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                39585060                       # number of integer regfile reads
+system.cpu2.int_regfile_writes               21198431                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    68487                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   68830                       # number of floating regfile writes
+system.cpu2.misc_regfile_reads                4557721                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                264115                       # number of misc regfile writes
+system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
+system.cpu2.kern.inst.hwrei                         0                       # number of hwrei instructions executed
+system.cpu2.kern.mode_switch::kernel                0                       # number of protection mode switches
+system.cpu2.kern.mode_switch::user                  0                       # number of protection mode switches
+system.cpu2.kern.mode_switch::idle                  0                       # number of protection mode switches
+system.cpu2.kern.mode_good::kernel                  0                      
+system.cpu2.kern.mode_good::user                    0                      
+system.cpu2.kern.mode_good::idle                    0                      
+system.cpu2.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
+system.cpu2.kern.mode_switch_good::user           nan                       # fraction of useful protection mode switches
+system.cpu2.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
+system.cpu2.kern.mode_switch_good::total          nan                       # fraction of useful protection mode switches
+system.cpu2.kern.mode_ticks::kernel                 0                       # number of ticks spent at the given mode
+system.cpu2.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
+system.cpu2.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
+system.cpu2.kern.swap_context                       0                       # number of times the context was actually changed
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal
new file mode 100644
index 0000000..8a879f5
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal
Binary files differ
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
new file mode 100644
index 0000000..fbde95c
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
@@ -0,0 +1,1204 @@
+[root]
+type=Root
+children=system
+full_system=true
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 cpu0 cpu1 cpu2 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
+atags_addr=256
+boot_loader=/arm/scratch/sysexplr/dist/binaries/boot.arm
+boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+clock=1000
+dtb_filename=
+early_kernel_symbols=false
+enable_context_switch_stats_dump=false
+flags_addr=268435504
+gic_cpu_addr=520093952
+init_param=0
+kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+load_addr_mask=268435455
+machine_type=RealView_PBX
+mem_mode=atomic
+mem_ranges=0:134217727
+memories=system.physmem system.realview.nvmem
+multi_proc=true
+num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
+readfile=tests/halt.sh
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.bridge]
+type=Bridge
+clock=1000
+delay=50000
+ranges=268435456:520093695 1073741824:1610612735
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+image_file=/arm/scratch/sysexplr/dist/disks/linux-arm-ael.img
+read_only=true
+
+[system.cpu0]
+type=AtomicSimpleCPU
+children=dcache dtb icache interrupts isa itb tracer
+checker=Null
+clock=500
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu0.dtb
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+switched_out=false
+system=system
+tracer=system.cpu0.tracer
+width=1
+workload=
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=4
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+size=32768
+system=system
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu0.dtb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu0.dtb.walker
+
+[system.cpu0.dtb.walker]
+type=ArmTableWalker
+clock=500
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[3]
+
+[system.cpu0.icache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=1
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+size=32768
+system=system
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.interrupts]
+type=ArmInterrupts
+
+[system.cpu0.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
+[system.cpu0.itb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu0.itb.walker
+
+[system.cpu0.itb.walker]
+type=ArmTableWalker
+clock=500
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[2]
+
+[system.cpu0.tracer]
+type=ExeTracer
+
+[system.cpu1]
+type=TimingSimpleCPU
+children=dtb interrupts isa itb tracer
+checker=Null
+clock=500
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu1.dtb
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+switched_out=true
+system=system
+tracer=system.cpu1.tracer
+workload=
+
+[system.cpu1.dtb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu1.dtb.walker
+
+[system.cpu1.dtb.walker]
+type=ArmTableWalker
+clock=500
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.interrupts]
+type=ArmInterrupts
+
+[system.cpu1.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
+[system.cpu1.itb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu1.itb.walker
+
+[system.cpu1.itb.walker]
+type=ArmTableWalker
+clock=500
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.tracer]
+type=ExeTracer
+
+[system.cpu2]
+type=DerivO3CPU
+children=dtb fuPool interrupts isa itb tracer
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+dispatchWidth=8
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu2.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu2.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+interrupts=system.cpu2.interrupts
+isa=system.cpu2.isa
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu2.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+needsTSO=false
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+predType=tournament
+profile=0
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+switched_out=true
+system=system
+tracer=system.cpu2.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=
+
+[system.cpu2.dtb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu2.dtb.walker
+
+[system.cpu2.dtb.walker]
+type=ArmTableWalker
+clock=500
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu2.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
+
+[system.cpu2.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu2.fuPool.FUList0.opList
+
+[system.cpu2.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu2.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
+
+[system.cpu2.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu2.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu2.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2
+
+[system.cpu2.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu2.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu2.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu2.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
+
+[system.cpu2.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu2.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu2.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu2.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu2.fuPool.FUList4.opList
+
+[system.cpu2.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu2.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
+
+[system.cpu2.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu2.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu2.fuPool.FUList6.opList
+
+[system.cpu2.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu2.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
+
+[system.cpu2.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu2.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu2.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu2.fuPool.FUList8.opList
+
+[system.cpu2.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu2.interrupts]
+type=ArmInterrupts
+
+[system.cpu2.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
+[system.cpu2.itb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu2.itb.walker
+
+[system.cpu2.itb.walker]
+type=ArmTableWalker
+clock=500
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu2.tracer]
+type=ExeTracer
+
+[system.intrctrl]
+type=IntrControl
+sys=system
+
+[system.iobus]
+type=NoncoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=8
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
+
+[system.iocache]
+type=BaseCache
+addr_ranges=0:134217727
+assoc=8
+block_size=64
+clock=1000
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+size=1024
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[25]
+mem_side=system.membus.slave[2]
+
+[system.l2c]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=8
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+size=4194304
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.membus]
+type=CoherentBus
+children=badaddr_responder
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=8
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
+slave=system.system_port system.l2c.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
+conf_table_reported=true
+in_addr_map=true
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
+null=false
+page_policy=open
+range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
+zero=false
+port=system.membus.master[2]
+
+[system.realview]
+type=RealView
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+intrctrl=system.intrctrl
+max_mem_size=268435456
+mem_start_addr=0
+pci_cfg_base=0
+system=system
+
+[system.realview.a9scu]
+type=A9SCU
+clock=1000
+pio_addr=520093696
+pio_latency=100000
+system=system
+pio=system.membus.master[5]
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268451840
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=402653184
+BAR0LegacyIO=true
+BAR0Size=16
+BAR1=402653440
+BAR1LegacyIO=true
+BAR1Size=1
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=0
+MinimumGrant=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clock=1000
+config_latency=20000
+ctrl_offset=2
+disks=system.cf0
+io_shift=1
+pci_bus=2
+pci_dev=7
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[8]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[7]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clock=1000
+gic=system.realview.gic
+int_num=55
+pio_addr=268566528
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.dmac_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268632064
+pio_latency=100000
+system=system
+pio=system.iobus.master[9]
+
+[system.realview.flash_fake]
+type=IsaFake
+clock=1000
+fake_mem=true
+pio_addr=1073741824
+pio_latency=100000
+pio_size=536870912
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[24]
+
+[system.realview.gic]
+type=Gic
+clock=1000
+cpu_addr=520093952
+cpu_pio_delay=10000
+dist_addr=520097792
+dist_pio_delay=10000
+int_latency=10000
+it_lines=128
+platform=system.realview
+system=system
+pio=system.membus.master[3]
+
+[system.realview.gpio0_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268513280
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.gpio1_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268517376
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.realview.gpio2_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268521472
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clock=1000
+gic=system.realview.gic
+int_delay=1000000
+int_num=52
+is_mouse=false
+pio_addr=268460032
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[5]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clock=1000
+gic=system.realview.gic
+int_delay=1000000
+int_num=53
+is_mouse=true
+pio_addr=268464128
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=520101888
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.membus.master[4]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clock=1000
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=520095232
+pio_latency=100000
+system=system
+pio=system.membus.master[6]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268455936
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clock=1000
+conf_table_reported=false
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2214592511
+zero=true
+port=system.membus.master[1]
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clock=1000
+idreg=0
+pio_addr=268435456
+pio_latency=100000
+proc_id0=201326592
+proc_id1=201327138
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clock=1000
+gic=system.realview.gic
+int_delay=100000
+int_num=42
+pio_addr=268529664
+pio_latency=100000
+system=system
+time=Thu Jan  1 00:00:00 2009
+pio=system.iobus.master[23]
+
+[system.realview.sci_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268492800
+pio_latency=100000
+system=system
+pio=system.iobus.master[20]
+
+[system.realview.smc_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=269357056
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=true
+pio_addr=268439552
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.ssp_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268488704
+pio_latency=100000
+system=system
+pio=system.iobus.master[19]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clock=1000
+clock0=1000000
+clock1=1000000
+gic=system.realview.gic
+int_num0=36
+int_num1=36
+pio_addr=268505088
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clock=1000
+clock0=1000000
+clock1=1000000
+gic=system.realview.gic
+int_num0=37
+int_num1=37
+pio_addr=268509184
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clock=1000
+end_on_eot=false
+gic=system.realview.gic
+int_delay=100000
+int_num=44
+pio_addr=268472320
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268476416
+pio_latency=100000
+system=system
+pio=system.iobus.master[10]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268480512
+pio_latency=100000
+system=system
+pio=system.iobus.master[11]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268484608
+pio_latency=100000
+system=system
+pio=system.iobus.master[12]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268500992
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=CoherentBus
+block_size=64
+clock=500
+header_cycles=1
+use_default_range=false
+width=8
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
+
+[system.vncserver]
+type=VncServer
+frame_capture=false
+number=0
+port=5900
+
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr
new file mode 100755
index 0000000..d34d935
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr
@@ -0,0 +1,28 @@
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: The clidr register always reports 0 caches.
+warn: clidr LoUIS field of 0b001 to match current ARM implementations.
+warn: The csselr register isn't implemented.
+warn: The ccsidr register isn't implemented and always reads as 0.
+warn: 	instruction 'mcr bpiallis' unimplemented
+warn: 	instruction 'mcr icialluis' unimplemented
+hack: be nice to actually delete the event here
+warn: 	instruction 'mcr dccimvac' unimplemented
+warn: 	instruction 'mcr dccmvau' unimplemented
+warn: 	instruction 'mcr icimvau' unimplemented
+warn: LCD dual screen mode not supported
+warn: 	instruction 'mcr icialluis' unimplemented
+warn: 	instruction 'mcr bpiallis' unimplemented
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout
new file mode 100755
index 0000000..f005229
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout
@@ -0,0 +1,4106 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Dec 11 2012 16:28:23
+gem5 started Dec 11 2012 16:28:35
+gem5 executing on e103721-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: Using bootloader at address 0x80000000
+info: Entering event queue @ 0.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1000000000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2000000000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2000001000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3000001000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3000008500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4000008500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 5000008500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5000009000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 6000009000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 6000041500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 7000041500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 8000041500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 8000042500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 9000042500.  Starting simulation...
+info: Entering event queue @ 9000050500.  Starting simulation...
+info: Entering event queue @ 9000061000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 9000065500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 10000065500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 11000065500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 11000066500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 12000066500.  Starting simulation...
+info: Entering event queue @ 12000080000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 12000084500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 13000084500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 14000084500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 14000088000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 15000088000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 15000331000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 16000331000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 17000331000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 17000332000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 18000332000.  Starting simulation...
+info: Entering event queue @ 26175972000.  Starting simulation...
+info: Entering event queue @ 26175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 26175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 27175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 28175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 29175983500.  Starting simulation...
+info: Entering event queue @ 36175972000.  Starting simulation...
+info: Entering event queue @ 36175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 36175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 37175983500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 37175984000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 38175984000.  Starting simulation...
+info: Entering event queue @ 38175999500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 38176040500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 39176040500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 39176113500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 40176113500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 41176113500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 41176114500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 42176114500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 42176477500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 43176477500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 44176477500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 44176479000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 45176479000.  Starting simulation...
+info: Entering event queue @ 45176488000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 45176492500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 46176492500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 47176492500.  Starting simulation...
+info: Entering event queue @ 47176497000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 47176499500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 48176499500.  Starting simulation...
+info: Entering event queue @ 48176506500.  Starting simulation...
+info: Entering event queue @ 48176516500.  Starting simulation...
+info: Entering event queue @ 48176521000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 48176522000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 49176522000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 50176522000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 51176522000.  Starting simulation...
+info: Entering event queue @ 56175972000.  Starting simulation...
+info: Entering event queue @ 56175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 56175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 57175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 58175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 59175983500.  Starting simulation...
+info: Entering event queue @ 66175972000.  Starting simulation...
+info: Entering event queue @ 66175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 66175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 67175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 68175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 69175983500.  Starting simulation...
+info: Entering event queue @ 76175972000.  Starting simulation...
+info: Entering event queue @ 76175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 76175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 77175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 78175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 79175983500.  Starting simulation...
+info: Entering event queue @ 86175972000.  Starting simulation...
+info: Entering event queue @ 86175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 86175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 87175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 88175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 89175983500.  Starting simulation...
+info: Entering event queue @ 96175973000.  Starting simulation...
+info: Entering event queue @ 96175982000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 96175986500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 97175986500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 98175986500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 99175986500.  Starting simulation...
+info: Entering event queue @ 106175972000.  Starting simulation...
+info: Entering event queue @ 106175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 106175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 107175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 108175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 109175979000.  Starting simulation...
+info: Entering event queue @ 116175972000.  Starting simulation...
+info: Entering event queue @ 116175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 116175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 117175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 118175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 119175979000.  Starting simulation...
+info: Entering event queue @ 126175972000.  Starting simulation...
+info: Entering event queue @ 126175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 126175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 127175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 128175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 129175979000.  Starting simulation...
+info: Entering event queue @ 136175972000.  Starting simulation...
+info: Entering event queue @ 136175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 136175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 137175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 138175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 139175979000.  Starting simulation...
+info: Entering event queue @ 146175972000.  Starting simulation...
+info: Entering event queue @ 146175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 146175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 147175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 148175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 149175983500.  Starting simulation...
+info: Entering event queue @ 156175972000.  Starting simulation...
+info: Entering event queue @ 156175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 156175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 157175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 158175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 159175983500.  Starting simulation...
+info: Entering event queue @ 166175972000.  Starting simulation...
+info: Entering event queue @ 166175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 166175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 167175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 168175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 169175979000.  Starting simulation...
+info: Entering event queue @ 176175972000.  Starting simulation...
+info: Entering event queue @ 176175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 176175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 177175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 178175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 179175979000.  Starting simulation...
+info: Entering event queue @ 186175972000.  Starting simulation...
+info: Entering event queue @ 186175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 186175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 187175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 188175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 189175979000.  Starting simulation...
+info: Entering event queue @ 196175972000.  Starting simulation...
+info: Entering event queue @ 196175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 196175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 197175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 198175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 199175979000.  Starting simulation...
+info: Entering event queue @ 206175972000.  Starting simulation...
+info: Entering event queue @ 206175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 206175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 207175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 208175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 209175983500.  Starting simulation...
+info: Entering event queue @ 216175972000.  Starting simulation...
+info: Entering event queue @ 216175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 216175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 217175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 218175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 219175983500.  Starting simulation...
+info: Entering event queue @ 226175972000.  Starting simulation...
+info: Entering event queue @ 226175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 226175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 227175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 228175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 229175983500.  Starting simulation...
+info: Entering event queue @ 236175972000.  Starting simulation...
+info: Entering event queue @ 236175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 236175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 237175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 238175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 239175983500.  Starting simulation...
+info: Entering event queue @ 246175972000.  Starting simulation...
+info: Entering event queue @ 246175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 246175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 247175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 248175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 249175983500.  Starting simulation...
+info: Entering event queue @ 256175973000.  Starting simulation...
+info: Entering event queue @ 256175984500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 256175989000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 257175989000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 258175989000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 259175989000.  Starting simulation...
+info: Entering event queue @ 266175972000.  Starting simulation...
+info: Entering event queue @ 266979463000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 266979465000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 267979465000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 268979465000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 269979465000.  Starting simulation...
+info: Entering event queue @ 276175972000.  Starting simulation...
+info: Entering event queue @ 276175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 276175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 277175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 278175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 279175979000.  Starting simulation...
+info: Entering event queue @ 286175972000.  Starting simulation...
+info: Entering event queue @ 286175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 286175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 287175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 288175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 289175979000.  Starting simulation...
+info: Entering event queue @ 296175972000.  Starting simulation...
+info: Entering event queue @ 296175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 296175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 297175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 298175979000.  Starting simulation...
+info: Entering event queue @ 299715607000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 299715609000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 300715609000.  Starting simulation...
+info: Entering event queue @ 306175972000.  Starting simulation...
+info: Entering event queue @ 306175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 306175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 307175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 308175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 309175983500.  Starting simulation...
+info: Entering event queue @ 316175972000.  Starting simulation...
+info: Entering event queue @ 316175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 316175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 317175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 318175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 319175983500.  Starting simulation...
+info: Entering event queue @ 326175972000.  Starting simulation...
+info: Entering event queue @ 326175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 326175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 327175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 328175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 329175979000.  Starting simulation...
+info: Entering event queue @ 336175972000.  Starting simulation...
+info: Entering event queue @ 336175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 336175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 337175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 338175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 339175979000.  Starting simulation...
+info: Entering event queue @ 346175972000.  Starting simulation...
+info: Entering event queue @ 346175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 346175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 347175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 348175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 349175979000.  Starting simulation...
+info: Entering event queue @ 356175972000.  Starting simulation...
+info: Entering event queue @ 356175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 356175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 357175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 358175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 359175979000.  Starting simulation...
+info: Entering event queue @ 366175972000.  Starting simulation...
+info: Entering event queue @ 366175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 366175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 367175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 368175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 369175983500.  Starting simulation...
+info: Entering event queue @ 376175972000.  Starting simulation...
+info: Entering event queue @ 376175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 376175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 377175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 378175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 379175983500.  Starting simulation...
+info: Entering event queue @ 386175973000.  Starting simulation...
+info: Entering event queue @ 386175980000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 386175984500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 387175984500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 388175984500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 389175984500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 396175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 397175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 398175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 399175973000.  Starting simulation...
+info: Entering event queue @ 406175973000.  Starting simulation...
+info: Entering event queue @ 406175981500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 406175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 407175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 408175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 409175986000.  Starting simulation...
+info: Entering event queue @ 416175972000.  Starting simulation...
+info: Entering event queue @ 416175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 416175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 417175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 418175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 419175983500.  Starting simulation...
+info: Entering event queue @ 426175972000.  Starting simulation...
+info: Entering event queue @ 426175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 426175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 427175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 428175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 429175979000.  Starting simulation...
+info: Entering event queue @ 436175972000.  Starting simulation...
+info: Entering event queue @ 436175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 436175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 437175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 438175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 439175979000.  Starting simulation...
+info: Entering event queue @ 446175972000.  Starting simulation...
+info: Entering event queue @ 446175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 446175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 447175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 448175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 449175979000.  Starting simulation...
+info: Entering event queue @ 456175972000.  Starting simulation...
+info: Entering event queue @ 456175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 456175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 457175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 458175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 459175979000.  Starting simulation...
+info: Entering event queue @ 466175972000.  Starting simulation...
+info: Entering event queue @ 466175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 466175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 467175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 468175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 469175983500.  Starting simulation...
+info: Entering event queue @ 476175972000.  Starting simulation...
+info: Entering event queue @ 476175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 476175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 477175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 478175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 479175983500.  Starting simulation...
+info: Entering event queue @ 486175972000.  Starting simulation...
+info: Entering event queue @ 486175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 486175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 487175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 488175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 489175979000.  Starting simulation...
+info: Entering event queue @ 496175972000.  Starting simulation...
+info: Entering event queue @ 496175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 496175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 497175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 498175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 499175979000.  Starting simulation...
+info: Entering event queue @ 506175972000.  Starting simulation...
+info: Entering event queue @ 506175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 506175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 507175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 508175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 509175979000.  Starting simulation...
+info: Entering event queue @ 516175972000.  Starting simulation...
+info: Entering event queue @ 516175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 516175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 517175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 518175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 519175979000.  Starting simulation...
+info: Entering event queue @ 526175972000.  Starting simulation...
+info: Entering event queue @ 526175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 526175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 527175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 528175983500.  Starting simulation...
+info: Entering event queue @ 528869056000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 528869058000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 529869058000.  Starting simulation...
+info: Entering event queue @ 536175972000.  Starting simulation...
+info: Entering event queue @ 536175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 536175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 537175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 538175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 539175983500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 546175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 547175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 548175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 549175973000.  Starting simulation...
+info: Entering event queue @ 556175973000.  Starting simulation...
+info: Entering event queue @ 556175985000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 556175989500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 557175989500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 558175989500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 559175989500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 566175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 567175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 568175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 569175973000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 576175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 577175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 578175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 579175973000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 586175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 587175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 588175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 589175973000.  Starting simulation...
+info: Entering event queue @ 596175973000.  Starting simulation...
+info: Entering event queue @ 596175981500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 596175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 597175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 598175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 599175986000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 606175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 607175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 608175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 609175973000.  Starting simulation...
+info: Entering event queue @ 616175972000.  Starting simulation...
+info: Entering event queue @ 616175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 616175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 617175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 618175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 619175979000.  Starting simulation...
+info: Entering event queue @ 626175972000.  Starting simulation...
+info: Entering event queue @ 627078091000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 627078093000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 628078093000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 629078093000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 630078093000.  Starting simulation...
+info: Entering event queue @ 636175972000.  Starting simulation...
+info: Entering event queue @ 636175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 636175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 637175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 638175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 639175979000.  Starting simulation...
+info: Entering event queue @ 646175972000.  Starting simulation...
+info: Entering event queue @ 646175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 646175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 647175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 648175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 649175979000.  Starting simulation...
+info: Entering event queue @ 656175972000.  Starting simulation...
+info: Entering event queue @ 656175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 656175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 657175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 658175983500.  Starting simulation...
+info: Entering event queue @ 659814382000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 659814384000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 660814384000.  Starting simulation...
+info: Entering event queue @ 666175972000.  Starting simulation...
+info: Entering event queue @ 666175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 666175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 667175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 668175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 669175983500.  Starting simulation...
+info: Entering event queue @ 676175972000.  Starting simulation...
+info: Entering event queue @ 676175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 676175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 677175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 678175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 679175979000.  Starting simulation...
+info: Entering event queue @ 686175972000.  Starting simulation...
+info: Entering event queue @ 686175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 686175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 687175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 688175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 689175979000.  Starting simulation...
+info: Entering event queue @ 696175972000.  Starting simulation...
+info: Entering event queue @ 696175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 696175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 697175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 698175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 699175979000.  Starting simulation...
+info: Entering event queue @ 706175972000.  Starting simulation...
+info: Entering event queue @ 706175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 706175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 707175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 708175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 709175979000.  Starting simulation...
+info: Entering event queue @ 716175972000.  Starting simulation...
+info: Entering event queue @ 716175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 716175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 717175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 718175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 719175983500.  Starting simulation...
+info: Entering event queue @ 726175972000.  Starting simulation...
+info: Entering event queue @ 726175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 726175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 727175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 728175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 729175983500.  Starting simulation...
+info: Entering event queue @ 736175973000.  Starting simulation...
+info: Entering event queue @ 736175981000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 736175985500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 737175985500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 738175985500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 739175985500.  Starting simulation...
+info: Entering event queue @ 746175973000.  Starting simulation...
+info: Entering event queue @ 746175980500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 746175985000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 747175985000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 748175985000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 749175985000.  Starting simulation...
+info: Entering event queue @ 756175972000.  Starting simulation...
+info: Entering event queue @ 756175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 756175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 757175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 758175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 759175983500.  Starting simulation...
+info: Entering event queue @ 766175973000.  Starting simulation...
+info: Entering event queue @ 766175980000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 766175984500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 767175984500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 768175984500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 769175984500.  Starting simulation...
+info: Entering event queue @ 776175972000.  Starting simulation...
+info: Entering event queue @ 776175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 776175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 777175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 778175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 779175979000.  Starting simulation...
+info: Entering event queue @ 786175972000.  Starting simulation...
+info: Entering event queue @ 786175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 786175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 787175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 788175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 789175979000.  Starting simulation...
+info: Entering event queue @ 796175972000.  Starting simulation...
+info: Entering event queue @ 796175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 796175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 797175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 798175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 799175979000.  Starting simulation...
+info: Entering event queue @ 806175972000.  Starting simulation...
+info: Entering event queue @ 806175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 806175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 807175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 808175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 809175979000.  Starting simulation...
+info: Entering event queue @ 816175972000.  Starting simulation...
+info: Entering event queue @ 816175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 816175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 817175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 818175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 819175983500.  Starting simulation...
+info: Entering event queue @ 826175972000.  Starting simulation...
+info: Entering event queue @ 826175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 826175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 827175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 828175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 829175983500.  Starting simulation...
+info: Entering event queue @ 836175972000.  Starting simulation...
+info: Entering event queue @ 836175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 836175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 837175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 838175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 839175979000.  Starting simulation...
+info: Entering event queue @ 846175972000.  Starting simulation...
+info: Entering event queue @ 846175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 846175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 847175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 848175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 849175979000.  Starting simulation...
+info: Entering event queue @ 856175972000.  Starting simulation...
+info: Entering event queue @ 856231996000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 856231998000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 857231998000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 858231998000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 859231998000.  Starting simulation...
+info: Entering event queue @ 866175972000.  Starting simulation...
+info: Entering event queue @ 866175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 866175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 867175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 868175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 869175979000.  Starting simulation...
+info: Entering event queue @ 876175972000.  Starting simulation...
+info: Entering event queue @ 876175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 876175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 877175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 878175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 879175983500.  Starting simulation...
+info: Entering event queue @ 886175972000.  Starting simulation...
+info: Entering event queue @ 886175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 886175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 887175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 888175983500.  Starting simulation...
+info: Entering event queue @ 888968137000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 888968139000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 889968139000.  Starting simulation...
+info: Entering event queue @ 896175973000.  Starting simulation...
+info: Entering event queue @ 896175981000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 896175985500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 897175985500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 898175985500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 899175985500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 906175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 907175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 908175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 909175973000.  Starting simulation...
+info: Entering event queue @ 916175972000.  Starting simulation...
+info: Entering event queue @ 916175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 916175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 917175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 918175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 919175983500.  Starting simulation...
+info: Entering event queue @ 926175973000.  Starting simulation...
+info: Entering event queue @ 926175981500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 926175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 927175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 928175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 929175986000.  Starting simulation...
+info: Entering event queue @ 936175972000.  Starting simulation...
+info: Entering event queue @ 936175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 936175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 937175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 938175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 939175979000.  Starting simulation...
+info: Entering event queue @ 946175972000.  Starting simulation...
+info: Entering event queue @ 946175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 946175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 947175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 948175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 949175979000.  Starting simulation...
+info: Entering event queue @ 956175972000.  Starting simulation...
+info: Entering event queue @ 956175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 956175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 957175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 958175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 959175979000.  Starting simulation...
+info: Entering event queue @ 966175972000.  Starting simulation...
+info: Entering event queue @ 966175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 966175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 967175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 968175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 969175979000.  Starting simulation...
+info: Entering event queue @ 976175972000.  Starting simulation...
+info: Entering event queue @ 976175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 976175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 977175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 978175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 979175983500.  Starting simulation...
+info: Entering event queue @ 986175973000.  Starting simulation...
+info: Entering event queue @ 987176863000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 987176865000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 988176865000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 989176865000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 990176865000.  Starting simulation...
+info: Entering event queue @ 996175972000.  Starting simulation...
+info: Entering event queue @ 996175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 996175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 997175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 998175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 999175979000.  Starting simulation...
+info: Entering event queue @ 1006175972000.  Starting simulation...
+info: Entering event queue @ 1006175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1006175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1007175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1008175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1009175979000.  Starting simulation...
+info: Entering event queue @ 1016175972000.  Starting simulation...
+info: Entering event queue @ 1016175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1016175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1017175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1018175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1019175979000.  Starting simulation...
+info: Entering event queue @ 1026175972000.  Starting simulation...
+info: Entering event queue @ 1026175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1026175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1027175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1028175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1029175979000.  Starting simulation...
+info: Entering event queue @ 1036175972000.  Starting simulation...
+info: Entering event queue @ 1036175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1036175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1037175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1038175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1039175983500.  Starting simulation...
+info: Entering event queue @ 1046175972000.  Starting simulation...
+info: Entering event queue @ 1046175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1046175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1047175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1048175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1049175983500.  Starting simulation...
+info: Entering event queue @ 1056175972000.  Starting simulation...
+info: Entering event queue @ 1056175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1056175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1057175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1058175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1059175983500.  Starting simulation...
+info: Entering event queue @ 1066175972000.  Starting simulation...
+info: Entering event queue @ 1066175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1066175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1067175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1068175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1069175983500.  Starting simulation...
+info: Entering event queue @ 1076175972000.  Starting simulation...
+info: Entering event queue @ 1076175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1076175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1077175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1078175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1079175983500.  Starting simulation...
+info: Entering event queue @ 1086175973000.  Starting simulation...
+info: Entering event queue @ 1086175981500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1086175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1087175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1088175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1089175986000.  Starting simulation...
+info: Entering event queue @ 1096175972000.  Starting simulation...
+info: Entering event queue @ 1096175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1096175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1097175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1098175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1099175979000.  Starting simulation...
+info: Entering event queue @ 1106175972000.  Starting simulation...
+info: Entering event queue @ 1106175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1106175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1107175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1108175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1109175979000.  Starting simulation...
+info: Entering event queue @ 1116175972000.  Starting simulation...
+info: Entering event queue @ 1116175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1116175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1117175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1118175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1119175979000.  Starting simulation...
+info: Entering event queue @ 1126175972000.  Starting simulation...
+info: Entering event queue @ 1126175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1126175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1127175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1128175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1129175979000.  Starting simulation...
+info: Entering event queue @ 1136175972000.  Starting simulation...
+info: Entering event queue @ 1136175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1136175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1137175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1138175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1139175983500.  Starting simulation...
+info: Entering event queue @ 1146175972000.  Starting simulation...
+info: Entering event queue @ 1146175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1146175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1147175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1148175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1149175983500.  Starting simulation...
+info: Entering event queue @ 1156175972000.  Starting simulation...
+info: Entering event queue @ 1156175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1156175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1157175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1158175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1159175979000.  Starting simulation...
+info: Entering event queue @ 1166175972000.  Starting simulation...
+info: Entering event queue @ 1166175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1166175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1167175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1168175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1169175979000.  Starting simulation...
+info: Entering event queue @ 1176175972000.  Starting simulation...
+info: Entering event queue @ 1176175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1176175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1177175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1178175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1179175979000.  Starting simulation...
+info: Entering event queue @ 1186175972000.  Starting simulation...
+info: Entering event queue @ 1186175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1186175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1187175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1188175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1189175979000.  Starting simulation...
+info: Entering event queue @ 1196175972000.  Starting simulation...
+info: Entering event queue @ 1196175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1196175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1197175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1198175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1199175983500.  Starting simulation...
+info: Entering event queue @ 1206175972000.  Starting simulation...
+info: Entering event queue @ 1206175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1206175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1207175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1208175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1209175983500.  Starting simulation...
+info: Entering event queue @ 1216175973000.  Starting simulation...
+info: Entering event queue @ 1216330621000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1216330623000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1217330623000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1218330623000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1219330623000.  Starting simulation...
+info: Entering event queue @ 1226175973000.  Starting simulation...
+info: Entering event queue @ 1226175980500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1226175985000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1227175985000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1228175985000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1229175985000.  Starting simulation...
+info: Entering event queue @ 1236175972000.  Starting simulation...
+info: Entering event queue @ 1236175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1236175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1237175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1238175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1239175983500.  Starting simulation...
+info: Entering event queue @ 1246175973000.  Starting simulation...
+info: Entering event queue @ 1246175981500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1246175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1247175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1248175986000.  Starting simulation...
+info: Entering event queue @ 1249067221000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1249067223000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1250067223000.  Starting simulation...
+info: Entering event queue @ 1256175972000.  Starting simulation...
+info: Entering event queue @ 1256175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1256175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1257175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1258175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1259175979000.  Starting simulation...
+info: Entering event queue @ 1266175972000.  Starting simulation...
+info: Entering event queue @ 1266175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1266175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1267175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1268175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1269175979000.  Starting simulation...
+info: Entering event queue @ 1276175972000.  Starting simulation...
+info: Entering event queue @ 1276175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1276175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1277175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1278175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1279175979000.  Starting simulation...
+info: Entering event queue @ 1286175972000.  Starting simulation...
+info: Entering event queue @ 1286175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1286175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1287175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1288175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1289175979000.  Starting simulation...
+info: Entering event queue @ 1296175972000.  Starting simulation...
+info: Entering event queue @ 1296175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1296175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1297175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1298175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1299175983500.  Starting simulation...
+info: Entering event queue @ 1306175972000.  Starting simulation...
+info: Entering event queue @ 1306175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1306175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1307175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1308175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1309175983500.  Starting simulation...
+info: Entering event queue @ 1316175972000.  Starting simulation...
+info: Entering event queue @ 1316175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1316175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1317175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1318175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1319175979000.  Starting simulation...
+info: Entering event queue @ 1326175972000.  Starting simulation...
+info: Entering event queue @ 1326175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1326175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1327175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1328175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1329175979000.  Starting simulation...
+info: Entering event queue @ 1336175972000.  Starting simulation...
+info: Entering event queue @ 1336175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1336175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1337175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1338175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1339175979000.  Starting simulation...
+info: Entering event queue @ 1346175972000.  Starting simulation...
+info: Entering event queue @ 1347275947000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1347275949000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1348275949000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1349275949000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1350275949000.  Starting simulation...
+info: Entering event queue @ 1356175972000.  Starting simulation...
+info: Entering event queue @ 1356175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1356175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1357175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1358175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1359175983500.  Starting simulation...
+info: Entering event queue @ 1366175972000.  Starting simulation...
+info: Entering event queue @ 1366175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1366175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1367175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1368175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1369175983500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1376175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1377175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1378175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1379175973000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1386175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1387175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1388175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1389175973000.  Starting simulation...
+info: Entering event queue @ 1396175973000.  Starting simulation...
+info: Entering event queue @ 1396175981500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1396175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1397175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1398175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1399175986000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1406175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1407175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1408175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1409175973000.  Starting simulation...
+info: Entering event queue @ 1416175972000.  Starting simulation...
+info: Entering event queue @ 1416175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1416175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1417175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1418175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1419175979000.  Starting simulation...
+info: Entering event queue @ 1426175972000.  Starting simulation...
+info: Entering event queue @ 1426175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1426175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1427175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1428175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1429175979000.  Starting simulation...
+info: Entering event queue @ 1436175972000.  Starting simulation...
+info: Entering event queue @ 1436175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1436175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1437175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1438175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1439175979000.  Starting simulation...
+info: Entering event queue @ 1446175972000.  Starting simulation...
+info: Entering event queue @ 1446175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1446175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1447175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1448175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1449175979000.  Starting simulation...
+info: Entering event queue @ 1456175972000.  Starting simulation...
+info: Entering event queue @ 1456175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1456175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1457175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1458175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1459175983500.  Starting simulation...
+info: Entering event queue @ 1466175972000.  Starting simulation...
+info: Entering event queue @ 1466175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1466175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1467175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1468175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1469175983500.  Starting simulation...
+info: Entering event queue @ 1476175972000.  Starting simulation...
+info: Entering event queue @ 1476175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1476175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1477175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1478175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1479175979000.  Starting simulation...
+info: Entering event queue @ 1486175972000.  Starting simulation...
+info: Entering event queue @ 1486175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1486175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1487175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1488175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1489175979000.  Starting simulation...
+info: Entering event queue @ 1496175972000.  Starting simulation...
+info: Entering event queue @ 1496175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1496175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1497175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1498175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1499175979000.  Starting simulation...
+info: Entering event queue @ 1506175972000.  Starting simulation...
+info: Entering event queue @ 1506175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1506175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1507175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1508175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1509175979000.  Starting simulation...
+info: Entering event queue @ 1516175972000.  Starting simulation...
+info: Entering event queue @ 1516175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1516175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1517175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1518175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1519175983500.  Starting simulation...
+info: Entering event queue @ 1526175972000.  Starting simulation...
+info: Entering event queue @ 1526175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1526175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1527175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1528175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1529175983500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1536175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1537175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1538175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1539175973000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1546175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1547175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1548175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1549175973000.  Starting simulation...
+info: Entering event queue @ 1556175972000.  Starting simulation...
+info: Entering event queue @ 1556175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1556175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1557175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1558175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1559175983500.  Starting simulation...
+info: Entering event queue @ 1566175973000.  Starting simulation...
+info: Entering event queue @ 1566175981500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1566175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1567175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1568175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1569175986000.  Starting simulation...
+info: Entering event queue @ 1576175972000.  Starting simulation...
+info: Entering event queue @ 1576429705000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1576429707000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1577429707000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1578429707000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1579429707000.  Starting simulation...
+info: Entering event queue @ 1586175972000.  Starting simulation...
+info: Entering event queue @ 1586175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1586175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1587175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1588175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1589175979000.  Starting simulation...
+info: Entering event queue @ 1596175972000.  Starting simulation...
+info: Entering event queue @ 1596175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1596175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1597175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1598175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1599175979000.  Starting simulation...
+info: Entering event queue @ 1606175972000.  Starting simulation...
+info: Entering event queue @ 1606175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1606175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1607175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1608175979000.  Starting simulation...
+info: Entering event queue @ 1609165996000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1609165998000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1610165998000.  Starting simulation...
+info: Entering event queue @ 1616175972000.  Starting simulation...
+info: Entering event queue @ 1616175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1616175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1617175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1618175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1619175983500.  Starting simulation...
+info: Entering event queue @ 1626175972000.  Starting simulation...
+info: Entering event queue @ 1626175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1626175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1627175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1628175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1629175983500.  Starting simulation...
+info: Entering event queue @ 1636175972000.  Starting simulation...
+info: Entering event queue @ 1636175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1636175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1637175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1638175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1639175979000.  Starting simulation...
+info: Entering event queue @ 1646175972000.  Starting simulation...
+info: Entering event queue @ 1646175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1646175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1647175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1648175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1649175979000.  Starting simulation...
+info: Entering event queue @ 1656175972000.  Starting simulation...
+info: Entering event queue @ 1656175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1656175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1657175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1658175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1659175979000.  Starting simulation...
+info: Entering event queue @ 1666175972000.  Starting simulation...
+info: Entering event queue @ 1666175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1666175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1667175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1668175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1669175979000.  Starting simulation...
+info: Entering event queue @ 1676175972000.  Starting simulation...
+info: Entering event queue @ 1676175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1676175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1677175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1678175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1679175983500.  Starting simulation...
+info: Entering event queue @ 1686175972000.  Starting simulation...
+info: Entering event queue @ 1686175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1686175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1687175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1688175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1689175983500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1696175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1697175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1698175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1699175973000.  Starting simulation...
+info: Entering event queue @ 1706175973000.  Starting simulation...
+info: Entering event queue @ 1707375031000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1707375033000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1708375033000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1709375033000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1710375033000.  Starting simulation...
+info: Entering event queue @ 1716175972000.  Starting simulation...
+info: Entering event queue @ 1716175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1716175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1717175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1718175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1719175983500.  Starting simulation...
+info: Entering event queue @ 1726175973000.  Starting simulation...
+info: Entering event queue @ 1726175981500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1726175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1727175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1728175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1729175986000.  Starting simulation...
+info: Entering event queue @ 1736175972000.  Starting simulation...
+info: Entering event queue @ 1736175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1736175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1737175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1738175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1739175979000.  Starting simulation...
+info: Entering event queue @ 1746175972000.  Starting simulation...
+info: Entering event queue @ 1746175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1746175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1747175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1748175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1749175979000.  Starting simulation...
+info: Entering event queue @ 1756175972000.  Starting simulation...
+info: Entering event queue @ 1756175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1756175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1757175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1758175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1759175979000.  Starting simulation...
+info: Entering event queue @ 1766175972000.  Starting simulation...
+info: Entering event queue @ 1766175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1766175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1767175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1768175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1769175979000.  Starting simulation...
+info: Entering event queue @ 1776175972000.  Starting simulation...
+info: Entering event queue @ 1776175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1776175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1777175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1778175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1779175983500.  Starting simulation...
+info: Entering event queue @ 1786175972000.  Starting simulation...
+info: Entering event queue @ 1786175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1786175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1787175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1788175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1789175983500.  Starting simulation...
+info: Entering event queue @ 1796175972000.  Starting simulation...
+info: Entering event queue @ 1796175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1796175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1797175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1798175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1799175979000.  Starting simulation...
+info: Entering event queue @ 1806175972000.  Starting simulation...
+info: Entering event queue @ 1806175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1806175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1807175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1808175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1809175979000.  Starting simulation...
+info: Entering event queue @ 1816175972000.  Starting simulation...
+info: Entering event queue @ 1816175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1816175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1817175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1818175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1819175979000.  Starting simulation...
+info: Entering event queue @ 1826175972000.  Starting simulation...
+info: Entering event queue @ 1826175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1826175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1827175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1828175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1829175979000.  Starting simulation...
+info: Entering event queue @ 1836175972000.  Starting simulation...
+info: Entering event queue @ 1836175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1836175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1837175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1838175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1839175983500.  Starting simulation...
+info: Entering event queue @ 1846175972000.  Starting simulation...
+info: Entering event queue @ 1846175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1846175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1847175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1848175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1849175983500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1856175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1857175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1858175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1859175973000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1866175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1867175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1868175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1869175973000.  Starting simulation...
+info: Entering event queue @ 1876175972000.  Starting simulation...
+info: Entering event queue @ 1876175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1876175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1877175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1878175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1879175983500.  Starting simulation...
+info: Entering event queue @ 1886175973000.  Starting simulation...
+info: Entering event queue @ 1886175981500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1886175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1887175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1888175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1889175986000.  Starting simulation...
+info: Entering event queue @ 1896175972000.  Starting simulation...
+info: Entering event queue @ 1896175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1896175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1897175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1898175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1899175979000.  Starting simulation...
+info: Entering event queue @ 1906175972000.  Starting simulation...
+info: Entering event queue @ 1906175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1906175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1907175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1908175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1909175979000.  Starting simulation...
+info: Entering event queue @ 1916175972000.  Starting simulation...
+info: Entering event queue @ 1916175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1916175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1917175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1918175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1919175979000.  Starting simulation...
+info: Entering event queue @ 1926175972000.  Starting simulation...
+info: Entering event queue @ 1926175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1926175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1927175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1928175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1929175979000.  Starting simulation...
+info: Entering event queue @ 1936175972000.  Starting simulation...
+info: Entering event queue @ 1936528480000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1936528482000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1937528482000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1938528482000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1939528482000.  Starting simulation...
+info: Entering event queue @ 1946175972000.  Starting simulation...
+info: Entering event queue @ 1946175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1946175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1947175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1948175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1949175983500.  Starting simulation...
+info: Entering event queue @ 1956175972000.  Starting simulation...
+info: Entering event queue @ 1956175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1956175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1957175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1958175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1959175979000.  Starting simulation...
+info: Entering event queue @ 1966175972000.  Starting simulation...
+info: Entering event queue @ 1966175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1966175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1967175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1968175979000.  Starting simulation...
+info: Entering event queue @ 1969264621000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1969264623000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1970264623000.  Starting simulation...
+info: Entering event queue @ 1976175972000.  Starting simulation...
+info: Entering event queue @ 1976175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1976175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1977175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1978175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1979175979000.  Starting simulation...
+info: Entering event queue @ 1986175972000.  Starting simulation...
+info: Entering event queue @ 1986175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1986175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1987175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1988175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1989175979000.  Starting simulation...
+info: Entering event queue @ 1996175972000.  Starting simulation...
+info: Entering event queue @ 1996175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1996175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1997175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1998175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1999175983500.  Starting simulation...
+info: Entering event queue @ 2006175972000.  Starting simulation...
+info: Entering event queue @ 2006175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2006175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2007175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2008175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2009175983500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2016175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2017175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2018175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2019175973000.  Starting simulation...
+info: Entering event queue @ 2026175973000.  Starting simulation...
+info: Entering event queue @ 2026175980500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2026175985000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2027175985000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2028175985000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2029175985000.  Starting simulation...
+info: Entering event queue @ 2036175972000.  Starting simulation...
+info: Entering event queue @ 2036175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2036175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2037175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2038175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2039175983500.  Starting simulation...
+info: Entering event queue @ 2046175973000.  Starting simulation...
+info: Entering event queue @ 2046175981500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2046175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2047175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2048175986000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2049175986000.  Starting simulation...
+info: Entering event queue @ 2056175972000.  Starting simulation...
+info: Entering event queue @ 2056175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2056175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2057175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2058175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2059175979000.  Starting simulation...
+info: Entering event queue @ 2066175972000.  Starting simulation...
+info: Entering event queue @ 2067473656000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2067473658000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2068473658000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2069473658000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2070473658000.  Starting simulation...
+info: Entering event queue @ 2076175972000.  Starting simulation...
+info: Entering event queue @ 2076175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2076175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2077175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2078175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2079175979000.  Starting simulation...
+info: Entering event queue @ 2086175972000.  Starting simulation...
+info: Entering event queue @ 2086175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2086175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2087175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2088175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2089175979000.  Starting simulation...
+info: Entering event queue @ 2096175972000.  Starting simulation...
+info: Entering event queue @ 2096175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2096175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2097175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2098175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2099175983500.  Starting simulation...
+info: Entering event queue @ 2106175972000.  Starting simulation...
+info: Entering event queue @ 2106175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2106175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2107175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2108175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2109175983500.  Starting simulation...
+info: Entering event queue @ 2116175972000.  Starting simulation...
+info: Entering event queue @ 2116175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2116175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2117175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2118175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2119175979000.  Starting simulation...
+info: Entering event queue @ 2126175972000.  Starting simulation...
+info: Entering event queue @ 2126175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2126175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2127175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2128175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2129175979000.  Starting simulation...
+info: Entering event queue @ 2136175972000.  Starting simulation...
+info: Entering event queue @ 2136175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2136175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2137175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2138175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2139175979000.  Starting simulation...
+info: Entering event queue @ 2146175972000.  Starting simulation...
+info: Entering event queue @ 2146175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2146175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2147175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2148175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2149175979000.  Starting simulation...
+info: Entering event queue @ 2156175972000.  Starting simulation...
+info: Entering event queue @ 2156175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2156175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2157175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2158175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2159175983500.  Starting simulation...
+info: Entering event queue @ 2166175972000.  Starting simulation...
+info: Entering event queue @ 2166175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2166175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2167175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2168175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2169175983500.  Starting simulation...
+info: Entering event queue @ 2176175972000.  Starting simulation...
+info: Entering event queue @ 2176175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2176175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2177175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2178175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2179175983500.  Starting simulation...
+info: Entering event queue @ 2186175972000.  Starting simulation...
+info: Entering event queue @ 2186175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2186175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2187175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2188175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2189175983500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2196175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2197175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2198175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2199175973000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2206175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2207175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2208175973000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2209175973000.  Starting simulation...
+info: Entering event queue @ 2216175972000.  Starting simulation...
+info: Entering event queue @ 2216175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2216175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2217175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2218175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2219175979000.  Starting simulation...
+info: Entering event queue @ 2226175972000.  Starting simulation...
+info: Entering event queue @ 2226175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2226175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2227175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2228175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2229175979000.  Starting simulation...
+info: Entering event queue @ 2236175972000.  Starting simulation...
+info: Entering event queue @ 2236175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2236175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2237175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2238175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2239175979000.  Starting simulation...
+info: Entering event queue @ 2246175972000.  Starting simulation...
+info: Entering event queue @ 2246175978500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2246175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2247175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2248175979000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2249175979000.  Starting simulation...
+info: Entering event queue @ 2256175972000.  Starting simulation...
+info: Entering event queue @ 2256175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2256175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2257175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2258175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2259175983500.  Starting simulation...
+info: Entering event queue @ 2266175972000.  Starting simulation...
+info: Entering event queue @ 2266175979000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2266175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2267175983500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2268175983500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2268175984500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2269175984500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2269176099000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2270176099000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2270176101000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2271176101000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2271176134000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2272176134000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2272176298000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2273176298000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2274176298000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2274176358000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2275176358000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2275176444000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2276176444000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2277176444000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2277176548000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2278176548000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2278176623000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2279176623000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2280176623000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2280176733000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2281176733000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2281177431000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2282177431000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2283177431000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2283177432000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2284177432000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2284177537000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2285177537000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2286177537000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2286177620000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2287177620000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2287177681000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2288177681000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2289177681000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2289177796000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2290177796000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2290177891000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2291177891000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2292177891000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2292177955000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2293177955000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2293178118500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2294178118500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2295178118500.  Starting simulation...
+info: Entering event queue @ 2296627561000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2296627563000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2297627563000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2297627577000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2298627577000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2299627577000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2299627643000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2300627643000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2300627767000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2301627767000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2302627767000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2302627826000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2303627826000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2303627914000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2304627914000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2305627914000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2305628068000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2306628068000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2306628219000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2307628219000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2308628219000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2308628231000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2309628231000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2309628374500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2310628374500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2311628374500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2311628440000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2312628440000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2312628571000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2313628571000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2314628571000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2314628586000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2315628586000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2315628609000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2316628609000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2317628609000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2317628760000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2318628760000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2318628871500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2319628871500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2320628871500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2320628950000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2321628950000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2321628957000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2322628957000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2323628957000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2323629079000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2324629079000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2324629126000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2325629126000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2326629126000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2326629176000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2327629176000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2327629301000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2328629301000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2329629301000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2329629399000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2330629399000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2330629558000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2331629558000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2332629558000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2332629573000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2333629573000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2333629640000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2334629640000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2335629640000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2335629779000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2336629779000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2336629888500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2337629888500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2338629888500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2338630042000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2339630042000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2339630075000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2340630075000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2341630075000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2341630098000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2342630098000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2342630224500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2343630224500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2344630224500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2344630308000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2345630308000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2345630440000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2346630440000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2347630440000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2347630481000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2348630481000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2348630538000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2349630538000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2350630538000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2350630623000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2351630623000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2351630640000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2352630640000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2353630640000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2353630748000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2354630748000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2354630878000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2355630878000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2356630878000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2356630895000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2357630895000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2357630943000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2358630943000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2359630943000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2359630963000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2360630963000.  Starting simulation...
+info: Entering event queue @ 2362100305000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2362100307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2363100307000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2364100307000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2364100364000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2365100364000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2365100522000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2366100522000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2367100522000.  Starting simulation...
+info: Entering event queue @ 2367100525000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2367100527500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2368100527500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2368100529500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2369100529500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2370100529500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2370100533000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2371100533000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2371100682500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2372100682500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2373100682500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2373100683500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2374100683500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2374102804500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2375102804500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2376102804500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2376102808000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2377102808000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2377102891000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2378102891000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2379102891000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2379102993000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2380102993000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2380103021000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2381103021000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2382103021000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2382103048000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2383103048000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2383112179000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2384112179000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2385112179000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2385112305000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2386112305000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2386112310500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2387112310500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2387112312500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2388112312500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2388112314500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2389112314500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2389112333500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2390112333500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2391112333500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2391112334500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2392112334500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2392112630500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2393112630500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2393112631000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2394112631000.  Starting simulation...
+info: Entering event queue @ 2394836596000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2394836598000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2395836598000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2395839042500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2396839042500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2397839042500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2397839043500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2398839043500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2398839190000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2399839190000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2399839190500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2400839190500.  Starting simulation...
+info: Entering event queue @ 2400839197500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2400839201000.  Starting simulation...
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
new file mode 100644
index 0000000..ba42539
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
@@ -0,0 +1,1572 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  2.401421                       # Number of seconds simulated
+sim_ticks                                2401421439000                       # Number of ticks simulated
+final_tick                               2401421439000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 170882                       # Simulator instruction rate (inst/s)
+host_op_rate                                   219406                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6786575645                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 393972                       # Number of bytes of host memory used
+host_seconds                                   353.85                       # Real time elapsed on the host
+sim_insts                                    60466509                       # Number of instructions simulated
+sim_ops                                      77636591                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::realview.clcd    114819072                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           478816                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          7027600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst            73664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           716876                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker         1216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.itb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           218496                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          1332556                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            124668680                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       478816                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        73664                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       218496                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          770976                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3748032                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data       1052216                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data        199484                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2.data       1764144                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6763876                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      14352384                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             13684                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            109840                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1151                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             11204                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker           19                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.itb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              3414                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             20824                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              14512526                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           58563                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data           263054                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data            49871                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2.data           441036                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               812524                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47812962                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker            27                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker            53                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              199389                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             2926433                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker            27                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               30675                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              298522                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker           506                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.itb.walker            53                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               90986                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              554903                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51914536                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         199389                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          30675                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          90986                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             321050                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1560756                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data             438164                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data              83069                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2.data             734625                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2816613                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1560756                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47812962                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker           27                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker           53                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             199389                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            3364597                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker           27                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              30675                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             381591                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker          506                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.itb.walker           53                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst              90986                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            1289528                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               54731150                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      12619527                       # Total number of read requests seen
+system.physmem.writeReqs                       508095                       # Total number of write requests seen
+system.physmem.cpureqs                          56153                       # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead                    807649728                       # Total number of bytes read from memory
+system.physmem.bytesWritten                  32518080                       # Total number of bytes written to memory
+system.physmem.bytesConsumedRd              103006296                       # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr                3063660                       # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ                        2                       # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite               2356                       # Reqs where no action is needed
+system.physmem.perBankRdReqs::0                788374                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1                788516                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2                788173                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3                788282                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4                788267                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5                788268                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6                788411                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7                789077                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8                789904                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9                789864                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10               789609                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11               789636                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12               788668                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13               788108                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14               788208                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15               788160                       # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0                 30462                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1                 31339                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2                 31367                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3                 31519                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4                 31434                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5                 31463                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6                 31715                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7                 32144                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8                 32667                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9                 32642                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10                32415                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11                32370                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12                31797                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13                31479                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14                31921                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15                31361                       # Track writes on a per bank basis
+system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry                      317403                       # Number of times wr buffer was full causing retry
+system.physmem.totGap                    2400386249000                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::2                       6                       # Categorize read packet sizes
+system.physmem.readPktSize::3                12582912                       # Categorize read packet sizes
+system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::6                   36609                       # Categorize read packet sizes
+system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
+system.physmem.writePktSize::0                      0                       # categorize write packet sizes
+system.physmem.writePktSize::1                      0                       # categorize write packet sizes
+system.physmem.writePktSize::2                 808310                       # categorize write packet sizes
+system.physmem.writePktSize::3                      0                       # categorize write packet sizes
+system.physmem.writePktSize::4                      0                       # categorize write packet sizes
+system.physmem.writePktSize::5                      0                       # categorize write packet sizes
+system.physmem.writePktSize::6                  17188                       # categorize write packet sizes
+system.physmem.writePktSize::7                      0                       # categorize write packet sizes
+system.physmem.writePktSize::8                      0                       # categorize write packet sizes
+system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::6                 2356                       # categorize neither packet sizes
+system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
+system.physmem.rdQLenPdf::0                    817282                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    792530                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    787018                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    816081                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                   2309777                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                   2310026                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   4565188                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     24972                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     24597                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                     24594                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                    24587                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                    47867                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    24582                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    47847                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                     1291                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                     1284                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0                      3518                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                      3552                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                      3620                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                      3760                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                      3937                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                      4056                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                      4161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                      4250                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                      4415                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                     22096                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                    22090                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                    22088                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                    22084                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                    22079                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::15                    22070                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    22068                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    22064                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    22061                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    22055                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    22051                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    22047                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    22044                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    18625                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    18585                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    18515                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    18369                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    18188                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    18065                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    17957                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    17859                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17690                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.totQLat                   234691241923                       # Total cycles spent in queuing delays
+system.physmem.totMemAccLat              297448055923                       # Sum of mem lat for all requests
+system.physmem.totBusLat                  50478100000                       # Total cycles spent in databus access
+system.physmem.totBankLat                 12278714000                       # Total cycles spent in bank access
+system.physmem.avgQLat                       18597.47                       # Average queueing delay per request
+system.physmem.avgBankLat                      972.99                       # Average bank access latency per request
+system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
+system.physmem.avgMemAccLat                  23570.46                       # Average memory access latency
+system.physmem.avgRdBW                         336.32                       # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW                          13.54                       # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW                  42.89                       # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW                   1.28                       # Average consumed write bandwidth in MB/s
+system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil                           2.19                       # Data bus utilization in percentage
+system.physmem.avgRdQLen                         0.12                       # Average read queue length over time
+system.physmem.avgWrQLen                         0.40                       # Average write queue length over time
+system.physmem.readRowHits                   12589945                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    499132                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   99.77                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  98.24                       # Row buffer hit rate for writes
+system.physmem.avgGap                       182850.04                       # Average gap between requests
+system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                         63371                       # number of replacements
+system.l2c.tagsinuse                     50440.930838                       # Cycle average of tags in use
+system.l2c.total_refs                         1764263                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        128761                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         13.701843                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                  2374519462500                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        36775.045658                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.dtb.walker       0.000018                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.itb.walker       0.000124                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          4782.596749                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          3401.388842                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.dtb.walker       0.993264                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst           624.225892                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data          1084.430901                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.dtb.walker      16.710319                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.itb.walker       0.970933                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.inst          2110.368967                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.data          1644.199171                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.561143                       # Average percentage of cache occupancy
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+system.l2c.occ_percent::cpu1.inst            0.009525                       # Average percentage of cache occupancy
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+system.l2c.Writeback_hits::writebacks          597611                       # number of Writeback hits
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+system.l2c.UpgradeReq_hits::cpu1.data               4                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2.data              14                       # number of UpgradeReq hits
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+system.l2c.UpgradeReq_misses::cpu2.data           987                       # number of UpgradeReq misses
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+system.l2c.demand_accesses::cpu2.inst          289339                       # number of demand (read+write) accesses
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+system.l2c.demand_accesses::total             1575437                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         8851                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         3420                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::total            1575437                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000113                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000585                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.014907                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.031070                       # miss rate for ReadReq accesses
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+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000582                       # miss rate for ReadReq accesses
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+system.l2c.ReadReq_miss_rate::cpu2.inst      0.011806                       # miss rate for ReadReq accesses
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+system.l2c.ReadReq_miss_rate::total          0.016414                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.990985                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.991886                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.986014                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.989441                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.626453                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.347876                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.365463                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.539900                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000113                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000585                       # miss rate for demand accesses
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+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000113                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000582                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::total          0.098493                       # miss rate for overall accesses
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+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51417.028671                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 52455.505762                       # average ReadReq miss latency
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+system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker        68500                       # average ReadReq miss latency
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+system.l2c.ReadReq_avg_miss_latency::total 22535.152442                       # average ReadReq miss latency
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+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   138.804458                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total    78.657487                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 44622.288366                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53950.624170                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 10931.443782                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        69000                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::total 12562.035181                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks::writebacks               58563                       # number of writebacks
+system.l2c.writebacks::total                    58563                       # number of writebacks
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+system.l2c.UpgradeReq_mshr_misses::cpu2.data          987                       # number of UpgradeReq MSHR misses
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+system.l2c.UpgradeReq_mshr_miss_latency::total     14818943                       # number of UpgradeReq MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu1.data    376974564                       # number of demand (read+write) MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu2.data    897793025                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   1475093295                       # number of demand (read+write) MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::cpu2.data    897793025                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   1475093295                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  25233133000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  26572368004                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total  51805501004                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    640106868                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   7144945536                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   7785052404                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data        76004                       # number of LoadLockedReq MSHR uncacheable cycles
+system.l2c.LoadLockedReq_mshr_uncacheable_latency::total        76004                       # number of LoadLockedReq MSHR uncacheable cycles
+system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data        30003                       # number of StoreCondReq MSHR uncacheable cycles
+system.l2c.StoreCondReq_mshr_uncacheable_latency::total        30003                       # number of StoreCondReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data  25873239868                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data  33717313540                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  59590553408                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000388                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.008970                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.026158                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000582                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.000441                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.011799                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.019761                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.006589                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.991886                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.986014                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.502725                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.347876                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.365463                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.116332                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000388                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.008970                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.130072                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000582                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.000441                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.011799                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.116915                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.023796                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000388                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.008970                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.130072                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000582                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.000441                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.011799                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.116915                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.023796                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        56002                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 38719.183319                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 39635.471191                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 58238.684211                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker        56002                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 45250.552138                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 44961.523425                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 43335.555695                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10118.519427                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10039.934282                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 31789.320755                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41472.149695                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 38132.557628                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        56002                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 38719.183319                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 32857.540661                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 58238.684211                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker        56002                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 45250.552138                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41896.169910                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 39347.363093                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        56002                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 38719.183319                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 32857.540661                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 58238.684211                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker        56002                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 45250.552138                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41896.169910                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 39347.363093                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average LoadLockedReq mshr uncacheable latency
+system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total          inf                       # average LoadLockedReq mshr uncacheable latency
+system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average StoreCondReq mshr uncacheable latency
+system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total          inf                       # average StoreCondReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
+system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
+system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
+system.cpu0.dtb.read_hits                     7902224                       # DTB read hits
+system.cpu0.dtb.read_misses                      6242                       # DTB read misses
+system.cpu0.dtb.write_hits                    6537817                       # DTB write hits
+system.cpu0.dtb.write_misses                     1923                       # DTB write misses
+system.cpu0.dtb.flush_tlb                         279                       # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid                688                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                    5669                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                   113                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults                      213                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                 7908466                       # DTB read accesses
+system.cpu0.dtb.write_accesses                6539740                       # DTB write accesses
+system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
+system.cpu0.dtb.hits                         14440041                       # DTB hits
+system.cpu0.dtb.misses                           8165                       # DTB misses
+system.cpu0.dtb.accesses                     14448206                       # DTB accesses
+system.cpu0.itb.inst_hits                    31853127                       # ITB inst hits
+system.cpu0.itb.inst_misses                      3518                       # ITB inst misses
+system.cpu0.itb.read_hits                           0                       # DTB read hits
+system.cpu0.itb.read_misses                         0                       # DTB read misses
+system.cpu0.itb.write_hits                          0                       # DTB write hits
+system.cpu0.itb.write_misses                        0                       # DTB write misses
+system.cpu0.itb.flush_tlb                         279                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid                688                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                    2622                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
+system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
+system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
+system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.read_accesses                       0                       # DTB read accesses
+system.cpu0.itb.write_accesses                      0                       # DTB write accesses
+system.cpu0.itb.inst_accesses                31856645                       # ITB inst accesses
+system.cpu0.itb.hits                         31853127                       # DTB hits
+system.cpu0.itb.misses                           3518                       # DTB misses
+system.cpu0.itb.accesses                     31856645                       # DTB accesses
+system.cpu0.numCycles                       112931028                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.committedInsts                   31362077                       # Number of instructions committed
+system.cpu0.committedOps                     41448320                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             36567470                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  5105                       # Number of float alu accesses
+system.cpu0.num_func_calls                    1216492                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      4268853                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    36567470                       # number of integer instructions
+system.cpu0.num_fp_insts                         5105                       # number of float instructions
+system.cpu0.num_int_register_reads          186633277                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          38778240                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                3615                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes               1492                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                     15097186                       # number of memory refs
+system.cpu0.num_load_insts                    8269911                       # Number of load instructions
+system.cpu0.num_store_insts                   6827275                       # Number of store instructions
+system.cpu0.num_idle_cycles              13401980962.617596                       # Number of idle cycles
+system.cpu0.num_busy_cycles              -13289049934.617596                       # Number of busy cycles
+system.cpu0.not_idle_fraction             -117.674037                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                  118.674037                       # Percentage of idle cycles
+system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu0.kern.inst.quiesce                   84468                       # number of quiesce instructions executed
+system.cpu0.icache.replacements                892780                       # number of replacements
+system.cpu0.icache.tagsinuse               511.591234                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                43441886                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                893292                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                 48.631227                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle            8001805000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst   491.376976                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_blocks::cpu1.inst     7.109245                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_blocks::cpu2.inst    13.105014                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.959721                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::cpu1.inst     0.013885                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::cpu2.inst     0.025596                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.999202                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst     31380980                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst      8436238                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst      3624668                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       43441886                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     31380980                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst      8436238                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst      3624668                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        43441886                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     31380980                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst      8436238                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst      3624668                       # number of overall hits
+system.cpu0.icache.overall_hits::total       43441886                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       474853                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       128587                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       314740                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       918180                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       474853                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       128587                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       314740                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        918180                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       474853                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       128587                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       314740                       # number of overall misses
+system.cpu0.icache.overall_misses::total       918180                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1722310000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4209726988                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   5932036988                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   1722310000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   4209726988                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   5932036988                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   1722310000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   4209726988                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   5932036988                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     31855833                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst      8564825                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst      3939408                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     44360066                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     31855833                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst      8564825                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst      3939408                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     44360066                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     31855833                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst      8564825                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst      3939408                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     44360066                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014906                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015013                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.079895                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.020698                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014906                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015013                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.079895                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.020698                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014906                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015013                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.079895                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.020698                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13394.122267                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13375.252551                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  6460.647137                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13394.122267                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13375.252551                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  6460.647137                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13394.122267                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13375.252551                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  6460.647137                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         3469                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              241                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.394191                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        24876                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        24876                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        24876                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        24876                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        24876                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        24876                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       128587                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       289864                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       418451                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       128587                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       289864                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       418451                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       128587                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       289864                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       418451                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1465136000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3427061488                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   4892197488                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1465136000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3427061488                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   4892197488                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1465136000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3427061488                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   4892197488                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015013                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.073581                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009433                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015013                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.073581                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.009433                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015013                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.073581                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.009433                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11394.122267                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11822.997985                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11691.207544                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11394.122267                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11822.997985                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11691.207544                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11394.122267                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11822.997985                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11691.207544                       # average overall mshr miss latency
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.replacements                629952                       # number of replacements
+system.cpu0.dcache.tagsinuse               511.997116                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                23322161                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs                630464                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                 36.992058                       # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle              21763000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::cpu0.data   497.280136                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_blocks::cpu1.data     8.191597                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_blocks::cpu2.data     6.525382                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.971250                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::cpu1.data     0.015999                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::cpu2.data     0.012745                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.999994                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6763167                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      1877822                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      4718068                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       13359057                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      5963557                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      1365617                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data      2102817                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       9431991                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       135570                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        32797                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        91307                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       259674                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       142092                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data        34425                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data        91924                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       268441                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     12726724                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      3243439                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data      6820885                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        22791048                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     12726724                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      3243439                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data      6820885                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       22791048                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       185432                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data        58086                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data       273913                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       517431                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       168460                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data        28983                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data       595876                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       793319                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6522                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         1629                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         3810                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        11961                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu2.data            6                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total            6                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       353892                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data        87069                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data       869789                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1310750                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       353892                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data        87069                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data       869789                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1310750                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data    824588500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   3876286000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   4700874500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data    726126000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  19133055918                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  19859181918                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     21335000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data     51226000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total     72561000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data        78000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total        78000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   1550714500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  23009341918                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  24560056418                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   1550714500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  23009341918                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  24560056418                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      6948599                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      1935908                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      4991981                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     13876488                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      6132017                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      1394600                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      2698693                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     10225310                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       142092                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        34426                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        95117                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       271635                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       142092                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        34425                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        91930                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       268447                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     13080616                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      3330508                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      7690674                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     24101798                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     13080616                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      3330508                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      7690674                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     24101798                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.026686                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.030005                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.054871                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.037288                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.027472                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.020782                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.220802                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.077584                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.045900                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.047319                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.040056                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.044033                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000065                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000022                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027055                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.026143                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.113097                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.054384                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027055                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.026143                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.113097                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.054384                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14195.993871                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14151.522564                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total  9085.026796                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 25053.514129                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32109.123237                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 25033.034527                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13096.992020                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13445.144357                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  6066.466015                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        13000                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17810.179283                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 26453.935285                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 18737.407147                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17810.179283                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 26453.935285                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 18737.407147                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs         6963                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets          952                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs              771                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets             46                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs     9.031128                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    20.695652                       # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.dcache.writebacks::writebacks       597611                       # number of writebacks
+system.cpu0.dcache.writebacks::total           597611                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       145491                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       145491                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       543392                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       543392                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data          428                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total          428                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       688883                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       688883                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       688883                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       688883                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        58086                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       128422                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       186508                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        28983                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        52484                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total        81467                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1629                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         3382                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         5011                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            6                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total            6                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data        87069                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       180906                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       267975                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data        87069                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       180906                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       267975                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    708416500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   1664999000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2373415500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data    668160000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   1456004992                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   2124164992                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     18077000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     39418000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     57495000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        66000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        66000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   1376576500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   3121003992                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   4497580492                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   1376576500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   3121003992                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   4497580492                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  27568021500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  29009742000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  56577763500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1272962000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data  12893978360                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  14166940360                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data       117500                       # number of LoadLockedReq MSHR uncacheable cycles
+system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total       117500                       # number of LoadLockedReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data        69000                       # number of StoreCondReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total        69000                       # number of StoreCondReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  28840983500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  41903720360                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  70744703860                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.030005                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.025726                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.013441                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.020782                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.019448                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007967                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.047319                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.035556                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.018448                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000065                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000022                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.026143                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.023523                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.011118                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.026143                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.023523                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.011118                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12195.993871                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12965.060504                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12725.542604                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23053.514129                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27741.883088                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26073.931678                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11096.992020                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11655.233590                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11473.757733                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        11000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15810.179283                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17252.075619                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16783.582394                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15810.179283                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17252.075619                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16783.582394                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average LoadLockedReq mshr uncacheable latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total          inf                       # average LoadLockedReq mshr uncacheable latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average StoreCondReq mshr uncacheable latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total          inf                       # average StoreCondReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
+system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
+system.cpu1.dtb.read_hits                     2149941                       # DTB read hits
+system.cpu1.dtb.read_misses                      2094                       # DTB read misses
+system.cpu1.dtb.write_hits                    1479770                       # DTB write hits
+system.cpu1.dtb.write_misses                      382                       # DTB write misses
+system.cpu1.dtb.flush_tlb                         277                       # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid                240                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                     11                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                    1681                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                    46                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
+system.cpu1.dtb.perms_faults                       79                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 2152035                       # DTB read accesses
+system.cpu1.dtb.write_accesses                1480152                       # DTB write accesses
+system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
+system.cpu1.dtb.hits                          3629711                       # DTB hits
+system.cpu1.dtb.misses                           2476                       # DTB misses
+system.cpu1.dtb.accesses                      3632187                       # DTB accesses
+system.cpu1.itb.inst_hits                     8564825                       # ITB inst hits
+system.cpu1.itb.inst_misses                      1128                       # ITB inst misses
+system.cpu1.itb.read_hits                           0                       # DTB read hits
+system.cpu1.itb.read_misses                         0                       # DTB read misses
+system.cpu1.itb.write_hits                          0                       # DTB write hits
+system.cpu1.itb.write_misses                        0                       # DTB write misses
+system.cpu1.itb.flush_tlb                         277                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid                240                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                     11                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                     827                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
+system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
+system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
+system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.read_accesses                       0                       # DTB read accesses
+system.cpu1.itb.write_accesses                      0                       # DTB write accesses
+system.cpu1.itb.inst_accesses                 8565953                       # ITB inst accesses
+system.cpu1.itb.hits                          8564825                       # DTB hits
+system.cpu1.itb.misses                           1128                       # DTB misses
+system.cpu1.itb.accesses                      8565953                       # DTB accesses
+system.cpu1.numCycles                       573618226                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.committedInsts                    8360582                       # Number of instructions committed
+system.cpu1.committedOps                     10552123                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses              9474069                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  2062                       # Number of float alu accesses
+system.cpu1.num_func_calls                     304948                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      1122653                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                     9474069                       # number of integer instructions
+system.cpu1.num_fp_insts                         2062                       # number of float instructions
+system.cpu1.num_int_register_reads           54388368                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          10296894                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                1613                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes                450                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                      3801129                       # number of memory refs
+system.cpu1.num_load_insts                    2242444                       # Number of load instructions
+system.cpu1.num_store_insts                   1558685                       # Number of store instructions
+system.cpu1.num_idle_cycles              -28470862.464355                       # Number of idle cycles
+system.cpu1.num_busy_cycles              602089088.464355                       # Number of busy cycles
+system.cpu1.not_idle_fraction                1.049634                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                   -0.049634                       # Percentage of idle cycles
+system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
+system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
+system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
+system.cpu2.dtb.read_hits                    11072336                       # DTB read hits
+system.cpu2.dtb.read_misses                     27162                       # DTB read misses
+system.cpu2.dtb.write_hits                    3379244                       # DTB write hits
+system.cpu2.dtb.write_misses                     7485                       # DTB write misses
+system.cpu2.dtb.flush_tlb                         276                       # Number of times complete TLB was flushed
+system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
+system.cpu2.dtb.flush_tlb_mva_asid                511                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.dtb.flush_tlb_asid                     22                       # Number of times TLB was flushed by ASID
+system.cpu2.dtb.flush_entries                    3059                       # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults                      671                       # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults                   210                       # Number of TLB faults due to prefetch
+system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
+system.cpu2.dtb.perms_faults                      417                       # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses                11099498                       # DTB read accesses
+system.cpu2.dtb.write_accesses                3386729                       # DTB write accesses
+system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
+system.cpu2.dtb.hits                         14451580                       # DTB hits
+system.cpu2.dtb.misses                          34647                       # DTB misses
+system.cpu2.dtb.accesses                     14486227                       # DTB accesses
+system.cpu2.itb.inst_hits                     3940913                       # ITB inst hits
+system.cpu2.itb.inst_misses                      4663                       # ITB inst misses
+system.cpu2.itb.read_hits                           0                       # DTB read hits
+system.cpu2.itb.read_misses                         0                       # DTB read misses
+system.cpu2.itb.write_hits                          0                       # DTB write hits
+system.cpu2.itb.write_misses                        0                       # DTB write misses
+system.cpu2.itb.flush_tlb                         276                       # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
+system.cpu2.itb.flush_tlb_mva_asid                511                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.itb.flush_tlb_asid                     22                       # Number of times TLB was flushed by ASID
+system.cpu2.itb.flush_entries                    1673                       # Number of entries that have been flushed from TLB
+system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
+system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
+system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
+system.cpu2.itb.perms_faults                     1015                       # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.read_accesses                       0                       # DTB read accesses
+system.cpu2.itb.write_accesses                      0                       # DTB write accesses
+system.cpu2.itb.inst_accesses                 3945576                       # ITB inst accesses
+system.cpu2.itb.hits                          3940913                       # DTB hits
+system.cpu2.itb.misses                           4663                       # DTB misses
+system.cpu2.itb.accesses                      3945576                       # DTB accesses
+system.cpu2.numCycles                        88228970                       # number of cpu cycles simulated
+system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu2.BPredUnit.lookups                 4678533                       # Number of BP lookups
+system.cpu2.BPredUnit.condPredicted           3809806                       # Number of conditional branches predicted
+system.cpu2.BPredUnit.condIncorrect            231267                       # Number of conditional branches incorrect
+system.cpu2.BPredUnit.BTBLookups              3069092                       # Number of BTB lookups
+system.cpu2.BPredUnit.BTBHits                 2498136                       # Number of BTB hits
+system.cpu2.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu2.BPredUnit.usedRAS                  412114                       # Number of times the RAS was used to get a target.
+system.cpu2.BPredUnit.RASInCorrect              22380                       # Number of incorrect RAS predictions.
+system.cpu2.fetch.icacheStallCycles           9360105                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                      31976282                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                    4678533                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches           2910250                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                      6786917                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                1728503                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                     53808                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.BlockedCycles              19342330                       # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles                 594                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles              913                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles        36859                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles        59251                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          389                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  3939412                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes               244088                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes                   2174                       # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples          36830548                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.047719                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.434253                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                30048718     81.59%     81.59% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  408687      1.11%     82.70% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                  492187      1.34%     84.03% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                  812698      2.21%     86.24% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  611463      1.66%     87.90% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  330922      0.90%     88.80% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                 1062958      2.89%     91.68% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  224607      0.61%     92.29% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                 2838308      7.71%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::total            36830548                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.053027                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       0.362424                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                 9885763                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             19327017                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                  6180149                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles               300885                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles               1135792                       # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved              597498                       # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred                54848                       # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts              36565818                       # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts               186819                       # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles               1135792                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                10385247                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                6621320                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles      11277395                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                  5962558                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles              1447335                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts              34838937                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                 2719                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents                250879                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents               912957                       # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.FullRegisterEvents           22201                       # Number of times there has been no free registers
+system.cpu2.rename.RenamedOperands           37227895                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups            159446068                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups       159418988                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups            27080                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps             26794485                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                10433409                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            254044                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts        230219                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                  3142941                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             6628278                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            3915406                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           518992                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          767543                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                  32164019                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             534132                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                 35030885                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            59969                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        6868407                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined     17749072                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved        150741                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples     36830548                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        0.951137                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.612264                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           24216483     65.75%     65.75% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            3835065     10.41%     76.16% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            2287291      6.21%     82.37% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            1980355      5.38%     87.75% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4            2800040      7.60%     95.35% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5            1007857      2.74%     98.09% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6             517219      1.40%     99.49% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             152490      0.41%     99.91% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8              33748      0.09%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total       36830548                       # Number of insts issued each cycle
+system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                  17662      1.14%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      1.14% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead               1415792     91.50%     92.64% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite               113850      7.36%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
+system.cpu2.iq.FU_type_0::No_OpClass            60995      0.17%      0.17% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu             19871242     56.72%     56.90% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               29695      0.08%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  5      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              5      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc           372      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            5      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead            11515486     32.87%     89.86% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            3553080     10.14%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::total              35030885                       # Type of FU issued
+system.cpu2.iq.rate                          0.397045                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                    1547304                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.044170                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads         108527324                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes         39572230                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses     28399462                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads               6790                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes              3711                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses         3127                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses              36513628                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                   3566                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          191014                       # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
+system.cpu2.iew.lsq.thread0.squashedLoads      1467031                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         2011                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         9738                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       545094                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
+system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu2.iew.lsq.thread0.rescheduledLoads      5365251                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked       332989                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
+system.cpu2.iew.iewSquashCycles               1135792                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                4899150                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles                89921                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts           32779082                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            64376                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              6628278                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             3915406                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            386018                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                 31359                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents                 2570                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          9738                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect        111294                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect        92702                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              203996                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts             34250844                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts             11286425                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           780041                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
+system.cpu2.iew.exec_nop                        80931                       # number of nop insts executed
+system.cpu2.iew.exec_refs                    14805022                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                 3673391                       # Number of branches executed
+system.cpu2.iew.exec_stores                   3518597                       # Number of stores executed
+system.cpu2.iew.exec_rate                    0.388204                       # Inst execution rate
+system.cpu2.iew.wb_sent                      33866957                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                     28402589                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                 16335424                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                 29431571                       # num instructions consuming a value
+system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
+system.cpu2.iew.wb_rate                      0.321919                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.555031                       # average fanout of values written-back
+system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu2.commit.commitSquashedInsts        6831747                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         383391                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           177223                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples     35694573                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     0.719725                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.780912                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     26969912     75.56%     75.56% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      4228252     11.85%     87.40% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1198360      3.36%     90.76% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3       616402      1.73%     92.49% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       527161      1.48%     93.96% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       311066      0.87%     94.84% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       434912      1.22%     96.05% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7       325428      0.91%     96.97% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8      1083080      3.03%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::total     35694573                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts            20797962                       # Number of instructions committed
+system.cpu2.commit.committedOps              25690260                       # Number of ops (including micro ops) committed
+system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
+system.cpu2.commit.refs                       8531559                       # Number of memory references committed
+system.cpu2.commit.loads                      5161247                       # Number of loads committed
+system.cpu2.commit.membars                      98356                       # Number of memory barriers committed
+system.cpu2.commit.branches                   3158165                       # Number of branches committed
+system.cpu2.commit.fp_insts                      3087                       # Number of committed floating point instructions.
+system.cpu2.commit.int_insts                 22900752                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              287889                       # Number of function calls committed.
+system.cpu2.commit.bw_lim_events              1083080                       # number cycles where commit BW limit reached
+system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
+system.cpu2.rob.rob_reads                    66589270                       # The number of ROB reads
+system.cpu2.rob.rob_writes                   66235051                       # The number of ROB writes
+system.cpu2.timesIdled                         359715                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                       51398422                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  3569788363                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                   20743850                       # Number of Instructions Simulated
+system.cpu2.committedOps                     25636148                       # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total             20743850                       # Number of Instructions Simulated
+system.cpu2.cpi                              4.253259                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        4.253259                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.235114                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.235114                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads               159046643                       # number of integer regfile reads
+system.cpu2.int_regfile_writes               30194860                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    22317                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   20822                       # number of floating regfile writes
+system.cpu2.misc_regfile_reads               41979427                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                278833                       # number of misc regfile writes
+system.iocache.replacements                         0                       # number of replacements
+system.iocache.tagsinuse                            0                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
+system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
+system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 925539770424                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 925539770424                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 925539770424                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 925539770424                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal
new file mode 100644
index 0000000..fa29081
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal
Binary files differ
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
new file mode 100644
index 0000000..340fc8f
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
@@ -0,0 +1,1457 @@
+[root]
+type=Root
+children=system
+full_system=true
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
+atags_addr=256
+boot_loader=/arm/scratch/sysexplr/dist/binaries/boot.arm
+boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+clock=1000
+dtb_filename=
+early_kernel_symbols=false
+enable_context_switch_stats_dump=false
+flags_addr=268435504
+gic_cpu_addr=520093952
+init_param=0
+kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+load_addr_mask=268435455
+machine_type=RealView_PBX
+mem_mode=timing
+mem_ranges=0:134217727
+memories=system.physmem system.realview.nvmem
+multi_proc=true
+num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
+readfile=tests/halt.sh
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.bridge]
+type=Bridge
+clock=1000
+delay=50000
+ranges=268435456:520093695 1073741824:1610612735
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+image_file=/arm/scratch/sysexplr/dist/disks/linux-arm-ael.img
+read_only=true
+
+[system.cpu0]
+type=DerivO3CPU
+children=dcache dtb fuPool icache interrupts isa itb tracer
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+dispatchWidth=8
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu0.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu0.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu0.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+needsTSO=false
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+predType=tournament
+profile=0
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+switched_out=false
+system=system
+tracer=system.cpu0.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=4
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+size=32768
+system=system
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu0.dtb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu0.dtb.walker
+
+[system.cpu0.dtb.walker]
+type=ArmTableWalker
+clock=500
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[3]
+
+[system.cpu0.fuPool]
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+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
+
+[system.iocache]
+type=BaseCache
+addr_ranges=0:134217727
+assoc=8
+block_size=64
+clock=1000
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+size=1024
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[25]
+mem_side=system.membus.slave[2]
+
+[system.l2c]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=8
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+size=4194304
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.membus]
+type=CoherentBus
+children=badaddr_responder
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=8
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
+slave=system.system_port system.l2c.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
+conf_table_reported=true
+in_addr_map=true
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
+null=false
+page_policy=open
+range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
+zero=false
+port=system.membus.master[2]
+
+[system.realview]
+type=RealView
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+intrctrl=system.intrctrl
+max_mem_size=268435456
+mem_start_addr=0
+pci_cfg_base=0
+system=system
+
+[system.realview.a9scu]
+type=A9SCU
+clock=1000
+pio_addr=520093696
+pio_latency=100000
+system=system
+pio=system.membus.master[5]
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268451840
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=402653184
+BAR0LegacyIO=true
+BAR0Size=16
+BAR1=402653440
+BAR1LegacyIO=true
+BAR1Size=1
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=0
+MinimumGrant=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clock=1000
+config_latency=20000
+ctrl_offset=2
+disks=system.cf0
+io_shift=1
+pci_bus=2
+pci_dev=7
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[8]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[7]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clock=1000
+gic=system.realview.gic
+int_num=55
+pio_addr=268566528
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.dmac_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268632064
+pio_latency=100000
+system=system
+pio=system.iobus.master[9]
+
+[system.realview.flash_fake]
+type=IsaFake
+clock=1000
+fake_mem=true
+pio_addr=1073741824
+pio_latency=100000
+pio_size=536870912
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[24]
+
+[system.realview.gic]
+type=Gic
+clock=1000
+cpu_addr=520093952
+cpu_pio_delay=10000
+dist_addr=520097792
+dist_pio_delay=10000
+int_latency=10000
+it_lines=128
+platform=system.realview
+system=system
+pio=system.membus.master[3]
+
+[system.realview.gpio0_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268513280
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.gpio1_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268517376
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.realview.gpio2_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268521472
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clock=1000
+gic=system.realview.gic
+int_delay=1000000
+int_num=52
+is_mouse=false
+pio_addr=268460032
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[5]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clock=1000
+gic=system.realview.gic
+int_delay=1000000
+int_num=53
+is_mouse=true
+pio_addr=268464128
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=520101888
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.membus.master[4]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clock=1000
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=520095232
+pio_latency=100000
+system=system
+pio=system.membus.master[6]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268455936
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clock=1000
+conf_table_reported=false
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2214592511
+zero=true
+port=system.membus.master[1]
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clock=1000
+idreg=0
+pio_addr=268435456
+pio_latency=100000
+proc_id0=201326592
+proc_id1=201327138
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clock=1000
+gic=system.realview.gic
+int_delay=100000
+int_num=42
+pio_addr=268529664
+pio_latency=100000
+system=system
+time=Thu Jan  1 00:00:00 2009
+pio=system.iobus.master[23]
+
+[system.realview.sci_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268492800
+pio_latency=100000
+system=system
+pio=system.iobus.master[20]
+
+[system.realview.smc_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=269357056
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=true
+pio_addr=268439552
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.ssp_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268488704
+pio_latency=100000
+system=system
+pio=system.iobus.master[19]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clock=1000
+clock0=1000000
+clock1=1000000
+gic=system.realview.gic
+int_num0=36
+int_num1=36
+pio_addr=268505088
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clock=1000
+clock0=1000000
+clock1=1000000
+gic=system.realview.gic
+int_num0=37
+int_num1=37
+pio_addr=268509184
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clock=1000
+end_on_eot=false
+gic=system.realview.gic
+int_delay=100000
+int_num=44
+pio_addr=268472320
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268476416
+pio_latency=100000
+system=system
+pio=system.iobus.master[10]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268480512
+pio_latency=100000
+system=system
+pio=system.iobus.master[11]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268484608
+pio_latency=100000
+system=system
+pio=system.iobus.master[12]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268500992
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=CoherentBus
+block_size=64
+clock=500
+header_cycles=1
+use_default_range=false
+width=8
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
+
+[system.vncserver]
+type=VncServer
+frame_capture=false
+number=0
+port=5900
+
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
new file mode 100755
index 0000000..6147a42
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
@@ -0,0 +1,18 @@
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: The clidr register always reports 0 caches.
+warn: clidr LoUIS field of 0b001 to match current ARM implementations.
+warn: The csselr register isn't implemented.
+warn: The ccsidr register isn't implemented and always reads as 0.
+warn: 	instruction 'mcr bpiallis' unimplemented
+warn: 	instruction 'mcr icialluis' unimplemented
+hack: be nice to actually delete the event here
+warn: 	instruction 'mcr dccimvac' unimplemented
+warn: 	instruction 'mcr dccmvau' unimplemented
+warn: 	instruction 'mcr icimvau' unimplemented
+warn: LCD dual screen mode not supported
+warn: 	instruction 'mcr icialluis' unimplemented
+warn: 	instruction 'mcr bpiallis' unimplemented
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout
new file mode 100755
index 0000000..5acdb72
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout
@@ -0,0 +1,2620 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Dec 11 2012 16:28:23
+gem5 started Dec 11 2012 16:28:35
+gem5 executing on e103721-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: Using bootloader at address 0x80000000
+info: Entering event queue @ 0.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1000000000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1000004500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2000004500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2000028000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 3000028000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3000031000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 4000031000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4000036000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 5000036000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5000042500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 6000042500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 6000066500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 7000066500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 7000292500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 8000292500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 8000305000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 9000305000.  Starting simulation...
+info: Entering event queue @ 9000308500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 9000313000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 10000313000.  Starting simulation...
+info: Entering event queue @ 10000329500.  Starting simulation...
+info: Entering event queue @ 10000335000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 10000339500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 11000339500.  Starting simulation...
+info: Entering event queue @ 11000385500.  Starting simulation...
+info: Entering event queue @ 11000485000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 11000489500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 12000489500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 12000495500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 13000495500.  Starting simulation...
+info: Entering event queue @ 13000512500.  Starting simulation...
+info: Entering event queue @ 13000518500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 13000523000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 14000523000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 14000526000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 15000526000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 15000544500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 16000544500.  Starting simulation...
+info: Entering event queue @ 16000649000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 16000650000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 17000650000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 17000658500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 18000658500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 26268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 27268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 36268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 37268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 46268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 47268191000.  Starting simulation...
+info: Entering event queue @ 48732715000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 48732717000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 49732717000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 49732757500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 50732757500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 50732909500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 51732909500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 51732927500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 52732927500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 52732945000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 53732945000.  Starting simulation...
+info: Entering event queue @ 53732954000.  Starting simulation...
+info: Entering event queue @ 53732958500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 53732963000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 54732963000.  Starting simulation...
+info: Entering event queue @ 54732970000.  Starting simulation...
+info: Entering event queue @ 54732980500.  Starting simulation...
+info: Entering event queue @ 54732985000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 54732986000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 55732986000.  Starting simulation...
+info: Entering event queue @ 55732994000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 55732998500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 56732998500.  Starting simulation...
+info: Entering event queue @ 56733008500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 56733013000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 57733013000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 66268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 67268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 76268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 77268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 86268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 87268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 96268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 97268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 106268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 107268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 116268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 117268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 126268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 127268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 136268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 137268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 146268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 147268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 156268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 157268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 166268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 167268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 176268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 177268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 186268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 187268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 196268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 197268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 206268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 207268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 207268194000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 208268194000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 216268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 217268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 226268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 227268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 236268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 237268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 246268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 247268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 256268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 257268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 266268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 267268191000.  Starting simulation...
+info: Entering event queue @ 276268191000.  Starting simulation...
+info: Entering event queue @ 277074505000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 277074507000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 278074507000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 286268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 287268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 296268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 297268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 306268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 307268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 316268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 317268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 326268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 327268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 336268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 337268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 346268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 347268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 356268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 357268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 366268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 367268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 376268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 377268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 386268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 387268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 396268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 397268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 406268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 407268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 416268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 417268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 426268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 427268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 436268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 437268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 446268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 447268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 456268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 457268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 466268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 467268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 476268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 477268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 486268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 487268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 496268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 497268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 506268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 507268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 516268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 517268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 526268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 527268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 536268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 537268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 546268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 547268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 556268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 557268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 566268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 567268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 576268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 577268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 586268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 587268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 596268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 597268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 606268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 607268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 616268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 617268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 626268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 627268191000.  Starting simulation...
+info: Entering event queue @ 636268191000.  Starting simulation...
+info: Entering event queue @ 637173280000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 637173282000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 638173282000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 646268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 647268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 656268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 657268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 666268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 667268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 676268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 677268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 686268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 687268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 696268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 697268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 706268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 707268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 716268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 717268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 726268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 727268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 736268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 737268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 746268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 747268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 756268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 757268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 766268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 767268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 776268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 777268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 786268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 787268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 796268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 797268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 806268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 807268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 816268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 817268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 826268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 827268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 836268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 837268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 846268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 847268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 856268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 857268191000.  Starting simulation...
+info: Entering event queue @ 866268191000.  Starting simulation...
+info: Entering event queue @ 866327182000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 866327184000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 867327184000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 876268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 877268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 886268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 887268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 896268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 897268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 906268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 907268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 916268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 917268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 926268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 927268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 936268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 937268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 946268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 947268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 956268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 957268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 966268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 967268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 976268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 977268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 986268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 987268191000.  Starting simulation...
+info: Entering event queue @ 996268191000.  Starting simulation...
+info: Entering event queue @ 997271905000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 997271907000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 998271907000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1006268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1007268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1016268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1017268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1026268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1027268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1036268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1037268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1046268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1047268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1056268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1057268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1066268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1067268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1076268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1077268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1086268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1087268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1096268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1097268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1106268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1107268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1116268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1117268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1126268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1127268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1136268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1137268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1146268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1147268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1156268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1157268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1166268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1167268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1176268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1177268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1186268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1187268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1196268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1197268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1206268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1207268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1216268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1217268191000.  Starting simulation...
+info: Entering event queue @ 1226268191000.  Starting simulation...
+info: Entering event queue @ 1226426263000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1226426265000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1227426265000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1236268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1237268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1246268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1247268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1256268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1257268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1266268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1267268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1276268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1277268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1286268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1287268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1296268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1297268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1306268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1307268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1316268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1317268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1326268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1327268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1336268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1337268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1346268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1347268191000.  Starting simulation...
+info: Entering event queue @ 1356268191000.  Starting simulation...
+info: Entering event queue @ 1357370989000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1357370991000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1358370991000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1366268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1367268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1376268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1377268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1386268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1387268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1396268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1397268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1406268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1407268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1416268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1417268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1426268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1427268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1436268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1437268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1446268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1447268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1456268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1457268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1466268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1467268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1476268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1477268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1486268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1487268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1496268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1497268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1506268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1507268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1516268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1517268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1526268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1527268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1536268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1537268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1546268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1547268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1556268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1557268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1566268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1567268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1576268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1577268191000.  Starting simulation...
+info: Entering event queue @ 1586268191000.  Starting simulation...
+info: Entering event queue @ 1586524891000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1586524893000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1587524893000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1596268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1597268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1606268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1607268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1616268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1617268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1626268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1627268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1636268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1637268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1646268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1647268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1656268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1657268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1666268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1667268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1676268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1677268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1686268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1687268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1696268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1697268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1706268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1707268191000.  Starting simulation...
+info: Entering event queue @ 1716268191000.  Starting simulation...
+info: Entering event queue @ 1717470073000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1717470075000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1718470075000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1726268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1727268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1736268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1737268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1746268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1747268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1756268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1757268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1766268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1767268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1776268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1777268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1786268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1787268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1796268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1797268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1806268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1807268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1816268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1817268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1826268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1827268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1836268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1837268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1846268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1847268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1856268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1857268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1866268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1867268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1876268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1877268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1886268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1887268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1896268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1897268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1906268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1907268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1916268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1917268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1926268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1927268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1936268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1937268191000.  Starting simulation...
+info: Entering event queue @ 1946268191000.  Starting simulation...
+info: Entering event queue @ 1946623663000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1946623665000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1947623665000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1956268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1957268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1966268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1967268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1976268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1977268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1986268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1987268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1996268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 1997268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2006268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2007268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2016268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2017268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2026268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2027268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2036268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2037268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2046268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2047268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2056268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2057268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2066268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2067268191000.  Starting simulation...
+info: Entering event queue @ 2076268191000.  Starting simulation...
+info: Entering event queue @ 2077568845000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2077568847000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2078568847000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2086268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2087268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2096268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2097268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2106268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2107268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2116268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2117268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2126268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2127268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2136268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2137268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2146268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2147268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2156268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2157268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2166268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2167268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2176268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2177268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2186268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2187268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2196268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2197268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2206268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2207268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2216268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2217268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2226268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2227268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2236268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2237268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2246268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2247268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2256268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2257268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2266268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2267268191000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2276268191000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2277268191000.  Starting simulation...
+info: Entering event queue @ 2277268954000.  Starting simulation...
+info: Entering event queue @ 2277268962000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2277268966500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2278268966500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2278269523500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2279269523500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2279269645000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2280269645000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2280269727000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2281269727000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2281270778500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2282270778500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2282270863000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2283270863000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2283277136500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2284277136500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2284277182000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2285277182000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2285277195500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2286277195500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2286277219000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2287277219000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2287277304000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2288277304000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2288277373000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2289277373000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2289277451000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2290277451000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2290285946000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2291285946000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2291286099000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2292286099000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2292286189000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2293286189000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2293286279000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2294286279000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2294286408000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2295286408000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2295286461000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2296286461000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2296286464000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2297286464000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2297286553000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2298286553000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2298286587000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2299286587000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2299286735000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2300286735000.  Starting simulation...
+info: Entering event queue @ 2300294447000.  Starting simulation...
+info: Entering event queue @ 2300294452000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2300294456500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2301294456500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2301294551000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2302294551000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2302294592000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2303294592000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2303304358000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2304304358000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2304304509000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2305304509000.  Starting simulation...
+info: Entering event queue @ 2306722747000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2306722749000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2307722749000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2307731302000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2308731302000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2308731447000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2309731447000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2309739461000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2310739461000.  Starting simulation...
+info: Entering event queue @ 2310747899500.  Starting simulation...
+info: Entering event queue @ 2310747906000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2310747910500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2311747910500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2311748072000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2312748072000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2312748081000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2313748081000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2313748138000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2314748138000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2314748214000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2315748214000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2315748327000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2316748327000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2316748378500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2317748378500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2317748526000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2318748526000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2318748667500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2319748667500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2319748721000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2320748721000.  Starting simulation...
+info: Entering event queue @ 2320749014500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2320749016000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2321749016000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2321749158000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2322749158000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2322749269000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2323749269000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2323749354500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2324749354500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2324749511000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2325749511000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2325749616000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2326749616000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2326749741000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2327749741000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2327749847000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2328749847000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2328749874000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2329749874000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2329759222000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2330759222000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2330759348000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2331759348000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2331759465500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2332759465500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2332759584500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2333759584500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2333759608000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2334759608000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2334759610500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2335759610500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2335759640000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2336759640000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2336765515000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2337765515000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2337765651000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2338765651000.  Starting simulation...
+info: Entering event queue @ 2339460421000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2339460423000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2340460423000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2340464476000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2341464476000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2341464590000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2342464590000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2342464662000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2343464662000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2343464764000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2344464764000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2344464828000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2345464828000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2345464841000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2346464841000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2346464923000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2347464923000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2347464976500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2348464976500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2348465079000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2349465079000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2349465120000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2350465120000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2350465140000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2351465140000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2351465243000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2352465243000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2352465352000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2353465352000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2353474826000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2354474826000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2354474888000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2355474888000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2355474996000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2356474996000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2356477220000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2357477220000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2357477294000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2358477294000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2358477324000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2359477324000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2359477395000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2360477395000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2360477426000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2361477426000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2361477471000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2362477471000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2362477622000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2363477622000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2363483382000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2364483382000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2364483394000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2365483394000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2365483556500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2366483556500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2366483582500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2367483582500.  Starting simulation...
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+info: Entering event queue @ 2367483684000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2368483684000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2368483745000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2369483745000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2369483898000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2370483898000.  Starting simulation...
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+info: Entering event queue @ 2370483923000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2371483923000.  Starting simulation...
+info: Entering event queue @ 2372195491000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2372195493000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2373195493000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2373195650000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2374195650000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2374195738000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2375195738000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2375195783500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2376195783500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2376195897000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2377195897000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2377202280000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2378202280000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2378202290000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2379202290000.  Starting simulation...
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+info: Entering event queue @ 2379202375500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2380202375500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2380202449000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2381202449000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2381202571000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2382202571000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2382202731000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2383202731000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2383202780000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2384202780000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2384202932000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2385202932000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2385212508000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2386212508000.  Starting simulation...
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+info: Entering event queue @ 2386212623000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2387212623000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2387212742000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2388212742000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2388213348000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2389213348000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2389215992000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2390215992000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2390216041000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2391216041000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2391216125000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2392216125000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2392216251000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2393216251000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2393216329000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2394216329000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2394216356000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2395216356000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2395216502000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2396216502000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2396216531000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2397216531000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2397216596500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2398216596500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2398216687000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2399216687000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2399216754000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2400216754000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2400216856000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2401216856000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2401216927000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2402216927000.  Starting simulation...
+info: Entering event queue @ 2402216935500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2402216940000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2403216940000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2403216956000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2404216956000.  Starting simulation...
+info: Entering event queue @ 2404931326000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2404931328000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2405931328000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2405931413000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2406931413000.  Starting simulation...
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+info: Entering event queue @ 2406934152000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2407934152000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2407934227000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2408934227000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2408934375000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2409934375000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2409934451000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2410934451000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2410934593000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2411934593000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2411934698000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2412934698000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2412934765000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2413934765000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2413934897000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2414934897000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2414934979500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2415934979500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2415935114000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2416935114000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2416935271000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2417935271000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2417935390000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2418935390000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2418935494000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2419935494000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2419935577000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2420935577000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2420935690500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2421935690500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2421935710000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2422935710000.  Starting simulation...
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+info: Entering event queue @ 2422935747000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2423935747000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2423935877000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2424935877000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2424936037000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2425936037000.  Starting simulation...
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+info: Entering event queue @ 2425936052000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2426936052000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2426943516000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2427943516000.  Starting simulation...
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+info: Entering event queue @ 2427943592000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2428943592000.  Starting simulation...
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+info: Entering event queue @ 2428943627000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2429943627000.  Starting simulation...
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+info: Entering event queue @ 2429943654000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2430943654000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2430943734000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2431943734000.  Starting simulation...
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+info: Entering event queue @ 2431947743000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2432947743000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2432947810000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2433947810000.  Starting simulation...
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+info: Entering event queue @ 2433947832500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2434947832500.  Starting simulation...
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+info: Entering event queue @ 2434947916000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2435947916000.  Starting simulation...
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+info: Entering event queue @ 2435948003500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2436948003500.  Starting simulation...
+info: Entering event queue @ 2437668382000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2437668384000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2438668384000.  Starting simulation...
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+info: Entering event queue @ 2438673856000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2439673856000.  Starting simulation...
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+info: Entering event queue @ 2439673903000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2440673903000.  Starting simulation...
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+info: Entering event queue @ 2440673981000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2441673981000.  Starting simulation...
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+info: Entering event queue @ 2441674104000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2442674104000.  Starting simulation...
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+info: Entering event queue @ 2442674129000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2443674129000.  Starting simulation...
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+info: Entering event queue @ 2443683664000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2444683664000.  Starting simulation...
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+info: Entering event queue @ 2444683754000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2445683754000.  Starting simulation...
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+info: Entering event queue @ 2445683860000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2446683860000.  Starting simulation...
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+info: Entering event queue @ 2446685588000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2447685588000.  Starting simulation...
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+info: Entering event queue @ 2447685601000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2448685601000.  Starting simulation...
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+info: Entering event queue @ 2448685693000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2449685693000.  Starting simulation...
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+info: Entering event queue @ 2449685842000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2450685842000.  Starting simulation...
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+info: Entering event queue @ 2450685955000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2451685955000.  Starting simulation...
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+info: Entering event queue @ 2451686091000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2452686091000.  Starting simulation...
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+info: Entering event queue @ 2452686250000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2453686250000.  Starting simulation...
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+info: Entering event queue @ 2453686372000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2454686372000.  Starting simulation...
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+info: Entering event queue @ 2454686459500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2455686459500.  Starting simulation...
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+info: Entering event queue @ 2455686603500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2456686603500.  Starting simulation...
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+info: Entering event queue @ 2456686628000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2457686628000.  Starting simulation...
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+info: Entering event queue @ 2457686754000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2458686754000.  Starting simulation...
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+info: Entering event queue @ 2458686874000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2459686874000.  Starting simulation...
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+info: Entering event queue @ 2459686985000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2460686985000.  Starting simulation...
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+info: Entering event queue @ 2460696452000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2461696452000.  Starting simulation...
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+info: Entering event queue @ 2461696525000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2462696525000.  Starting simulation...
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+info: Entering event queue @ 2462696666000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2463696666000.  Starting simulation...
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+info: Entering event queue @ 2463696803000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2464696803000.  Starting simulation...
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+info: Entering event queue @ 2464696917000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2465696917000.  Starting simulation...
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+info: Entering event queue @ 2465696991000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2466696991000.  Starting simulation...
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+info: Entering event queue @ 2466697129000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2467697129000.  Starting simulation...
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+info: Entering event queue @ 2467697268000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2468697268000.  Starting simulation...
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+info: Entering event queue @ 2468697299000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2469697299000.  Starting simulation...
+info: Entering event queue @ 2470404073000.  Starting simulation...
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+info: Entering event queue @ 2470404075000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2471404075000.  Starting simulation...
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+info: Entering event queue @ 2471404234000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2472404234000.  Starting simulation...
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+info: Entering event queue @ 2472404348000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2473404348000.  Starting simulation...
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+info: Entering event queue @ 2473404470000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2474404470000.  Starting simulation...
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+info: Entering event queue @ 2474404541000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2475404541000.  Starting simulation...
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+info: Entering event queue @ 2475404619000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2476404619000.  Starting simulation...
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+info: Entering event queue @ 2476404761000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2477404761000.  Starting simulation...
+info: Entering event queue @ 2477404786000.  Starting simulation...
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+info: Entering event queue @ 2477404817001.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2478404817001.  Starting simulation...
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+info: Entering event queue @ 2478413072000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2479413072000.  Starting simulation...
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+info: Entering event queue @ 2479413078500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2480413078500.  Starting simulation...
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+info: Entering event queue @ 2480413215000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2481413215000.  Starting simulation...
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+info: Entering event queue @ 2481413366000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2482413366000.  Starting simulation...
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+info: Entering event queue @ 2482413479000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2483413479000.  Starting simulation...
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+info: Entering event queue @ 2483413611000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2484413611000.  Starting simulation...
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+info: Entering event queue @ 2484413694000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2485413694000.  Starting simulation...
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+info: Entering event queue @ 2485413825000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2486413825000.  Starting simulation...
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+info: Entering event queue @ 2486413864000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2487413864000.  Starting simulation...
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+info: Entering event queue @ 2487413989500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2488413989500.  Starting simulation...
+info: Entering event queue @ 2488416129000.  Starting simulation...
+info: Entering event queue @ 2488416134000.  Starting simulation...
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+info: Entering event queue @ 2488416138500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2489416138500.  Starting simulation...
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+info: Entering event queue @ 2489419771500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2490419771500.  Starting simulation...
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+info: Entering event queue @ 2490419777000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2491419777000.  Starting simulation...
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+info: Entering event queue @ 2491419813500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2492419813500.  Starting simulation...
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+info: Entering event queue @ 2492419840500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2493419840500.  Starting simulation...
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+info: Entering event queue @ 2493419949500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2494419949500.  Starting simulation...
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+info: Entering event queue @ 2494419968000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2495419968000.  Starting simulation...
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+info: Entering event queue @ 2495420066000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2496420066000.  Starting simulation...
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+info: Entering event queue @ 2496428599000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2497428599000.  Starting simulation...
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+info: Entering event queue @ 2497428730000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2498428730000.  Starting simulation...
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+info: Entering event queue @ 2498428793000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2499428793000.  Starting simulation...
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+info: Entering event queue @ 2499428883000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2500428883000.  Starting simulation...
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+info: Entering event queue @ 2500428926000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2501428926000.  Starting simulation...
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+info: Entering event queue @ 2501428958500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2502428958500.  Starting simulation...
+info: Entering event queue @ 2503141891000.  Starting simulation...
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+info: Entering event queue @ 2503141893000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2504141893000.  Starting simulation...
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+info: Entering event queue @ 2504141911000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2505141911000.  Starting simulation...
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+info: Entering event queue @ 2505141987000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2506141987000.  Starting simulation...
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+info: Entering event queue @ 2506142106000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2507142106000.  Starting simulation...
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+info: Entering event queue @ 2507150640000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2508150640000.  Starting simulation...
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+info: Entering event queue @ 2508150650000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2509150650000.  Starting simulation...
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+info: Entering event queue @ 2509159425000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2510159425000.  Starting simulation...
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+info: Entering event queue @ 2510159522000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2511159522000.  Starting simulation...
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+info: Entering event queue @ 2511159638000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2512159638000.  Starting simulation...
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+info: Entering event queue @ 2512159774000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2513159774000.  Starting simulation...
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+info: Entering event queue @ 2513159867000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2514159867000.  Starting simulation...
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+info: Entering event queue @ 2514169302000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2515169302000.  Starting simulation...
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+info: Entering event queue @ 2515169394000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2516169394000.  Starting simulation...
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+info: Entering event queue @ 2516169545000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2517169545000.  Starting simulation...
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+info: Entering event queue @ 2517178449000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2518178449000.  Starting simulation...
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+info: Entering event queue @ 2518178548000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2519178548000.  Starting simulation...
+info: Entering event queue @ 2519180509500.  Starting simulation...
+info: Entering event queue @ 2519180519000.  Starting simulation...
+info: Entering event queue @ 2519180523500.  Starting simulation...
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+info: Entering event queue @ 2519180524500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2520180524500.  Starting simulation...
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+info: Entering event queue @ 2520180668000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2521180668000.  Starting simulation...
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+info: Entering event queue @ 2521180817000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2522180817000.  Starting simulation...
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+info: Entering event queue @ 2522180935500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2523180935500.  Starting simulation...
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+info: Entering event queue @ 2523180954000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2524180954000.  Starting simulation...
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+info: Entering event queue @ 2524181013000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2525181013000.  Starting simulation...
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+info: Entering event queue @ 2525181146000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2526181146000.  Starting simulation...
+info: Entering event queue @ 2526181160000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2526181162500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2527181162500.  Starting simulation...
+info: Entering event queue @ 2527181171500.  Starting simulation...
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+info: Entering event queue @ 2527181177000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2528181177000.  Starting simulation...
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+info: Entering event queue @ 2528181181000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2529181181000.  Starting simulation...
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+info: Entering event queue @ 2529181185500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2530181185500.  Starting simulation...
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+info: Entering event queue @ 2530181301000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2531181301000.  Starting simulation...
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+info: Entering event queue @ 2531181304500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2532181304500.  Starting simulation...
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+info: Entering event queue @ 2532181308000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2533181308000.  Starting simulation...
+info: Entering event queue @ 2533181317000.  Starting simulation...
+info: Entering event queue @ 2533181327000.  Starting simulation...
+info: Entering event queue @ 2533181337500.  Starting simulation...
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+info: Entering event queue @ 2533181338000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2534181338000.  Starting simulation...
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+info: Entering event queue @ 2534181592000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2535181592000.  Starting simulation...
+info: Entering event queue @ 2535877726000.  Starting simulation...
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+info: Entering event queue @ 2535877728000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2536877728000.  Starting simulation...
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+info: Entering event queue @ 2536877880500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2537877880500.  Starting simulation...
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+info: Entering event queue @ 2537877967000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2538877967000.  Starting simulation...
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+info: Entering event queue @ 2538877971000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2539877971000.  Starting simulation...
+info: Entering event queue @ 2539877977500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2539877982000.  Starting simulation...
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
new file mode 100644
index 0000000..b8d7124
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
@@ -0,0 +1,1684 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  2.540587                       # Number of seconds simulated
+sim_ticks                                2540587123500                       # Number of ticks simulated
+final_tick                               2540587123500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                  67374                       # Simulator instruction rate (inst/s)
+host_op_rate                                    86663                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2824409714                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 407052                       # Number of bytes of host memory used
+host_seconds                                   899.51                       # Real time elapsed on the host
+sim_insts                                    60603607                       # Number of instructions simulated
+sim_ops                                      77954043                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker         2048                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           521152                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4740560                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          576                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           279808                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4349656                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            131004456                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       521152                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       279808                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          800960                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3783104                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data       1619508                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data       1396592                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6799204                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker           32                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst              8143                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             74105                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker            9                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              4372                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             67969                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15293448                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           59111                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data           404877                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data           349148                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               813136                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47670291                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker           806                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              205131                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1865931                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           227                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              110135                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1712067                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51564638                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         205131                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         110135                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             315266                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1489067                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data             637454                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data             549712                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2676233                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1489067                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47670291                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          806                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             205131                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            2503385                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          227                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             110135                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            2261780                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               54240872                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      15293448                       # Total number of read requests seen
+system.physmem.writeReqs                       813136                       # Total number of write requests seen
+system.physmem.cpureqs                         218391                       # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead                    978780672                       # Total number of bytes read from memory
+system.physmem.bytesWritten                  52040704                       # Total number of bytes written to memory
+system.physmem.bytesConsumedRd              131004456                       # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr                6799204                       # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ                       10                       # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite               4690                       # Reqs where no action is needed
+system.physmem.perBankRdReqs::0                955907                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1                956222                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2                955717                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3                955757                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4                955661                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5                955544                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6                955404                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7                955585                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8                956056                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9                955920                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10               955992                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11               955944                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12               956032                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13               955927                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14               956056                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15               955714                       # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0                 50106                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1                 50364                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2                 49972                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3                 50036                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4                 50909                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5                 50827                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6                 50676                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7                 50834                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8                 51139                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9                 51219                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10                51120                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11                51083                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12                51352                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13                51170                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14                51298                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15                51031                       # Track writes on a per bank basis
+system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry                      677160                       # Number of times wr buffer was full causing retry
+system.physmem.totGap                    2540585876000                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::2                      42                       # Categorize read packet sizes
+system.physmem.readPktSize::3                15138816                       # Categorize read packet sizes
+system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::6                  154590                       # Categorize read packet sizes
+system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
+system.physmem.writePktSize::0                      0                       # categorize write packet sizes
+system.physmem.writePktSize::1                      0                       # categorize write packet sizes
+system.physmem.writePktSize::2                1431185                       # categorize write packet sizes
+system.physmem.writePktSize::3                      0                       # categorize write packet sizes
+system.physmem.writePktSize::4                      0                       # categorize write packet sizes
+system.physmem.writePktSize::5                      0                       # categorize write packet sizes
+system.physmem.writePktSize::6                  59111                       # categorize write packet sizes
+system.physmem.writePktSize::7                      0                       # categorize write packet sizes
+system.physmem.writePktSize::8                      0                       # categorize write packet sizes
+system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::6                 4690                       # categorize neither packet sizes
+system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
+system.physmem.rdQLenPdf::0                   1056941                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    992282                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    949580                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    983982                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                   2774748                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                   2777750                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   5475537                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     36612                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     30094                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                     29956                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                    29864                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                    57737                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    31653                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    59391                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                     5382                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                     1868                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       40                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       15                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0                      3640                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                      3716                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                      3825                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                      4020                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                      4294                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                      4489                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                      4657                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                      4830                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                      5057                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                     35378                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                    35366                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                    35349                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                    35330                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                    35318                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                    35309                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    35299                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    35283                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    35274                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    35255                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    35245                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    35237                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    35231                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    35222                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    31866                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    31776                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    31654                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    31445                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    31156                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    30947                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    30761                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    30573                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    30334                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.totQLat                   295225090687                       # Total cycles spent in queuing delays
+system.physmem.totMemAccLat              372543516687                       # Sum of mem lat for all requests
+system.physmem.totBusLat                  61173752000                       # Total cycles spent in databus access
+system.physmem.totBankLat                 16144674000                       # Total cycles spent in bank access
+system.physmem.avgQLat                       19304.04                       # Average queueing delay per request
+system.physmem.avgBankLat                     1055.66                       # Average bank access latency per request
+system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
+system.physmem.avgMemAccLat                  24359.70                       # Average memory access latency
+system.physmem.avgRdBW                         385.26                       # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW                          20.48                       # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW                  51.56                       # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW                   2.68                       # Average consumed write bandwidth in MB/s
+system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil                           2.54                       # Data bus utilization in percentage
+system.physmem.avgRdQLen                         0.15                       # Average read queue length over time
+system.physmem.avgWrQLen                         1.12                       # Average write queue length over time
+system.physmem.readRowHits                   15250784                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    786076                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   99.72                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  96.67                       # Row buffer hit rate for writes
+system.physmem.avgGap                       157735.86                       # Average gap between requests
+system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst           25                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst           25                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                         64360                       # number of replacements
+system.l2c.tagsinuse                     51403.610979                       # Cycle average of tags in use
+system.l2c.total_refs                         1940230                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        129752                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         14.953373                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                  2504468947000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        36917.340991                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.dtb.walker      20.674010                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.itb.walker       0.000348                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          5181.760660                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          3292.636698                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.dtb.walker       8.768373                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst          3037.851423                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data          2944.578476                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.563314                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.dtb.walker      0.000315                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.079067                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.050242                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.dtb.walker      0.000134                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.046354                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.044931                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.784357                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.dtb.walker        52210                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         7522                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             501648                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             201746                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        46118                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         6836                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             471830                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             185683                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1473593                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          608099                       # number of Writeback hits
+system.l2c.Writeback_hits::total               608099                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data              20                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              20                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  40                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data             6                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data             6                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                12                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            57007                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            55991                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               112998                       # number of ReadExReq hits
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+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.985316                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.986413                       # miss rate for UpgradeReq accesses
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+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
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+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
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+system.l2c.UpgradeReq_mshr_misses::cpu1.data         1342                       # number of UpgradeReq MSHR misses
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+system.l2c.overall_mshr_misses::total          156257                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      1865559                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        93002                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    318411185                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data    250751004                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       504018                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    178311078                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    193087266                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total    943023112                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     15680528                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     13422342                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     29102870                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        10001                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total        10001                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2929616476                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   2170341063                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5099957539                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      1865559                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        93002                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    318411185                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   3180367480                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       504018                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    178311078                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   2363428329                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   6042980651                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      1865559                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        93002                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    318411185                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   3180367480                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       504018                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    178311078                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   2363428329                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   6042980651                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      4312653                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  83955529530                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  83016717004                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 166976559187                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   8488186790                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   5709859144                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  14198045934                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data        76004                       # number of LoadLockedReq MSHR uncacheable cycles
+system.l2c.LoadLockedReq_mshr_uncacheable_latency::total        76004                       # number of LoadLockedReq MSHR uncacheable cycles
+system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data        30003                       # number of StoreCondReq MSHR uncacheable cycles
+system.l2c.StoreCondReq_mshr_uncacheable_latency::total        30003                       # number of StoreCondReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      4312653                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data  92443716320                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data  88726576148                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 181174605121                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000613                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000266                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015745                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.029749                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000195                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.009181                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.023468                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.015427                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.987358                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.985316                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.986413                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.142857                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.076923                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.547060                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.534591                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.540966                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000613                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000266                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015745                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.224784                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000195                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.009181                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.221522                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.089652                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000613                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000266                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015745                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.224784                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000195                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.009181                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.221522                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.089652                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 58298.718750                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        46501                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39677.406231                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40528.689834                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        56002                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40784.784538                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 43264.007618                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40841.191511                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10038.750320                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.745156                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10021.649449                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42548.857363                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 33746.012734                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 38297.457621                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 58298.718750                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        46501                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39677.406231                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 42382.295842                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        56002                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40784.784538                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 34363.643791                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 38673.343601                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 58298.718750                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        46501                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39677.406231                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 42382.295842                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        56002                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40784.784538                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 34363.643791                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 38673.343601                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average LoadLockedReq mshr uncacheable latency
+system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total          inf                       # average LoadLockedReq mshr uncacheable latency
+system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average StoreCondReq mshr uncacheable latency
+system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total          inf                       # average StoreCondReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
+system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
+system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
+system.cpu0.dtb.read_hits                    26104138                       # DTB read hits
+system.cpu0.dtb.read_misses                     45655                       # DTB read misses
+system.cpu0.dtb.write_hits                    6173225                       # DTB write hits
+system.cpu0.dtb.write_misses                    11582                       # DTB write misses
+system.cpu0.dtb.flush_tlb                         257                       # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid                737                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                    8687                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1569                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                   298                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults                      666                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                26149793                       # DTB read accesses
+system.cpu0.dtb.write_accesses                6184807                       # DTB write accesses
+system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
+system.cpu0.dtb.hits                         32277363                       # DTB hits
+system.cpu0.dtb.misses                          57237                       # DTB misses
+system.cpu0.dtb.accesses                     32334600                       # DTB accesses
+system.cpu0.itb.inst_hits                     6054056                       # ITB inst hits
+system.cpu0.itb.inst_misses                      7505                       # ITB inst misses
+system.cpu0.itb.read_hits                           0                       # DTB read hits
+system.cpu0.itb.read_misses                         0                       # DTB read misses
+system.cpu0.itb.write_hits                          0                       # DTB write hits
+system.cpu0.itb.write_misses                        0                       # DTB write misses
+system.cpu0.itb.flush_tlb                         257                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid                737                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                    2789                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
+system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
+system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
+system.cpu0.itb.perms_faults                     1640                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.read_accesses                       0                       # DTB read accesses
+system.cpu0.itb.write_accesses                      0                       # DTB write accesses
+system.cpu0.itb.inst_accesses                 6061561                       # ITB inst accesses
+system.cpu0.itb.hits                          6054056                       # DTB hits
+system.cpu0.itb.misses                           7505                       # DTB misses
+system.cpu0.itb.accesses                      6061561                       # DTB accesses
+system.cpu0.numCycles                       240389950                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.BPredUnit.lookups                 7650447                       # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted           6071769                       # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect            390619                       # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups              4963412                       # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits                 4056247                       # Number of BTB hits
+system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu0.BPredUnit.usedRAS                  744385                       # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.RASInCorrect              39840                       # Number of incorrect RAS predictions.
+system.cpu0.fetch.icacheStallCycles          15652124                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      47554546                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                    7650447                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           4800632                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     10611377                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                2494725                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                     89565                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles              50696365                       # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles                1823                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles             1967                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles        55574                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       106827                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          232                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  6051824                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               344537                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   3471                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples          78943853                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.750152                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.105781                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                68340077     86.57%     86.57% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  702129      0.89%     87.46% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                  881040      1.12%     88.57% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                 1224383      1.55%     90.12% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 1120463      1.42%     91.54% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  584523      0.74%     92.28% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                 1319074      1.67%     93.95% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  413717      0.52%     94.48% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4358447      5.52%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::total            78943853                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.031825                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.197823                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                16656979                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             50446432                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                  9625401                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles               575149                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1637749                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved             1050019                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                92865                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              56438894                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               312308                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1637749                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                17559275                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               19379590                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      27710296                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                  9215944                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              3438937                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              54038405                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                14132                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                614041                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents              2240889                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents           19821                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands           55994087                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            246350981                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       246302367                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups            48614                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             41407239                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                14586848                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts            463494                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        411765                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                  6993142                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            10396030                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            7010506                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1100529                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         1298753                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  50240617                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1080191                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 63997387                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            98424                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       10068381                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     24718063                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        263130                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples     78943853                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.810670                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.516651                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           55721215     70.58%     70.58% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1            7438559      9.42%     80.01% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            3764189      4.77%     84.77% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            3138828      3.98%     88.75% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            6266578      7.94%     96.69% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1507037      1.91%     98.60% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             806867      1.02%     99.62% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             233373      0.30%     99.91% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8              67207      0.09%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total       78943853                       # Number of insts issued each cycle
+system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                  28850      0.65%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     4      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      0.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               4202057     94.56%     95.21% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               212765      4.79%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
+system.cpu0.iq.FU_type_0::No_OpClass           196420      0.31%      0.31% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             30502224     47.66%     47.97% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               49600      0.08%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                 11      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 1      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              8      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc          1274      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            8      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            26758229     41.81%     89.86% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            6489612     10.14%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::total              63997387                       # Type of FU issued
+system.cpu0.iq.rate                          0.266223                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                    4443676                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.069435                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         211525282                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         61397992                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     45248586                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              12498                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes              6745                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         5570                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              68238014                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                   6629                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          331719                       # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
+system.cpu0.iew.lsq.thread0.squashedLoads      2183838                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         4014                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        16143                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       861796                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
+system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu0.iew.lsq.thread0.rescheduledLoads     17073193                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       345280                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
+system.cpu0.iew.iewSquashCycles               1637749                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               14492701                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               245337                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           51437500                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           107423                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts             10396030                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             7010506                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            766368                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 62240                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents                 3660                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         16143                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        190401                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       151763                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              342164                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             62995358                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             26449087                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          1002029                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
+system.cpu0.iew.exec_nop                       116692                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    32879818                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 6078109                       # Number of branches executed
+system.cpu0.iew.exec_stores                   6430731                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.262055                       # Inst execution rate
+system.cpu0.iew.wb_sent                      62497341                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     45254156                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 24800882                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 45441474                       # num instructions consuming a value
+system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
+system.cpu0.iew.wb_rate                      0.188253                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.545776                       # average fanout of values written-back
+system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu0.commit.commitSquashedInsts        9944794                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         817061                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           299135                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples     77306104                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.530438                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.512152                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     62653127     81.05%     81.05% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      7139643      9.24%     90.28% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      2117433      2.74%     93.02% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      1152491      1.49%     94.51% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1052620      1.36%     95.87% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       581358      0.75%     96.62% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       718590      0.93%     97.55% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       381418      0.49%     98.05% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1509424      1.95%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::total     77306104                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            32015395                       # Number of instructions committed
+system.cpu0.commit.committedOps              41006110                       # Number of ops (including micro ops) committed
+system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
+system.cpu0.commit.refs                      14360902                       # Number of memory references committed
+system.cpu0.commit.loads                      8212192                       # Number of loads committed
+system.cpu0.commit.membars                     221881                       # Number of memory barriers committed
+system.cpu0.commit.branches                   5266033                       # Number of branches committed
+system.cpu0.commit.fp_insts                      5497                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 36294613                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              520344                       # Number of function calls committed.
+system.cpu0.commit.bw_lim_events              1509424                       # number cycles where commit BW limit reached
+system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
+system.cpu0.rob.rob_reads                   125738503                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  103590706                       # The number of ROB writes
+system.cpu0.timesIdled                         892654                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                      161446097                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  2255175331                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   31936467                       # Number of Instructions Simulated
+system.cpu0.committedOps                     40927182                       # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total             31936467                       # Number of Instructions Simulated
+system.cpu0.cpi                              7.527130                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        7.527130                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.132853                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.132853                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               285784738                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               46365180                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                    22828                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                   19904                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads               64493667                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                471303                       # number of misc regfile writes
+system.cpu0.icache.replacements                986601                       # number of replacements
+system.cpu0.icache.tagsinuse               511.585602                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                10225858                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                987113                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                 10.359359                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle            6782112000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst   321.917069                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_blocks::cpu1.inst   189.668533                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.628744                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::cpu1.inst     0.370446                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.999191                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst      5498991                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst      4726867                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       10225858                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst      5498991                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst      4726867                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        10225858                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst      5498991                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst      4726867                       # number of overall hits
+system.cpu0.icache.overall_hits::total       10225858                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       552708                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       515964                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1068672                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       552708                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       515964                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1068672                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       552708                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       515964                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1068672                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7467633494                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   6811010992                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  14278644486                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   7467633494                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   6811010992                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  14278644486                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   7467633494                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   6811010992                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  14278644486                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      6051699                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst      5242831                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     11294530                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst      6051699                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst      5242831                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     11294530                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      6051699                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst      5242831                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     11294530                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.091331                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.098413                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.094619                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.091331                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.098413                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.094619                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.091331                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.098413                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.094619                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13510.992231                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13200.554674                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13361.110318                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13510.992231                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13200.554674                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13361.110318                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13510.992231                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13200.554674                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13361.110318                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         4485                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets          398                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              340                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              1                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.191176                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          398                       # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        42344                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        39180                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        81524                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        42344                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu1.inst        39180                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        81524                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        42344                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu1.inst        39180                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        81524                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       510364                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       476784                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       987148                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       510364                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       476784                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       987148                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       510364                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       476784                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       987148                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   6084165494                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   5553411993                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  11637577487                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   6084165494                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   5553411993                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  11637577487                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   6084165494                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   5553411993                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  11637577487                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      6767000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      6767000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      6767000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total      6767000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.084334                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.090940                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.087401                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.084334                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.090940                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.087401                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.084334                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.090940                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.087401                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11921.227779                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11647.647557                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11789.090883                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11921.227779                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11647.647557                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11789.090883                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11921.227779                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11647.647557                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11789.090883                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.replacements                643795                       # number of replacements
+system.cpu0.dcache.tagsinuse               511.994133                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                21730635                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs                644307                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                 33.727144                       # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle              36157000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::cpu0.data   255.754263                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_blocks::cpu1.data   256.239870                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.499520                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::cpu1.data     0.500468                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.999989                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data      7320998                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      6545083                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       13866081                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3839440                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      3452761                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       7292201                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       142548                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       140954                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       283502                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       144156                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data       141612                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       285768                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     11160438                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      9997844                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        21158282                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     11160438                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      9997844                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       21158282                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       376773                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       369451                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       746224                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1505844                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data      1453809                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      2959653                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         7530                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         6140                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        13670                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data            6                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu1.data            7                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total           13                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      1882617                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data      1823260                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       3705877                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1882617                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data      1823260                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      3705877                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5747755000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   5402696500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  11150451500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  63541262289                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  51082353349                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 114623615638                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    104538500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     81673500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    186212000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        78000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       103000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total       181000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  69289017289                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  56485049849                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 125774067138                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  69289017289                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data  56485049849                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 125774067138                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      7697771                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      6914534                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     14612305                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5345284                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      4906570                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     10251854                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       150078                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       147094                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       297172                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       144162                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       141619                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       285781                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     13043055                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     11821104                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     24864159                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     13043055                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     11821104                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     24864159                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.048946                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.053431                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.051068                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.281714                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.296298                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.288694                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.050174                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.041742                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.046000                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000042                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000049                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000045                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.144339                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.154238                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.149045                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.144339                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.154238                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.149045                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15255.219987                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14623.580664                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14942.499169                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42196.444179                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35136.908183                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 38728.734631                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13882.934927                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13301.872964                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13621.945867                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        13000                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 14714.285714                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13923.076923                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36804.627436                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 30980.249580                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 33939.083013                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36804.627436                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30980.249580                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 33939.083013                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs        35448                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        12573                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs             3421                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            258                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    10.361882                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    48.732558                       # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.dcache.writebacks::writebacks       608099                       # number of writebacks
+system.cpu0.dcache.writebacks::total           608099                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       175511                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       184666                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       360177                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1378456                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1332180                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      2710636                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          766                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data          717                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1483                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1553967                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data      1516846                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      3070813                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1553967                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data      1516846                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      3070813                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       201262                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       184785                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       386047                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       127388                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       121629                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       249017                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6764                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5423                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        12187                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            6                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            7                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           13                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       328650                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       306414                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       635064                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       328650                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       306414                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       635064                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2736355500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2446708500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5183064000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4640301429                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   3791272989                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8431574418                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     82236000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     62703500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    144939500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        66000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        89000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       155000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7376656929                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   6237981489                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  13614638418                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7376656929                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   6237981489                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  13614638418                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  91682874000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  90682822000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182365696000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  13814824895                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  10281264593                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  24096089488                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data       118000                       # number of LoadLockedReq MSHR uncacheable cycles
+system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total       118000                       # number of LoadLockedReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data        69000                       # number of StoreCondReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total        69000                       # number of StoreCondReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105497698895                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 100964086593                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 206461785488                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.026145                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.026724                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.026419                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023832                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.024789                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.024290                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.045070                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.036868                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.041010                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000042                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000049                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000045                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.025197                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.025921                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.025541                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.025197                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.025921                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.025541                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13595.986823                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13240.839354                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13425.992172                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36426.519209                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31170.797992                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33859.432962                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12157.894737                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11562.511525                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11892.959711                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        11000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 12714.285714                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11923.076923                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22445.327640                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20358.017222                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21438.214759                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22445.327640                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20358.017222                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21438.214759                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average LoadLockedReq mshr uncacheable latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total          inf                       # average LoadLockedReq mshr uncacheable latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average StoreCondReq mshr uncacheable latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total          inf                       # average StoreCondReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
+system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
+system.cpu1.dtb.read_hits                    25160982                       # DTB read hits
+system.cpu1.dtb.read_misses                     40128                       # DTB read misses
+system.cpu1.dtb.write_hits                    5622181                       # DTB write hits
+system.cpu1.dtb.write_misses                     9250                       # DTB write misses
+system.cpu1.dtb.flush_tlb                         254                       # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid                702                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                    7925                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                     1386                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   276                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
+system.cpu1.dtb.perms_faults                      627                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                25201110                       # DTB read accesses
+system.cpu1.dtb.write_accesses                5631431                       # DTB write accesses
+system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
+system.cpu1.dtb.hits                         30783163                       # DTB hits
+system.cpu1.dtb.misses                          49378                       # DTB misses
+system.cpu1.dtb.accesses                     30832541                       # DTB accesses
+system.cpu1.itb.inst_hits                     5244962                       # ITB inst hits
+system.cpu1.itb.inst_misses                      6670                       # ITB inst misses
+system.cpu1.itb.read_hits                           0                       # DTB read hits
+system.cpu1.itb.read_misses                         0                       # DTB read misses
+system.cpu1.itb.write_hits                          0                       # DTB write hits
+system.cpu1.itb.write_misses                        0                       # DTB write misses
+system.cpu1.itb.flush_tlb                         254                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid                702                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                    2650                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
+system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
+system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
+system.cpu1.itb.perms_faults                     1456                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.read_accesses                       0                       # DTB read accesses
+system.cpu1.itb.write_accesses                      0                       # DTB write accesses
+system.cpu1.itb.inst_accesses                 5251632                       # ITB inst accesses
+system.cpu1.itb.hits                          5244962                       # DTB hits
+system.cpu1.itb.misses                           6670                       # DTB misses
+system.cpu1.itb.accesses                      5251632                       # DTB accesses
+system.cpu1.numCycles                       232013377                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.BPredUnit.lookups                 6790425                       # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted           5410391                       # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect            343130                       # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups              4365867                       # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits                 3552399                       # Number of BTB hits
+system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu1.BPredUnit.usedRAS                  675836                       # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.RASInCorrect              35150                       # Number of incorrect RAS predictions.
+system.cpu1.fetch.icacheStallCycles          14219364                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      41265528                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    6790425                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           4228235                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                      9330468                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                2101425                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                     82678                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles              47674573                       # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles                1053                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles             1954                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles        48379                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles        99398                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles          108                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  5242833                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               267586                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   2984                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples          72923984                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.712246                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.058401                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                63601422     87.22%     87.22% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  651379      0.89%     88.11% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  811870      1.11%     89.22% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 1013874      1.39%     90.61% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                  943793      1.29%     91.91% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  538574      0.74%     92.65% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 1195574      1.64%     94.29% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  358365      0.49%     94.78% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 3809133      5.22%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::total            72923984                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.029267                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.177858                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                15065111                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             47459427                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  8508787                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               504767                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               1383740                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              935366                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred                84721                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              49702311                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts               283407                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               1383740                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                15832821                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               18424865                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      25966015                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  8176580                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              3137893                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              47902393                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                 7520                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                511770                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents              2112759                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents           14566                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands           49459920                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            218567938                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       218526163                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups            41775                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             37332689                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                12127230                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            420234                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts        377586                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  6217035                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             9300150                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            6339076                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           983520                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         1172387                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  44745095                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             970903                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 59171295                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            83947                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        8398889                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     19786111                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        243126                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     72923984                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.811411                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.516236                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           51567769     70.71%     70.71% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            6722785      9.22%     79.93% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            3414540      4.68%     84.62% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            2860255      3.92%     88.54% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            6054704      8.30%     96.84% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5            1326273      1.82%     98.66% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6             714361      0.98%     99.64% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7             204058      0.28%     99.92% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8              59239      0.08%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       72923984                       # Number of insts issued each cycle
+system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                  24658      0.56%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     2      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               4170684     95.00%     95.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               195004      4.44%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
+system.cpu1.iq.FU_type_0::No_OpClass           167246      0.28%      0.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             27298169     46.13%     46.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               44245      0.07%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  6      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              3      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc           839      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            3      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     46.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            25732684     43.49%     89.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            5928100     10.02%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::total              59171295                       # Type of FU issued
+system.cpu1.iq.rate                          0.255034                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    4390348                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.074197                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         195779484                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         54123667                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     40860194                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads              10578                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              5727                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         4726                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              63388772                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   5625                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          295886                       # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
+system.cpu1.iew.lsq.thread0.squashedLoads      1794199                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         2827                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation        15001                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       687985                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
+system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu1.iew.lsq.thread0.rescheduledLoads     17035415                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked       238532                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
+system.cpu1.iew.iewSquashCycles               1383740                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles               13800740                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               226965                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           45822265                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts            96960                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts              9300150                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             6339076                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            695770                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 48787                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents                 3997                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents         15001                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect        167673                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       132287                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              299960                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             58435443                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             25502557                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           735852                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
+system.cpu1.iew.exec_nop                       106267                       # number of nop insts executed
+system.cpu1.iew.exec_refs                    31379358                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 5453104                       # Number of branches executed
+system.cpu1.iew.exec_stores                   5876801                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.251862                       # Inst execution rate
+system.cpu1.iew.wb_sent                      58051293                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     40864920                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 22407090                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 41228321                       # num instructions consuming a value
+system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
+system.cpu1.iew.wb_rate                      0.176132                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.543488                       # average fanout of values written-back
+system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu1.commit.commitSquashedInsts        8312194                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         727777                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           259619                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     71540244                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.518566                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.491714                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     58151016     81.28%     81.28% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      6627858      9.26%     90.55% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      1880092      2.63%     93.18% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3      1040741      1.45%     94.63% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       983750      1.38%     96.01% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       494100      0.69%     96.70% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       697389      0.97%     97.67% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       324169      0.45%     98.13% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8      1341129      1.87%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::total     71540244                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            28738593                       # Number of instructions committed
+system.cpu1.commit.committedOps              37098314                       # Number of ops (including micro ops) committed
+system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
+system.cpu1.commit.refs                      13157042                       # Number of memory references committed
+system.cpu1.commit.loads                      7505951                       # Number of loads committed
+system.cpu1.commit.membars                     191336                       # Number of memory barriers committed
+system.cpu1.commit.branches                   4758017                       # Number of branches committed
+system.cpu1.commit.fp_insts                      4715                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                 32847444                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              475803                       # Number of function calls committed.
+system.cpu1.commit.bw_lim_events              1341129                       # number cycles where commit BW limit reached
+system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
+system.cpu1.rob.rob_reads                   114702650                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   92242025                       # The number of ROB writes
+system.cpu1.timesIdled                         868716                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                      159089393                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  2323530978                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   28667140                       # Number of Instructions Simulated
+system.cpu1.committedOps                     37026861                       # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total             28667140                       # Number of Instructions Simulated
+system.cpu1.cpi                              8.093356                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        8.093356                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.123558                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.123558                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               264545362                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               41743183                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    22037                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   19620                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads               56567930                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                442325                       # number of misc regfile writes
+system.iocache.replacements                         0                       # number of replacements
+system.iocache.tagsinuse                            0                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
+system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
+system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1125347676632                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1125347676632                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1125347676632                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1125347676632                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu0.kern.inst.quiesce                   88038                       # number of quiesce instructions executed
+system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal
new file mode 100644
index 0000000..f6a311d
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal
Binary files differ
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
new file mode 100644
index 0000000..c7f535f
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
@@ -0,0 +1,795 @@
+[root]
+type=Root
+children=system
+full_system=true
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
+atags_addr=256
+boot_loader=/arm/scratch/sysexplr/dist/binaries/boot.arm
+boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+clock=1000
+dtb_filename=
+early_kernel_symbols=false
+enable_context_switch_stats_dump=false
+flags_addr=268435504
+gic_cpu_addr=520093952
+init_param=0
+kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+load_addr_mask=268435455
+machine_type=RealView_PBX
+mem_mode=timing
+mem_ranges=0:134217727
+memories=system.physmem system.realview.nvmem
+multi_proc=true
+num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
+readfile=tests/halt.sh
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.bridge]
+type=Bridge
+clock=1000
+delay=50000
+ranges=268435456:520093695 1073741824:1610612735
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+image_file=/arm/scratch/sysexplr/dist/disks/linux-arm-ael.img
+read_only=true
+
+[system.cpu0]
+type=TimingSimpleCPU
+children=dcache dtb icache interrupts isa itb tracer
+checker=Null
+clock=500
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu0.dtb
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+switched_out=false
+system=system
+tracer=system.cpu0.tracer
+workload=
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=4
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+size=32768
+system=system
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu0.dtb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu0.dtb.walker
+
+[system.cpu0.dtb.walker]
+type=ArmTableWalker
+clock=500
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[3]
+
+[system.cpu0.icache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=1
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+size=32768
+system=system
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.interrupts]
+type=ArmInterrupts
+
+[system.cpu0.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
+[system.cpu0.itb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu0.itb.walker
+
+[system.cpu0.itb.walker]
+type=ArmTableWalker
+clock=500
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[2]
+
+[system.cpu0.tracer]
+type=ExeTracer
+
+[system.cpu1]
+type=TimingSimpleCPU
+children=dtb interrupts isa itb tracer
+checker=Null
+clock=500
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu1.dtb
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+switched_out=true
+system=system
+tracer=system.cpu1.tracer
+workload=
+
+[system.cpu1.dtb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu1.dtb.walker
+
+[system.cpu1.dtb.walker]
+type=ArmTableWalker
+clock=500
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.interrupts]
+type=ArmInterrupts
+
+[system.cpu1.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
+[system.cpu1.itb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu1.itb.walker
+
+[system.cpu1.itb.walker]
+type=ArmTableWalker
+clock=500
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.tracer]
+type=ExeTracer
+
+[system.intrctrl]
+type=IntrControl
+sys=system
+
+[system.iobus]
+type=NoncoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=8
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
+
+[system.iocache]
+type=BaseCache
+addr_ranges=0:134217727
+assoc=8
+block_size=64
+clock=1000
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+size=1024
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[25]
+mem_side=system.membus.slave[2]
+
+[system.l2c]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=8
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+size=4194304
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.membus]
+type=CoherentBus
+children=badaddr_responder
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=8
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
+slave=system.system_port system.l2c.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
+conf_table_reported=true
+in_addr_map=true
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
+null=false
+page_policy=open
+range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
+zero=false
+port=system.membus.master[2]
+
+[system.realview]
+type=RealView
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+intrctrl=system.intrctrl
+max_mem_size=268435456
+mem_start_addr=0
+pci_cfg_base=0
+system=system
+
+[system.realview.a9scu]
+type=A9SCU
+clock=1000
+pio_addr=520093696
+pio_latency=100000
+system=system
+pio=system.membus.master[5]
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268451840
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=402653184
+BAR0LegacyIO=true
+BAR0Size=16
+BAR1=402653440
+BAR1LegacyIO=true
+BAR1Size=1
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=0
+MinimumGrant=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clock=1000
+config_latency=20000
+ctrl_offset=2
+disks=system.cf0
+io_shift=1
+pci_bus=2
+pci_dev=7
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[8]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[7]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clock=1000
+gic=system.realview.gic
+int_num=55
+pio_addr=268566528
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.dmac_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268632064
+pio_latency=100000
+system=system
+pio=system.iobus.master[9]
+
+[system.realview.flash_fake]
+type=IsaFake
+clock=1000
+fake_mem=true
+pio_addr=1073741824
+pio_latency=100000
+pio_size=536870912
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[24]
+
+[system.realview.gic]
+type=Gic
+clock=1000
+cpu_addr=520093952
+cpu_pio_delay=10000
+dist_addr=520097792
+dist_pio_delay=10000
+int_latency=10000
+it_lines=128
+platform=system.realview
+system=system
+pio=system.membus.master[3]
+
+[system.realview.gpio0_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268513280
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.gpio1_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268517376
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.realview.gpio2_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268521472
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clock=1000
+gic=system.realview.gic
+int_delay=1000000
+int_num=52
+is_mouse=false
+pio_addr=268460032
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[5]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clock=1000
+gic=system.realview.gic
+int_delay=1000000
+int_num=53
+is_mouse=true
+pio_addr=268464128
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clock=1000
+fake_mem=false
+pio_addr=520101888
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.membus.master[4]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clock=1000
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=520095232
+pio_latency=100000
+system=system
+pio=system.membus.master[6]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268455936
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clock=1000
+conf_table_reported=false
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2214592511
+zero=true
+port=system.membus.master[1]
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clock=1000
+idreg=0
+pio_addr=268435456
+pio_latency=100000
+proc_id0=201326592
+proc_id1=201327138
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clock=1000
+gic=system.realview.gic
+int_delay=100000
+int_num=42
+pio_addr=268529664
+pio_latency=100000
+system=system
+time=Thu Jan  1 00:00:00 2009
+pio=system.iobus.master[23]
+
+[system.realview.sci_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268492800
+pio_latency=100000
+system=system
+pio=system.iobus.master[20]
+
+[system.realview.smc_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=269357056
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=true
+pio_addr=268439552
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.ssp_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268488704
+pio_latency=100000
+system=system
+pio=system.iobus.master[19]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clock=1000
+clock0=1000000
+clock1=1000000
+gic=system.realview.gic
+int_num0=36
+int_num1=36
+pio_addr=268505088
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clock=1000
+clock0=1000000
+clock1=1000000
+gic=system.realview.gic
+int_num0=37
+int_num1=37
+pio_addr=268509184
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clock=1000
+end_on_eot=false
+gic=system.realview.gic
+int_delay=100000
+int_num=44
+pio_addr=268472320
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268476416
+pio_latency=100000
+system=system
+pio=system.iobus.master[10]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268480512
+pio_latency=100000
+system=system
+pio=system.iobus.master[11]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268484608
+pio_latency=100000
+system=system
+pio=system.iobus.master[12]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clock=1000
+ignore_access=false
+pio_addr=268500992
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=CoherentBus
+block_size=64
+clock=500
+header_cycles=1
+use_default_range=false
+width=8
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
+
+[system.vncserver]
+type=VncServer
+frame_capture=false
+number=0
+port=5900
+
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr
new file mode 100755
index 0000000..98bbe41
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr
@@ -0,0 +1,40 @@
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: The clidr register always reports 0 caches.
+warn: clidr LoUIS field of 0b001 to match current ARM implementations.
+warn: The csselr register isn't implemented.
+warn: The ccsidr register isn't implemented and always reads as 0.
+hack: be nice to actually delete the event here
+warn: 	instruction 'mcr bpiallis' unimplemented
+warn: 	instruction 'mcr icialluis' unimplemented
+warn: 	instruction 'mcr dccimvac' unimplemented
+warn: 	instruction 'mcr dccmvau' unimplemented
+warn: 	instruction 'mcr icimvau' unimplemented
+warn: LCD dual screen mode not supported
+warn: 	instruction 'mcr icialluis' unimplemented
+warn: 	instruction 'mcr bpiallis' unimplemented
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout
new file mode 100755
index 0000000..7e73e93
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout
@@ -0,0 +1,10763 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Dec 11 2012 16:28:23
+gem5 started Dec 11 2012 16:28:35
+gem5 executing on e103721-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: Using bootloader at address 0x80000000
+info: Entering event queue @ 0.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1000000000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1000161000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2000161000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2000162000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 3000162000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3000209500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 4000209500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4000253500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 5000253500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5000254500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 6000254500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 6000255500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 7000255500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 7000257500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 8000257500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 8000258500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 9000258500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 9000473000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 10000473000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 10000475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 11000475000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 11000476000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 12000476000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 12000477500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 13000477500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 13000479500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 14000479500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 14000481500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 15000481500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 15000483500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 16000483500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 16000485500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 17000485500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 17000486500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 18000486500.  Starting simulation...
+info: Entering event queue @ 18000493500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 18000496000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 19000496000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 19000497000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 20000497000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 20000498000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 21000498000.  Starting simulation...
+info: Entering event queue @ 21000511500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 21000513000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 22000513000.  Starting simulation...
+info: Entering event queue @ 22000516500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 22000518000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 23000518000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 23000519000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 24000519000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 24000634000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 25000634000.  Starting simulation...
+info: Entering event queue @ 25000647000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 25000650500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 26000650500.  Starting simulation...
+info: Entering event queue @ 26000657000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 26000658500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 27000658500.  Starting simulation...
+info: Entering event queue @ 27000664500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 27000667000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 28000667000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 28000668000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 29000668000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 29000669000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 30000669000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 30000671000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 31000671000.  Starting simulation...
+info: Entering event queue @ 31000679500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 31000682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 32000682000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 32000683000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 33000683000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 33000684000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 34000684000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 34000685000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 35000685000.  Starting simulation...
+info: Entering event queue @ 35000871500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 35000872500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 36000872500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 36000875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 37000875000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 37001097000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 38001097000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 38001098000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 39001098000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 40001098000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 41001098000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 42001098000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 43001098000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 44001098000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 45001098000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 45001099000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 46001099000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 47001099000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 48001099000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 49001099000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 50001099000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 51001099000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 52001099000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 53001099000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 54001099000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 55001099000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 56001099000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 57001099000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 58001099000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 59001099000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 60001099000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 61001099000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 62001099000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 63001099000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 64001099000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 65001099000.  Starting simulation...
+info: Entering event queue @ 66306421000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 66306423000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 67306423000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 67306432500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 68306432500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 68306442500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 69306442500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 69306452500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 70306452500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 70306453500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 71306453500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 71306514500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 72306514500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 72306516500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 73306516500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 73306518500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 74306518500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 74306519500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 75306519500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 75306520500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 76306520500.  Starting simulation...
+info: Entering event queue @ 76306542500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 76306583500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 77306583500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 77306585500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 78306585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 78306586500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 79306586500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 79306587500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 80306587500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 80306589500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 81306589500.  Starting simulation...
+info: Entering event queue @ 81306614500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 81306676500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 82306676500.  Starting simulation...
+info: Entering event queue @ 82306698500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 82306739500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 83306739500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 83306740500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 84306740500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 84306741500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 85306741500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 85306742500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 86306742500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 86306743500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 87306743500.  Starting simulation...
+info: Entering event queue @ 87306763500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 87306822500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 88306822500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 88306823500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 89306823500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 89306824500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 90306824500.  Starting simulation...
+info: Entering event queue @ 90306840500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 90306899500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 91306899500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 91306906500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 92306906500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 92306907500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 93306907500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 93306908500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 94306908500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 94306931500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 95306931500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 95306933500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 96306933500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 96307006500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 97307006500.  Starting simulation...
+info: Entering event queue @ 97307011500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 97307013000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 98307013000.  Starting simulation...
+info: Entering event queue @ 99022063000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 99022065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 100022065000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 100022065500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 101022065500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 101022067500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 102022067500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 102022068500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 103022068500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 103022072000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 104022072000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 104022073000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 105022073000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 105022074500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 106022074500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 106022075000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 107022075000.  Starting simulation...
+info: Entering event queue @ 107022087500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 107022090000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 108022090000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 108022090500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 109022090500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 109022092500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 110022092500.  Starting simulation...
+info: Entering event queue @ 110022099500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 110022103000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 111022103000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 111022104000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 112022104000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 113022104000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 114022104000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 115022104000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 116022104000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 117022104000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 118022104000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 119022104000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 120022104000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 121022104000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 122022104000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 123022104000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 124022104000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 125022104000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 126022104000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 127022104000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 128022104000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 129022104000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 130022104000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 131022104000.  Starting simulation...
+info: Entering event queue @ 131758663000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 131758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 132758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 133758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 134758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 135758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 136758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 137758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 138758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 139758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 140758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 141758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 142758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 143758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 144758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 145758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 146758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 147758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 148758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 149758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 150758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 151758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 152758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 153758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 154758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 155758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 156758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 157758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 158758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 159758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 160758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 161758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 162758665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 163758665000.  Starting simulation...
+info: Entering event queue @ 164494807000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 164494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 165494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 166494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 167494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 168494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 169494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 170494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 171494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 172494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 173494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 174494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 175494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 176494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 177494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 178494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 179494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 180494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 181494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 182494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 183494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 184494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 185494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 186494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 187494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 188494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 189494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 190494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 191494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 192494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 193494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 194494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 195494809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 196494809000.  Starting simulation...
+info: Entering event queue @ 197230954000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 197230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 198230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 199230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 200230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 201230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 202230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 203230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 204230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 205230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 206230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 207230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 208230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 209230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 210230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 211230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 212230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 213230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 214230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 215230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 216230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 217230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 218230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 219230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 220230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 221230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 222230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 223230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 224230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 225230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 226230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 227230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 228230956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 229230956000.  Starting simulation...
+info: Entering event queue @ 229967245000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 229967247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 230967247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 231967247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 232967247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 233967247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 234967247000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 234967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 235967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 236967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 237967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 238967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 239967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 240967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 241967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 242967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 243967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 244967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 245967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 246967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 247967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 248967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 249967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 250967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 251967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 252967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 253967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 254967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 255967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 256967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 257967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 258967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 259967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 260967248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 261967248000.  Starting simulation...
+info: Entering event queue @ 262703389000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 262703391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 263703391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 264703391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 265703391000.  Starting simulation...
+info: Entering event queue @ 265703411000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 265703413500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 266703413500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 266703416000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 267703416000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 267703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 268703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 269703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 270703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 271703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 272703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 273703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 274703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 275703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 276703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 277703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 278703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 279703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 280703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 281703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 282703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 283703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 284703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 285703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 286703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 287703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 288703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 289703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 290703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 291703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 292703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 293703417000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 294703417000.  Starting simulation...
+info: Entering event queue @ 295439680000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 295439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 296439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 297439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 298439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 299439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 300439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 301439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 302439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 303439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 304439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 305439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 306439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 307439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 308439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 309439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 310439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 311439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 312439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 313439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 314439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 315439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 316439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 317439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 318439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 319439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 320439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 321439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 322439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 323439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 324439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 325439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 326439682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 327439682000.  Starting simulation...
+info: Entering event queue @ 328175821000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 328175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 329175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 330175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 331175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 332175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 333175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 334175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 335175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 336175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 337175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 338175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 339175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 340175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 341175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 342175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 343175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 344175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 345175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 346175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 347175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 348175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 349175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 350175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 351175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 352175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 353175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 354175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 355175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 356175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 357175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 358175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 359175823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 360175823000.  Starting simulation...
+info: Entering event queue @ 360912115000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 360912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 361912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 362912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 363912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 364912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 365912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 366912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 367912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 368912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 369912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 370912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 371912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 372912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 373912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 374912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 375912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 376912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 377912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 378912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 379912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 380912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 381912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 382912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 383912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 384912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 385912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 386912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 387912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 388912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 389912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 390912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 391912117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 392912117000.  Starting simulation...
+info: Entering event queue @ 393648256000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 393648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 394648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 395648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 396648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 397648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 398648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 399648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 400648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 401648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 402648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 403648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 404648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 405648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 406648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 407648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 408648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 409648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 410648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 411648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 412648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 413648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 414648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 415648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 416648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 417648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 418648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 419648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 420648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 421648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 422648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 423648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 424648258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 425648258000.  Starting simulation...
+info: Entering event queue @ 426384856000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 426384858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 427384858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 428384858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 429384858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 430384858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 431384858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 432384858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 433384858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 434384858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 435384858000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 435384859000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 436384859000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 437384859000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 438384859000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 439384859000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 440384859000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 441384859000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 442384859000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 443384859000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 444384859000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 445384859000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 446384859000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 447384859000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 448384859000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 449384859000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 450384859000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 451384859000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 452384859000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 453384859000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 454384859000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 455384859000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 456384859000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 457384859000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 458384859000.  Starting simulation...
+info: Entering event queue @ 459121147000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 459121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 460121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 461121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 462121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 463121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 464121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 465121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 466121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 467121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 468121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 469121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 470121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 471121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 472121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 473121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 474121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 475121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 476121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 477121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 478121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 479121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 480121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 481121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 482121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 483121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 484121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 485121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 486121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 487121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 488121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 489121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 490121149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 491121149000.  Starting simulation...
+info: Entering event queue @ 491857291000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 491857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 492857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 493857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 494857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 495857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 496857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 497857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 498857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 499857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 500857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 501857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 502857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 503857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 504857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 505857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 506857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 507857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 508857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 509857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 510857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 511857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 512857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 513857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 514857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 515857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 516857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 517857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 518857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 519857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 520857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 521857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 522857293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 523857293000.  Starting simulation...
+info: Entering event queue @ 524593582000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 524593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 525593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 526593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 527593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 528593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 529593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 530593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 531593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 532593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 533593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 534593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 535593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 536593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 537593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 538593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 539593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 540593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 541593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 542593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 543593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 544593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 545593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 546593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 547593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 548593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 549593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 550593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 551593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 552593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 553593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 554593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 555593584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 556593584000.  Starting simulation...
+info: Entering event queue @ 557329726000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 557329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 558329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 559329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 560329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 561329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 562329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 563329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 564329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 565329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 566329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 567329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 568329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 569329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 570329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 571329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 572329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 573329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 574329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 575329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 576329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 577329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 578329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 579329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 580329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 581329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 582329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 583329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 584329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 585329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 586329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 587329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 588329728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 589329728000.  Starting simulation...
+info: Entering event queue @ 590065873000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 590065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 591065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 592065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 593065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 594065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 595065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 596065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 597065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 598065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 599065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 600065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 601065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 602065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 603065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 604065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 605065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 606065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 607065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 608065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 609065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 610065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 611065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 612065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 613065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 614065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 615065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 616065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 617065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 618065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 619065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 620065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 621065875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 622065875000.  Starting simulation...
+info: Entering event queue @ 622802473000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 622802475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 623802475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 624802475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 625802475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 626802475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 627802475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 628802475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 629802475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 630802475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 631802475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 632802475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 633802475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 634802475000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 634802476000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 635802476000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 636802476000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 637802476000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 638802476000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 639802476000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 640802476000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 641802476000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 642802476000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 643802476000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 644802476000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 645802476000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 646802476000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 647802476000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 648802476000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 649802476000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 650802476000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 651802476000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 652802476000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 653802476000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 654802476000.  Starting simulation...
+info: Entering event queue @ 655538305000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 655538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 656538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 657538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 658538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 659538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 660538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 661538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 662538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 663538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 664538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 665538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 666538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 667538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 668538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 669538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 670538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 671538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 672538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 673538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 674538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 675538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 676538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 677538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 678538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 679538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 680538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 681538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 682538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 683538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 684538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 685538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 686538307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 687538307000.  Starting simulation...
+info: Entering event queue @ 688274905000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 688274907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 689274907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 690274907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 691274907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 692274907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 693274907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 694274907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 695274907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 696274907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 697274907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 698274907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 699274907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 700274907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 701274907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 702274907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 703274907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 704274907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 705274907000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 705274908000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 706274908000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 707274908000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 708274908000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 709274908000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 710274908000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 711274908000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 712274908000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 713274908000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 714274908000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 715274908000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 716274908000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 717274908000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 718274908000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 719274908000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 720274908000.  Starting simulation...
+info: Entering event queue @ 721011196000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 721011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 722011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 723011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 724011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 725011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 726011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 727011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 728011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 729011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 730011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 731011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 732011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 733011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 734011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 735011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 736011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 737011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 738011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 739011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 740011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 741011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 742011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 743011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 744011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 745011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 746011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 747011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 748011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 749011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 750011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 751011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 752011198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 753011198000.  Starting simulation...
+info: Entering event queue @ 753747337000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 753747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 754747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 755747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 756747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 757747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 758747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 759747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 760747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 761747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 762747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 763747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 764747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 765747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 766747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 767747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 768747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 769747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 770747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 771747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 772747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 773747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 774747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 775747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 776747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 777747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 778747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 779747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 780747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 781747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 782747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 783747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 784747339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 785747339000.  Starting simulation...
+info: Entering event queue @ 786483631000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 786483633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 787483633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 788483633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 789483633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 790483633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 791483633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 792483633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 793483633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 794483633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 795483633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 796483633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 797483633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 798483633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 799483633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 800483633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 801483633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 802483633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 803483633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 804483633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 805483633000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 805483634000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 806483634000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 807483634000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 808483634000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 809483634000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 810483634000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 811483634000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 812483634000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 813483634000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 814483634000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 815483634000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 816483634000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 817483634000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 818483634000.  Starting simulation...
+info: Entering event queue @ 819219772000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 819219774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 820219774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 821219774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 822219774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 823219774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 824219774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 825219774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 826219774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 827219774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 828219774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 829219774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 830219774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 831219774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 832219774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 833219774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 834219774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 835219774000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 835219775000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 836219775000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 837219775000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 838219775000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 839219775000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 840219775000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 841219775000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 842219775000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 843219775000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 844219775000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 845219775000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 846219775000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 847219775000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 848219775000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 849219775000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 850219775000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 851219775000.  Starting simulation...
+info: Entering event queue @ 851956063000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 851956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 852956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 853956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 854956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 855956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 856956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 857956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 858956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 859956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 860956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 861956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 862956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 863956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 864956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 865956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 866956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 867956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 868956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 869956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 870956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 871956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 872956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 873956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 874956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 875956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 876956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 877956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 878956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 879956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 880956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 881956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 882956065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 883956065000.  Starting simulation...
+info: Entering event queue @ 884692663000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 884692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 885692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 886692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 887692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 888692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 889692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 890692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 891692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 892692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 893692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 894692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 895692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 896692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 897692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 898692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 899692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 900692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 901692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 902692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 903692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 904692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 905692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 906692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 907692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 908692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 909692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 910692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 911692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 912692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 913692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 914692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 915692665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 916692665000.  Starting simulation...
+info: Entering event queue @ 917428807000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 917428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 918428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 919428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 920428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 921428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 922428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 923428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 924428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 925428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 926428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 927428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 928428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 929428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 930428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 931428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 932428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 933428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 934428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 935428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 936428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 937428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 938428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 939428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 940428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 941428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 942428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 943428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 944428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 945428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 946428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 947428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 948428809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 949428809000.  Starting simulation...
+info: Entering event queue @ 950164954000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 950164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 951164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 952164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 953164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 954164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 955164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 956164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 957164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 958164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 959164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 960164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 961164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 962164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 963164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 964164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 965164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 966164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 967164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 968164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 969164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 970164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 971164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 972164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 973164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 974164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 975164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 976164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 977164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 978164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 979164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 980164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 981164956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 982164956000.  Starting simulation...
+info: Entering event queue @ 982901245000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 982901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 983901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 984901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 985901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 986901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 987901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 988901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 989901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 990901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 991901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 992901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 993901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 994901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 995901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 996901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 997901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 998901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 999901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1000901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1001901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1002901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1003901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1004901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1005901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1006901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1007901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1008901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1009901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1010901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1011901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1012901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1013901247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1014901247000.  Starting simulation...
+info: Entering event queue @ 1015637389000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1015637391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1016637391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1017637391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1018637391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1019637391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1020637391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1021637391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1022637391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1023637391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1024637391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1025637391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1026637391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1027637391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1028637391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1029637391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1030637391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1031637391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1032637391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1033637391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1034637391000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1034637391500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1035637391500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1035637392500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1036637392500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1037637392500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1038637392500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1039637392500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1040637392500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1041637392500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1042637392500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1043637392500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1044637392500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1045637392500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1046637392500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1047637392500.  Starting simulation...
+info: Entering event queue @ 1048373680000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1048373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1049373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1050373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1051373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1052373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1053373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1054373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1055373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1056373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1057373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1058373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1059373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1060373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1061373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1062373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1063373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1064373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1065373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1066373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1067373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1068373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1069373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1070373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1071373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1072373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1073373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1074373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1075373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1076373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1077373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1078373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1079373682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1080373682000.  Starting simulation...
+info: Entering event queue @ 1081109821000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1081109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1082109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1083109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1084109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1085109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1086109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1087109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1088109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1089109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1090109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1091109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1092109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1093109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1094109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1095109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1096109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1097109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1098109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1099109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1100109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1101109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1102109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1103109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1104109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1105109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1106109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1107109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1108109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1109109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1110109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1111109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1112109823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1113109823000.  Starting simulation...
+info: Entering event queue @ 1113846115000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1113846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1114846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1115846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1116846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1117846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1118846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1119846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1120846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1121846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1122846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1123846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1124846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1125846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1126846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1127846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1128846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1129846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1130846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1131846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1132846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1133846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1134846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1135846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1136846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1137846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1138846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1139846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1140846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1141846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1142846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1143846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1144846117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1145846117000.  Starting simulation...
+info: Entering event queue @ 1146582256000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1146582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1147582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1148582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1149582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1150582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1151582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1152582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1153582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1154582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1155582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1156582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1157582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1158582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1159582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1160582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1161582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1162582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1163582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1164582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1165582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1166582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1167582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1168582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1169582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1170582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1171582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1172582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1173582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1174582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1175582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1176582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1177582258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1178582258000.  Starting simulation...
+info: Entering event queue @ 1179318856000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1179318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1180318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1181318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1182318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1183318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1184318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1185318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1186318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1187318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1188318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1189318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1190318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1191318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1192318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1193318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1194318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1195318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1196318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1197318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1198318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1199318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1200318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1201318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1202318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1203318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1204318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1205318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1206318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1207318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1208318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1209318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1210318858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1211318858000.  Starting simulation...
+info: Entering event queue @ 1212055147000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1212055149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1213055149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1214055149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1215055149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1216055149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1217055149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1218055149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1219055149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1220055149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1221055149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1222055149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1223055149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1224055149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1225055149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1226055149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1227055149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1228055149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1229055149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1230055149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1231055149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1232055149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1233055149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1234055149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1235055149000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1235055150000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1236055150000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1237055150000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1238055150000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1239055150000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1240055150000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1241055150000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1242055150000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1243055150000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1244055150000.  Starting simulation...
+info: Entering event queue @ 1244791291000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1244791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1245791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1246791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1247791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1248791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1249791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1250791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1251791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1252791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1253791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1254791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1255791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1256791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1257791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1258791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1259791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1260791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1261791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1262791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1263791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1264791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1265791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1266791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1267791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1268791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1269791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1270791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1271791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1272791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1273791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1274791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1275791293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1276791293000.  Starting simulation...
+info: Entering event queue @ 1277527582000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1277527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1278527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1279527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1280527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1281527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1282527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1283527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1284527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1285527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1286527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1287527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1288527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1289527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1290527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1291527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1292527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1293527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1294527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1295527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1296527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1297527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1298527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1299527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1300527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1301527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1302527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1303527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1304527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1305527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1306527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1307527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1308527584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1309527584000.  Starting simulation...
+info: Entering event queue @ 1310263726000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1310263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1311263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1312263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1313263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1314263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1315263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1316263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1317263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1318263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1319263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1320263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1321263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1322263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1323263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1324263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1325263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1326263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1327263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1328263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1329263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1330263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1331263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1332263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1333263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1334263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1335263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1336263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1337263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1338263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1339263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1340263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1341263728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1342263728000.  Starting simulation...
+info: Entering event queue @ 1342999873000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1342999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1343999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1344999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1345999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1346999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1347999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1348999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1349999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1350999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1351999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1352999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1353999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1354999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1355999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1356999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1357999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1358999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1359999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1360999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1361999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1362999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1363999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1364999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1365999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1366999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1367999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1368999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1369999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1370999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1371999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1372999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1373999875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1374999875000.  Starting simulation...
+info: Entering event queue @ 1375736473000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1375736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1376736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1377736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1378736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1379736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1380736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1381736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1382736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1383736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1384736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1385736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1386736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1387736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1388736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1389736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1390736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1391736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1392736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1393736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1394736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1395736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1396736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1397736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1398736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1399736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1400736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1401736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1402736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1403736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1404736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1405736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1406736475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1407736475000.  Starting simulation...
+info: Entering event queue @ 1408472305000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1408472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1409472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1410472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1411472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1412472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1413472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1414472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1415472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1416472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1417472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1418472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1419472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1420472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1421472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1422472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1423472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1424472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1425472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1426472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1427472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1428472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1429472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1430472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1431472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1432472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1433472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1434472307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1435472307000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1435472308000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1436472308000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1437472308000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1438472308000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1439472308000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1440472308000.  Starting simulation...
+info: Entering event queue @ 1441208905000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1441208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1442208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1443208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1444208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1445208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1446208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1447208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1448208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1449208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1450208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1451208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1452208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1453208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1454208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1455208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1456208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1457208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1458208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1459208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1460208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1461208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1462208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1463208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1464208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1465208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1466208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1467208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1468208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1469208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1470208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1471208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1472208907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1473208907000.  Starting simulation...
+info: Entering event queue @ 1473945196000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1473945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1474945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1475945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1476945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1477945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1478945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1479945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1480945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1481945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1482945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1483945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1484945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1485945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1486945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1487945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1488945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1489945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1490945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1491945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1492945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1493945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1494945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1495945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1496945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1497945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1498945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1499945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1500945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1501945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1502945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1503945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1504945198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1505945198000.  Starting simulation...
+info: Entering event queue @ 1506681337000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1506681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1507681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1508681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1509681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1510681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1511681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1512681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1513681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1514681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1515681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1516681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1517681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1518681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1519681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1520681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1521681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1522681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1523681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1524681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1525681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1526681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1527681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1528681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1529681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1530681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1531681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1532681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1533681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1534681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1535681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1536681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1537681339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1538681339000.  Starting simulation...
+info: Entering event queue @ 1539417631000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1539417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1540417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1541417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1542417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1543417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1544417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1545417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1546417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1547417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1548417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1549417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1550417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1551417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1552417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1553417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1554417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1555417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1556417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1557417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1558417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1559417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1560417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1561417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1562417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1563417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1564417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1565417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1566417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1567417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1568417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1569417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1570417633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1571417633000.  Starting simulation...
+info: Entering event queue @ 1572153772000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1572153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1573153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1574153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1575153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1576153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1577153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1578153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1579153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1580153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1581153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1582153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1583153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1584153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1585153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1586153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1587153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1588153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1589153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1590153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1591153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1592153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1593153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1594153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1595153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1596153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1597153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1598153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1599153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1600153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1601153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1602153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1603153774000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1604153774000.  Starting simulation...
+info: Entering event queue @ 1604890063000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1604890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1605890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1606890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1607890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1608890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1609890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1610890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1611890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1612890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1613890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1614890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1615890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1616890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1617890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1618890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1619890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1620890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1621890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1622890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1623890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1624890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1625890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1626890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1627890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1628890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1629890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1630890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1631890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1632890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1633890065000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1634890065000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1634890066000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1635890066000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1636890066000.  Starting simulation...
+info: Entering event queue @ 1637626663000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1637626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1638626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1639626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1640626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1641626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1642626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1643626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1644626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1645626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1646626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1647626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1648626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1649626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1650626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1651626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1652626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1653626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1654626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1655626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1656626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1657626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1658626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1659626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1660626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1661626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1662626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1663626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1664626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1665626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1666626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1667626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1668626665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1669626665000.  Starting simulation...
+info: Entering event queue @ 1670362807000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1670362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1671362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1672362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1673362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1674362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1675362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1676362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1677362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1678362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1679362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1680362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1681362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1682362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1683362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1684362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1685362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1686362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1687362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1688362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1689362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1690362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1691362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1692362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1693362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1694362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1695362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1696362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1697362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1698362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1699362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1700362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1701362809000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1702362809000.  Starting simulation...
+info: Entering event queue @ 1703098954000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1703098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1704098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1705098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1706098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1707098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1708098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1709098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1710098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1711098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1712098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1713098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1714098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1715098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1716098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1717098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1718098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1719098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1720098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1721098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1722098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1723098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1724098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1725098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1726098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1727098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1728098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1729098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1730098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1731098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1732098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1733098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1734098956000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1735098956000.  Starting simulation...
+info: Entering event queue @ 1735835245000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1735835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1736835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1737835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1738835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1739835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1740835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1741835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1742835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1743835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1744835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1745835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1746835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1747835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1748835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1749835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1750835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1751835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1752835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1753835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1754835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1755835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1756835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1757835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1758835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1759835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1760835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1761835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1762835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1763835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1764835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1765835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1766835247000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1767835247000.  Starting simulation...
+info: Entering event queue @ 1768571389000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1768571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1769571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1770571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1771571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1772571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1773571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1774571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1775571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1776571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1777571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1778571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1779571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1780571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1781571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1782571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1783571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1784571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1785571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1786571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1787571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1788571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1789571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1790571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1791571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1792571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1793571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1794571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1795571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1796571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1797571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1798571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1799571391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1800571391000.  Starting simulation...
+info: Entering event queue @ 1801307680000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1801307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1802307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1803307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1804307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1805307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1806307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1807307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1808307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1809307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1810307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1811307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1812307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1813307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1814307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1815307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1816307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1817307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1818307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1819307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1820307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1821307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1822307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1823307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1824307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1825307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1826307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1827307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1828307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1829307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1830307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1831307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1832307682000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1833307682000.  Starting simulation...
+info: Entering event queue @ 1834043821000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1834043823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1835043823000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1835043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1836043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1837043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1838043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1839043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1840043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1841043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1842043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1843043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1844043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1845043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1846043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1847043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1848043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1849043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1850043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1851043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1852043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1853043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1854043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1855043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1856043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1857043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1858043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1859043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1860043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1861043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1862043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1863043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1864043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1865043824000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1866043824000.  Starting simulation...
+info: Entering event queue @ 1866780115000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1866780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1867780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1868780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1869780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1870780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1871780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1872780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1873780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1874780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1875780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1876780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1877780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1878780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1879780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1880780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1881780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1882780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1883780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1884780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1885780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1886780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1887780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1888780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1889780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1890780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1891780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1892780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1893780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1894780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1895780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1896780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1897780117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1898780117000.  Starting simulation...
+info: Entering event queue @ 1899516256000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1899516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1900516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1901516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1902516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1903516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1904516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1905516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1906516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1907516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1908516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1909516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1910516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1911516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1912516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1913516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1914516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1915516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1916516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1917516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1918516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1919516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1920516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1921516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1922516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1923516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1924516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1925516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1926516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1927516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1928516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1929516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1930516258000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1931516258000.  Starting simulation...
+info: Entering event queue @ 1932252856000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1932252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1933252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1934252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1935252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1936252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1937252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1938252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1939252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1940252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1941252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1942252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1943252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1944252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1945252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1946252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1947252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1948252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1949252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1950252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1951252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1952252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1953252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1954252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1955252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1956252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1957252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1958252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1959252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1960252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1961252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1962252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1963252858000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1964252858000.  Starting simulation...
+info: Entering event queue @ 1964989147000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1964989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1965989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1966989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1967989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1968989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1969989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1970989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1971989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1972989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1973989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1974989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1975989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1976989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1977989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1978989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1979989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1980989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1981989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1982989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1983989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1984989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1985989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1986989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1987989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1988989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1989989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1990989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1991989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1992989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1993989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1994989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1995989149000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1996989149000.  Starting simulation...
+info: Entering event queue @ 1997725291000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1997725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1998725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1999725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2000725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2001725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2002725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2003725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2004725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2005725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2006725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2007725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2008725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2009725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2010725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2011725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2012725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2013725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2014725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2015725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2016725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2017725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2018725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2019725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2020725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2021725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2022725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2023725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2024725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2025725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2026725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2027725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2028725293000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2029725293000.  Starting simulation...
+info: Entering event queue @ 2030461582000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2030461584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2031461584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2032461584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2033461584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2034461584000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2035461584000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2035461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2036461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2037461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2038461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2039461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2040461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2041461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2042461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2043461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2044461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2045461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2046461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2047461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2048461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2049461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2050461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2051461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2052461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2053461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2054461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2055461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2056461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2057461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2058461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2059461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2060461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2061461585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2062461585000.  Starting simulation...
+info: Entering event queue @ 2063197726000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2063197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2064197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2065197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2066197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2067197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2068197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2069197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2070197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2071197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2072197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2073197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2074197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2075197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2076197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2077197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2078197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2079197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2080197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2081197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2082197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2083197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2084197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2085197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2086197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2087197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2088197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2089197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2090197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2091197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2092197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2093197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2094197728000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2095197728000.  Starting simulation...
+info: Entering event queue @ 2095933873000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2095933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2096933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2097933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2098933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2099933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2100933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2101933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2102933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2103933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2104933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2105933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2106933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2107933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2108933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2109933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2110933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2111933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2112933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2113933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2114933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2115933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2116933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2117933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2118933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2119933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2120933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2121933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2122933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2123933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2124933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2125933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2126933875000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2127933875000.  Starting simulation...
+info: Entering event queue @ 2128670473000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2128670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2129670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2130670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2131670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2132670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2133670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2134670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2135670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2136670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2137670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2138670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2139670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2140670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2141670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2142670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2143670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2144670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2145670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2146670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2147670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2148670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2149670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2150670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2151670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2152670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2153670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2154670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2155670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2156670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2157670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2158670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2159670475000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2160670475000.  Starting simulation...
+info: Entering event queue @ 2161406305000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2161406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2162406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2163406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2164406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2165406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2166406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2167406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2168406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2169406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2170406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2171406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2172406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2173406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2174406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2175406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2176406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2177406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2178406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2179406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2180406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2181406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2182406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2183406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2184406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2185406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2186406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2187406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2188406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2189406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2190406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2191406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2192406307000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2193406307000.  Starting simulation...
+info: Entering event queue @ 2194142905000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2194142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2195142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2196142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2197142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2198142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2199142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2200142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2201142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2202142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2203142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2204142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2205142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2206142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2207142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2208142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2209142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2210142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2211142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2212142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2213142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2214142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2215142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2216142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2217142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2218142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2219142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2220142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2221142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2222142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2223142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2224142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2225142907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2226142907000.  Starting simulation...
+info: Entering event queue @ 2226879196000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2226879198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2227879198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2228879198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2229879198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2230879198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2231879198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2232879198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2233879198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2234879198000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2234879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2235879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2236879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2237879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2238879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2239879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2240879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2241879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2242879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2243879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2244879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2245879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2246879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2247879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2248879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2249879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2250879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2251879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2252879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2253879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2254879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2255879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2256879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2257879199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2258879199000.  Starting simulation...
+info: Entering event queue @ 2259615337000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2259615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2260615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2261615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2262615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2263615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2264615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2265615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2266615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2267615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2268615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2269615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2270615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2271615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2272615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2273615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2274615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2275615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2276615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2277615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2278615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2279615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2280615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2281615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2282615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2283615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2284615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2285615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2286615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2287615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2288615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2289615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2290615339000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2291615339000.  Starting simulation...
+info: Entering event queue @ 2292351631000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2292351633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2293351633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2294351633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2295351633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2296351633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2297351633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2298351633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2299351633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2300351633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2301351633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2302351633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2303351633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2304351633000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2305351633000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2305351696000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2306351696000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2306351697000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2307351697000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2308351697000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2309351697000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2310351697000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2311351697000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2312351697000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2313351697000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2314351697000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2315351697000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2316351697000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2317351697000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2318351697000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2319351697000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2320351697000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2321351697000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2322351697000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2323351697000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2324351697000.  Starting simulation...
+info: Entering event queue @ 2325088231000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2325088237000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2326088237000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2326088238500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2327088238500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2327088324000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2328088324000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2328088325000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2329088325000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2329088480000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2330088480000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2330088481000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2331088481000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2331088482000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2332088482000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2332088483000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2333088483000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2333088484000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2334088484000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2334088485000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2335088485000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2335088511000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2336088511000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2336088552000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2337088552000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2337088554000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2338088554000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2338088597000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2339088597000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2339088612000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2340088612000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2340088674000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2341088674000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2341088772000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2342088772000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2342088773000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2343088773000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2343088775000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2344088775000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2344088789000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2345088789000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2345088919000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2346088919000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2346088990000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2347088990000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2347089092000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2348089092000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2348089095500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2349089095500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2349089096500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2350089096500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2350089098500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2351089098500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2351089113000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2352089113000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2352089199000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2353089199000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2353089200000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2354089200000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2354089248000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2355089248000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2355089265000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2356089265000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2356089316000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2357089316000.  Starting simulation...
+info: Entering event queue @ 2357824372000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2357824374000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2358824374000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2358824488000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2359824488000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2359824489000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2360824489000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2360824618000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2361824618000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2361824637000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2362824637000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2362824638000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2363824638000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2363824687000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2364824687000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2364824823000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2365824823000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2365824964000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2366824964000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2366824989000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2367824989000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2367825012000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2368825012000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2368825145000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2369825145000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2369825146000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2370825146000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2370825288000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2371825288000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2371825289000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2372825289000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2372825296000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2373825296000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2373825361000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2374825361000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2374825463000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2375825463000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2375825612000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2376825612000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2376825684000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2377825684000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2377825750000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2378825750000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2378825867000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2379825867000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2379825907000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2380825907000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2380825985000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2381825985000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2381826127000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2382826127000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2382826217000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2383826217000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2383826218000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2384826218000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2384826219000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2385826219000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2385826249000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2386826249000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2386826330000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2387826330000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2387826331000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2388826331000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2388826388000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2389826388000.  Starting simulation...
+info: Entering event queue @ 2390560663000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2390560665000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2391560665000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2391560666000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2392560666000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2392560703000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2393560703000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2393560798000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2394560798000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2394560799000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2395560799000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2395560928000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2396560928000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2396561075000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2397561075000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2397561139000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2398561139000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2398561189000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2399561189000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2399561344000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2400561344000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2400561484000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2401561484000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2401561534000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2402561534000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2402561628000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2403561628000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2403561712000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2404561712000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2404561726000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2405561726000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2405561835000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2406561835000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2406561960000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2407561960000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2407562071000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2408562071000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2408562185000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2409562185000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2409562309000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2410562309000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2410562346000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2411562346000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2411562485000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2412562485000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2412562486000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2413562486000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2413562559000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2414562559000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2414562654000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2415562654000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2415562655000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2416562655000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2416562810000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2417562810000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2417562871000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2418562871000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2418562872000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2419562872000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2419562919000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2420562919000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2420562986000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2421562986000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2421562987000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2422562987000.  Starting simulation...
+info: Entering event queue @ 2423297572000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2423297574000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2424297574000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2424297699000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2425297699000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2425297786000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2426297786000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2426297856000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2427297856000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2427298009000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2428298009000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2428298043000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2429298043000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2429298115000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2430298115000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2430298116000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2431298116000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2431298128000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2432298128000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2432298154000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2433298154000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2433298155000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2434298155000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2434298209000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2435298209000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2435298264000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2436298264000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2436298295000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2437298295000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2437298393000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2438298393000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2438298535000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2439298535000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2439298588000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2440298588000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2440298715000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2441298715000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2441298826000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2442298826000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2442298827000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2443298827000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2443298920000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2444298920000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2444298968000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2445298968000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2445298969000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2446298969000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2446299109000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2447299109000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2447299228000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2448299228000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2448299344000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2449299344000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2449299491000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2450299491000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2450299553000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2451299553000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2451299683000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2452299683000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2452299768000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2453299768000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2453299890000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2454299890000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2454299959000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2455299959000.  Starting simulation...
+info: Entering event queue @ 2456033037000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2456033039000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2457033039000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2457033167000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2458033167000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2458033184000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2459033184000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2459033282000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2460033282000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2460033316000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2461033316000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2461033409000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2462033409000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2462033511000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2463033511000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2463033638000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2464033638000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2464033758000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2465033758000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2465033759000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2466033759000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2466033904000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2467033904000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2467033927000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2468033927000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2468034035000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2469034035000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2469034153000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2470034153000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2470034198000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2471034198000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2471034246000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2472034246000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2472034313000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2473034313000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2473034456000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2474034456000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2474034604000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2475034604000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2475034749000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2476034749000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2476034794000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2477034794000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2477034802000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2478034802000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2478034803000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2479034803000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2479034908000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2480034908000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2480034957000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2481034957000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2481034958000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2482034958000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2482035090000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2483035090000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2483035091000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2484035091000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2484035144000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2485035144000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2485035271000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2486035271000.  Starting simulation...
+info: Entering event queue @ 2486035296500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2486035328001.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2487035328001.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2487035397000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2488035397000.  Starting simulation...
+info: Entering event queue @ 2488769554000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2488769556000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2489769556000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2489769557000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2490769557000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2490769609000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2491769609000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2491769729000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2492769729000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2492769746000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2493769746000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2493769816000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2494769816000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2494769817000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2495769817000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2495769874000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2496769874000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2496769981000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2497769981000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2497769982000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2498769982000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2498770059000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2499770059000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2499770067000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2500770067000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2500770068000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2501770068000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2501770143000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2502770143000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2502770205000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2503770205000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2503770206000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2504770206000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2504770245000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2505770245000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2505770337000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2506770337000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2506770376000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2507770376000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2507770429000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2508770429000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2508770532000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2509770532000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2509770565000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2510770565000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2510770668000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2511770668000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2511770737000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2512770737000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2512770886000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2513770886000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2513770887000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2514770887000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2514771013000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2515771013000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2515771025000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2516771025000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2516771132000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2517771132000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2517771133000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2518771133000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2518771270000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2519771270000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2519771364000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2520771364000.  Starting simulation...
+info: Entering event queue @ 2521505845000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2521505847000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2522505847000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2522505848000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2523505848000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2523505849000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2524505849000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2524505850000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2525505850000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2525505953000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2526505953000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2526505954000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2527505954000.  Starting simulation...
+info: Entering event queue @ 2527505964000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2527505965500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2528505965500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2528506085000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2529506085000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2529506182000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2530506182000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2530506241000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2531506241000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2531506368000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2532506368000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2532506400000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2533506400000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2533506404000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2534506404000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2534506527000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2535506527000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2535506668000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2536506668000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2536506816000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2537506816000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2537506817000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2538506817000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2538506962000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2539506962000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2539507054000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2540507054000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2540507055000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2541507055000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2541507057000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2542507057000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2542507129000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2543507129000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2543507190000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2544507190000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2544507208000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2545507208000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2545507209000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2546507209000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2546507292000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2547507292000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2547507296000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2548507296000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2548507297000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2549507297000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2549507392000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2550507392000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2550507429000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2551507429000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2551507430000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2552507430000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2552507449000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2553507449000.  Starting simulation...
+info: Entering event queue @ 2554241989000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2554241991000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2555241991000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2555241999500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2556241999500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2556242000500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2557242000500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2557242001500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2558242001500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2558242077000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2559242077000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2559242141000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2560242141000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2560242242000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2561242242000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2561242255000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2562242255000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2562242375000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2563242375000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2563242389000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2564242389000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2564242391000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2565242391000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2565242463000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2566242463000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2566242542000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2567242542000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2567242688000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2568242688000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2568242730000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2569242730000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2569242838000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2570242838000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2570242940000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2571242940000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2571242946000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2572242946000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2572243030000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2573243030000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2573243031000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2574243031000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2574243077000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2575243077000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2575243233000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2576243233000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2576243261000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2577243261000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2577243262000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2578243262000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2578243340000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2579243340000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2579243341000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2580243341000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2580243342000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2581243342000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2581243343000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2582243343000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2582243344000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2583243344000.  Starting simulation...
+info: Entering event queue @ 2583243355000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2583243358500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2584243358500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2584243360500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2585243360500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2585243362500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2586243362500.  Starting simulation...
+info: Entering event queue @ 2586996937000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2586996939000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2587996939000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2587996940000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2588996940000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2588996941000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2589996941000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2589996942000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2590996942000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2590996944000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2591996944000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2591996945000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2592996945000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2592996946000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2593996946000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2593996952500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2594996952500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2594996953500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2595996953500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2595996958500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2596996958500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2596996959500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2597996959500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2597996960500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2598996960500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2598996961500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2599996961500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2599996963500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2600996963500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2600996975000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2601996975000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2601996976000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2602996976000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2602997129000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2603997129000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2603997243000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2604997243000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2604997244500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2605997244500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2605997245500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2606997245500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2606997246500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2607997246500.  Starting simulation...
+info: Entering event queue @ 2607997257000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2607997260500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2608997260500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2608997261500.  Starting simulation...
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
new file mode 100644
index 0000000..965d0e9
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
@@ -0,0 +1,1067 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  2.609477                       # Number of seconds simulated
+sim_ticks                                2609476867000                       # Number of ticks simulated
+final_tick                               2609476867000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 293996                       # Simulator instruction rate (inst/s)
+host_op_rate                                   374108                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            12742678359                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 397908                       # Number of bytes of host memory used
+host_seconds                                   204.78                       # Real time elapsed on the host
+sim_insts                                    60205243                       # Number of instructions simulated
+sim_ops                                      76610733                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::realview.clcd    122683392                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           349152                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4456460                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           356032                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4588440                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            132433668                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       349152                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       356032                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          705184                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3672640                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data       1522768                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data       1493500                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6688908                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      15335424                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             11658                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             69665                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              5563                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             71715                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15494028                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           57385                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data           380692                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data           373375                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               811452                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47014554                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker            25                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker            49                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              133802                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1707798                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              136438                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1758375                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                50751041                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         133802                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         136438                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             270240                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1407424                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data             583553                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data             572337                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2563314                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1407424                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47014554                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker           25                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker           49                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             133802                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            2291351                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             136438                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            2330712                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               53314355                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      15494028                       # Total number of read requests seen
+system.physmem.writeReqs                       811452                       # Total number of write requests seen
+system.physmem.cpureqs                         213833                       # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead                    991617792                       # Total number of bytes read from memory
+system.physmem.bytesWritten                  51932928                       # Total number of bytes written to memory
+system.physmem.bytesConsumedRd              132433668                       # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr                6688908                       # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ                       26                       # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite               4517                       # Reqs where no action is needed
+system.physmem.perBankRdReqs::0                968202                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1                968429                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2                967970                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3                967933                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4                967596                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5                967536                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6                967538                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7                967708                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8                974536                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9                967896                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10               968050                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11               968032                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12               968173                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13               968196                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14               968244                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15               967963                       # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0                 50183                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1                 50348                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2                 49939                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3                 49920                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4                 50621                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5                 50585                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6                 50546                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7                 50745                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8                 50919                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9                 50958                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10                50981                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11                51015                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12                51209                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13                51186                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14                51259                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15                51038                       # Track writes on a per bank basis
+system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
+system.physmem.totGap                    2609472479500                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::2                    6673                       # Categorize read packet sizes
+system.physmem.readPktSize::3                15335424                       # Categorize read packet sizes
+system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::6                  151931                       # Categorize read packet sizes
+system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
+system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
+system.physmem.writePktSize::0                      0                       # categorize write packet sizes
+system.physmem.writePktSize::1                      0                       # categorize write packet sizes
+system.physmem.writePktSize::2                 754067                       # categorize write packet sizes
+system.physmem.writePktSize::3                      0                       # categorize write packet sizes
+system.physmem.writePktSize::4                      0                       # categorize write packet sizes
+system.physmem.writePktSize::5                      0                       # categorize write packet sizes
+system.physmem.writePktSize::6                  57385                       # categorize write packet sizes
+system.physmem.writePktSize::7                      0                       # categorize write packet sizes
+system.physmem.writePktSize::8                      0                       # categorize write packet sizes
+system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::6                 4517                       # categorize neither packet sizes
+system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
+system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
+system.physmem.rdQLenPdf::0                   1117981                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    962159                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    962420                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    998543                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                   2811240                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::6                   5545406                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::8                     30744                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::13                    58397                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                     2158                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                     1941                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       75                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0                     35453                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                     35426                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                     35407                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::22                    35114                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.totQLat                   286738639625                       # Total cycles spent in queuing delays
+system.physmem.totMemAccLat              365542479625                       # Sum of mem lat for all requests
+system.physmem.totBusLat                  61976008000                       # Total cycles spent in databus access
+system.physmem.totBankLat                 16827832000                       # Total cycles spent in bank access
+system.physmem.avgQLat                       18506.43                       # Average queueing delay per request
+system.physmem.avgBankLat                     1086.09                       # Average bank access latency per request
+system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
+system.physmem.avgMemAccLat                  23592.52                       # Average memory access latency
+system.physmem.avgRdBW                         380.01                       # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW                          19.90                       # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW                  50.75                       # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW                   2.56                       # Average consumed write bandwidth in MB/s
+system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil                           2.50                       # Data bus utilization in percentage
+system.physmem.avgRdQLen                         0.14                       # Average read queue length over time
+system.physmem.avgWrQLen                         1.25                       # Average write queue length over time
+system.physmem.readRowHits                   15452119                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    785190                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   99.73                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  96.76                       # Row buffer hit rate for writes
+system.physmem.avgGap                       160036.53                       # Average gap between requests
+system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                         61820                       # number of replacements
+system.l2c.tagsinuse                     50921.903557                       # Cycle average of tags in use
+system.l2c.total_refs                         1697937                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        127204                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         13.348142                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                  2557805301500                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        37911.972595                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.dtb.walker       0.000184                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.itb.walker       0.000639                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          3578.783807                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          2862.372936                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst          3416.906879                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data          3151.866517                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.578491                       # Average percentage of cache occupancy
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+system.l2c.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.054608                       # Average percentage of cache occupancy
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+system.l2c.ReadReq_hits::cpu0.dtb.walker         9713                       # number of ReadReq hits
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+system.l2c.ReadReq_hits::total                1241218                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          596393                       # number of Writeback hits
+system.l2c.Writeback_hits::total               596393                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data              17                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data               9                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  26                       # number of UpgradeReq hits
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+system.l2c.UpgradeReq_accesses::total            2904                       # number of UpgradeReq accesses(hits+misses)
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+system.l2c.overall_accesses::cpu0.data         312888                       # number of overall (read+write) accesses
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+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000103                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000579                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.012747                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.026592                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.012118                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.025188                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.016216                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.988340                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.993776                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.991047                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.538968                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.535983                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.537444                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000103                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000579                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.012747                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.225151                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.012118                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.230060                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.101746                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000103                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000579                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.012747                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.225151                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.012118                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.230060                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.101746                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        69000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        33750                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 49316.045220                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 50550.922292                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49697.195758                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 53109.989485                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 50608.485263                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   109.299098                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   205.984690                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   157.574705                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44784.165506                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 45955.895809                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 45380.633456                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        69000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker        33750                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 49316.045220                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 45201.321561                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 49697.195758                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 46425.008619                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 46077.101647                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        69000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker        33750                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 49316.045220                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 45201.321561                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 49697.195758                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 46425.008619                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 46077.101647                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks::writebacks               57385                       # number of writebacks
+system.l2c.writebacks::total                    57385                       # number of writebacks
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            1                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst         5042                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data         5096                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         5563                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         4755                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           20459                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         1441                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         1437                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         2878                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        65351                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        67760                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        133111                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst         5042                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        70447                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         5563                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        72515                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           153570                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker            1                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst         5042                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        70447                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         5563                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        72515                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          153570                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker        56002                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        42004                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    184664530                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data    192314139                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    205852055                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    191753450                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total    774682180                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     14466412                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     14371437                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     28837849                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2097339236                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   2255705289                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   4353044525                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker        56002                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        42004                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    184664530                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   2289653375                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    205852055                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   2447458739                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   5127726705                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker        56002                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        42004                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    184664530                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   2289653375                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    205852055                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   2447458739                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   5127726705                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    197466551                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  84525516564                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  82169986021                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 166892969136                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4630774338                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   4531933372                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   9162707710                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data        76004                       # number of LoadLockedReq MSHR uncacheable cycles
+system.l2c.LoadLockedReq_mshr_uncacheable_latency::total        76004                       # number of LoadLockedReq MSHR uncacheable cycles
+system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data        30003                       # number of StoreCondReq MSHR uncacheable cycles
+system.l2c.StoreCondReq_mshr_uncacheable_latency::total        30003                       # number of StoreCondReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    197466551                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data  89156290902                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data  86701919393                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 176055676846                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000103                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000579                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.012747                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.026592                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.012118                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.025188                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.016216                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.988340                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.993776                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.991047                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.538968                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.535983                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.537444                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000103                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000579                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.012747                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.225151                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.012118                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.230060                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.101746                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000103                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000579                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.012747                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.225151                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.012118                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.230060                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.101746                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        56002                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        21002                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 36625.253868                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 37738.253336                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 37003.784828                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40326.698212                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 37865.104844                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10039.147814                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10020.100417                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32093.452832                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 33289.629413                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 32702.365131                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        56002                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        21002                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 36625.253868                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32501.786804                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 37003.784828                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33751.068593                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 33390.158918                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        56002                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        21002                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36625.253868                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32501.786804                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 37003.784828                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33751.068593                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 33390.158918                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average LoadLockedReq mshr uncacheable latency
+system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total          inf                       # average LoadLockedReq mshr uncacheable latency
+system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average StoreCondReq mshr uncacheable latency
+system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total          inf                       # average StoreCondReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
+system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
+system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
+system.cpu0.dtb.read_hits                     7346324                       # DTB read hits
+system.cpu0.dtb.read_misses                      6876                       # DTB read misses
+system.cpu0.dtb.write_hits                    5393725                       # DTB write hits
+system.cpu0.dtb.write_misses                     1788                       # DTB write misses
+system.cpu0.dtb.flush_tlb                        1277                       # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid                739                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                     29                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                    6380                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                   138                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults                      236                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                 7353200                       # DTB read accesses
+system.cpu0.dtb.write_accesses                5395513                       # DTB write accesses
+system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
+system.cpu0.dtb.hits                         12740049                       # DTB hits
+system.cpu0.dtb.misses                           8664                       # DTB misses
+system.cpu0.dtb.accesses                     12748713                       # DTB accesses
+system.cpu0.itb.inst_hits                    30077314                       # ITB inst hits
+system.cpu0.itb.inst_misses                      3618                       # ITB inst misses
+system.cpu0.itb.read_hits                           0                       # DTB read hits
+system.cpu0.itb.read_misses                         0                       # DTB read misses
+system.cpu0.itb.write_hits                          0                       # DTB write hits
+system.cpu0.itb.write_misses                        0                       # DTB write misses
+system.cpu0.itb.flush_tlb                        1277                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid                739                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                     29                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                    2643                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
+system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
+system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
+system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.read_accesses                       0                       # DTB read accesses
+system.cpu0.itb.write_accesses                      0                       # DTB write accesses
+system.cpu0.itb.inst_accesses                30080932                       # ITB inst accesses
+system.cpu0.itb.hits                         30077314                       # DTB hits
+system.cpu0.itb.misses                           3618                       # DTB misses
+system.cpu0.itb.accesses                     30080932                       # DTB accesses
+system.cpu0.numCycles                      2667978103                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.committedInsts                   29443364                       # Number of instructions committed
+system.cpu0.committedOps                     37313873                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             33552683                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  4308                       # Number of float alu accesses
+system.cpu0.num_func_calls                     997498                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      3872350                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    33552683                       # number of integer instructions
+system.cpu0.num_fp_insts                         4308                       # number of float instructions
+system.cpu0.num_int_register_reads          192457043                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          36187608                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                3214                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes               1096                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                     13317945                       # number of memory refs
+system.cpu0.num_load_insts                    7675788                       # Number of load instructions
+system.cpu0.num_store_insts                   5642157                       # Number of store instructions
+system.cpu0.num_idle_cycles              1511306252.685236                       # Number of idle cycles
+system.cpu0.num_busy_cycles              1156671850.314764                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.433539                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.566461                       # Percentage of idle cycles
+system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu0.kern.inst.quiesce                   83014                       # number of quiesce instructions executed
+system.cpu0.icache.replacements                855749                       # number of replacements
+system.cpu0.icache.tagsinuse               510.984146                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                60643040                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                856261                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                 70.823078                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle           18731806000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst   165.100321                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_blocks::cpu1.inst   345.883825                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.322462                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::cpu1.inst     0.675554                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.998016                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst     29681003                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     30962037                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       60643040                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     29681003                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     30962037                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        60643040                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     29681003                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     30962037                       # number of overall hits
+system.cpu0.icache.overall_hits::total       60643040                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       396311                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       459950                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       856261                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       396311                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       459950                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        856261                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       396311                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       459950                       # number of overall misses
+system.cpu0.icache.overall_misses::total       856261                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5359552000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   6210691500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  11570243500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   5359552000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   6210691500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  11570243500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   5359552000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   6210691500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  11570243500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     30077314                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     31421987                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     61499301                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     30077314                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     31421987                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     61499301                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     30077314                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     31421987                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     61499301                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.013176                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014638                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.013923                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.013176                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014638                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.013923                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.013176                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014638                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.013923                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13523.601414                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13502.970975                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13512.519547                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13523.601414                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13502.970975                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13512.519547                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13523.601414                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13502.970975                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13512.519547                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       396311                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       459950                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       856261                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       396311                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       459950                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       856261                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       396311                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       459950                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       856261                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4566930000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   5290791500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   9857721500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4566930000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   5290791500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   9857721500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4566930000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   5290791500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   9857721500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    288141500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    288141500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    288141500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    288141500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.013176                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014638                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.013923                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.013176                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.014638                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.013923                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.013176                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.014638                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.013923                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11523.601414                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11502.970975                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11512.519547                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11523.601414                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11502.970975                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11512.519547                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11523.601414                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11502.970975                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11512.519547                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.replacements                627576                       # number of replacements
+system.cpu0.dcache.tagsinuse               511.914984                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                23658480                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs                628088                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                 37.667461                       # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle             460735000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::cpu0.data   142.165809                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_blocks::cpu1.data   369.749176                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.277668                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::cpu1.data     0.722166                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.999834                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6448677                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      6748535                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       13197212                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      4778089                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      5196213                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       9974302                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       105697                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       130631                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       236328                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       111573                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data       136161                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       247734                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     11226766                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data     11944748                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        23171514                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     11226766                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data     11944748                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       23171514                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       185759                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       183249                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       369008                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       122710                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data       127868                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       250578                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         5877                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         5530                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        11407                       # number of LoadLockedReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       308469                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       311117                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        619586                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       308469                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       311117                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       619586                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   2627565000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2598558000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   5226123000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   3886745500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   4117005000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   8003750500                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     81831500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     73520000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    155351500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data   6514310500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   6715563000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  13229873500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data   6514310500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   6715563000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  13229873500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      6634436                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      6931784                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     13566220                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      4900799                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      5324081                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     10224880                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       111574                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       136161                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       247735                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       111573                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       136161                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       247734                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     11535235                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     12255865                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     23791100                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     11535235                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     12255865                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     23791100                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.027999                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.026436                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.027201                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.025039                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.024017                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.024507                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.052674                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.040614                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.046045                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026741                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.025385                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.026043                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.026741                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.025385                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.026043                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14145.021237                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14180.475746                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14162.627911                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31674.236004                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 32197.305033                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 31941.154052                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13924.025864                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13294.755877                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13618.962041                       # average LoadLockedReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21118.201505                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21585.329635                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 21352.763781                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21118.201505                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21585.329635                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 21352.763781                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.dcache.writebacks::writebacks       596393                       # number of writebacks
+system.cpu0.dcache.writebacks::total           596393                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       185759                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       183249                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       369008                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       122710                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       127868                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       250578                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         5877                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5530                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        11407                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       308469                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       311117                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       619586                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       308469                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       311117                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       619586                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2256047000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2232060000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4488107000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   3641325500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   3861269000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7502594500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     70077500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     62460000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    132537500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   5897372500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   6093329000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  11990701500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   5897372500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   6093329000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  11990701500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  92330241000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  89759244500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182089485500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   9446181000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   9255751500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  18701932500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data       117500                       # number of LoadLockedReq MSHR uncacheable cycles
+system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total       117500                       # number of LoadLockedReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data        69000                       # number of StoreCondReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total        69000                       # number of StoreCondReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 101776422000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  99014996000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 200791418000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.027999                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.026436                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.027201                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025039                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.024017                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.024507                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.052674                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.040614                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.046045                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.026741                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.025385                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.026043                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026741                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.025385                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.026043                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12145.021237                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12180.475746                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12162.627911                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29674.236004                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30197.305033                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29941.154052                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11924.025864                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11294.755877                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11618.962041                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19118.201505                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19585.329635                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19352.763781                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19118.201505                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19585.329635                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19352.763781                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average LoadLockedReq mshr uncacheable latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total          inf                       # average LoadLockedReq mshr uncacheable latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average StoreCondReq mshr uncacheable latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total          inf                       # average StoreCondReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
+system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
+system.cpu1.dtb.read_hits                     7651718                       # DTB read hits
+system.cpu1.dtb.read_misses                      6996                       # DTB read misses
+system.cpu1.dtb.write_hits                    5838563                       # DTB write hits
+system.cpu1.dtb.write_misses                     1808                       # DTB write misses
+system.cpu1.dtb.flush_tlb                        1276                       # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid                700                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                     34                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                    6464                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   130                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
+system.cpu1.dtb.perms_faults                      216                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 7658714                       # DTB read accesses
+system.cpu1.dtb.write_accesses                5840371                       # DTB write accesses
+system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
+system.cpu1.dtb.hits                         13490281                       # DTB hits
+system.cpu1.dtb.misses                           8804                       # DTB misses
+system.cpu1.dtb.accesses                     13499085                       # DTB accesses
+system.cpu1.itb.inst_hits                    31421987                       # ITB inst hits
+system.cpu1.itb.inst_misses                      3616                       # ITB inst misses
+system.cpu1.itb.read_hits                           0                       # DTB read hits
+system.cpu1.itb.read_misses                         0                       # DTB read misses
+system.cpu1.itb.write_hits                          0                       # DTB write hits
+system.cpu1.itb.write_misses                        0                       # DTB write misses
+system.cpu1.itb.flush_tlb                        1276                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid                700                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                     34                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                    2808                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
+system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
+system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
+system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.read_accesses                       0                       # DTB read accesses
+system.cpu1.itb.write_accesses                      0                       # DTB write accesses
+system.cpu1.itb.inst_accesses                31425603                       # ITB inst accesses
+system.cpu1.itb.hits                         31421987                       # DTB hits
+system.cpu1.itb.misses                           3616                       # DTB misses
+system.cpu1.itb.accesses                     31425603                       # DTB accesses
+system.cpu1.numCycles                      2550975631                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.committedInsts                   30761879                       # Number of instructions committed
+system.cpu1.committedOps                     39296860                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             35324832                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  5961                       # Number of float alu accesses
+system.cpu1.num_func_calls                    1142639                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      4076383                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    35324832                       # number of integer instructions
+system.cpu1.num_fp_insts                         5961                       # number of float instructions
+system.cpu1.num_int_register_reads          202353181                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          37998347                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                4279                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes               1684                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                     14079956                       # number of memory refs
+system.cpu1.num_load_insts                    7986446                       # Number of load instructions
+system.cpu1.num_store_insts                   6093510                       # Number of store instructions
+system.cpu1.num_idle_cycles              3341647478.137703                       # Number of idle cycles
+system.cpu1.num_busy_cycles              -790671847.137703                       # Number of busy cycles
+system.cpu1.not_idle_fraction               -0.309949                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    1.309949                       # Percentage of idle cycles
+system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
+system.iocache.replacements                         0                       # number of replacements
+system.iocache.tagsinuse                            0                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
+system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
+system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1128670778319                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1128670778319                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1128670778319                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1128670778319                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal
new file mode 100644
index 0000000..8dd192b
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal
Binary files differ