arch-arm: Implement LoadAcquire/StoreRelease in AArch32
This patch is implementing LoadAcquire/StoreRelease instructions in
AArch32, which were added in ARMv8-A only and where not present in
ARMv7.
Change-Id: I5e26459971d0b183a955cd7b0c9c7eaffef453be
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15817
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index 3edeb38..6e5122c 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2010-2011 ARM Limited
+// Copyright (c) 2010-2011,2019 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -173,11 +173,17 @@
elif self.flavor == "iprefetch":
self.memFlags.append("Request::PREFETCH")
self.instFlags = ['IsInstPrefetch']
- elif self.flavor == "exclusive":
- self.memFlags.append("Request::LLSC")
elif self.flavor == "normal":
self.memFlags.append("ArmISA::TLB::AllowUnaligned")
+ if self.flavor in ("exclusive", "acex"):
+ self.memFlags.append("Request::LLSC")
+
+ if self.flavor in ("acquire", "acex"):
+ self.instFlags.extend(["IsMemBarrier",
+ "IsWriteBarrier",
+ "IsReadBarrier"])
+
# Disambiguate the class name for different flavors of loads
if self.flavor != "normal":
self.Name = "%s_%s" % (self.name.upper(), self.Name)
@@ -235,8 +241,9 @@
# Build the default class name
self.Name = self.nameFunc(self.post, self.add, self.writeback)
+ self.instFlags = []
# Add memory request flags where necessary
- if self.flavor == "exclusive":
+ if self.flavor in ("exclusive", "acex"):
self.memFlags.append("Request::LLSC")
self.memFlags.append("ArmISA::TLB::AlignDoubleWord")
else:
@@ -246,6 +253,11 @@
if self.flavor != "normal":
self.Name = "%s_%s" % (self.name.upper(), self.Name)
+ if self.flavor in ("acquire", "acex"):
+ self.instFlags.extend(["IsMemBarrier",
+ "IsWriteBarrier",
+ "IsReadBarrier"])
+
def emit(self):
# Address computation code
eaCode = "EA = Base"
@@ -279,7 +291,7 @@
wbDecl = None
if self.writeback:
wbDecl = self.wbDecl
- self.emitHelper(base, wbDecl)
+ self.emitHelper(base, wbDecl, self.instFlags)
def loadDoubleImmClassName(post, add, writeback):
return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False)
@@ -365,6 +377,14 @@
LoadImm("ldrexb", False, True, False, size=1, flavor="exclusive").emit()
LoadDoubleImm("ldrexd", False, True, False, flavor="exclusive").emit()
+ LoadImm("lda", False, True, False, size=4, flavor="acquire").emit()
+ LoadImm("ldah", False, True, False, size=2, flavor="acquire").emit()
+ LoadImm("ldab", False, True, False, size=1, flavor="acquire").emit()
+ LoadImm("ldaex", False, True, False, size=4, flavor="acex").emit()
+ LoadImm("ldaexh", False, True, False, size=2, flavor="acex").emit()
+ LoadImm("ldaexb", False, True, False, size=1, flavor="acex").emit()
+ LoadDoubleImm("ldaexd", False, True, False, flavor="acex").emit()
+
LoadImm("vldr", False, True, False, size=4, flavor="fp").emit()
LoadImm("vldr", False, False, False, size=4, flavor="fp").emit()
LoadDoubleImm("vldr", False, True, False, flavor="fp").emit()
