commit 72d1d2930fc2b8ef6d32ec2ce2eabbac00684159
author Tuan Ta <qtt2@cornell.edu> Mon Apr 02 16:21:28 2018 -0400
committer Tuan Ta <qtt2@cornell.edu> Fri Feb 08 15:25:30 2019 +0000
tree 30e4dff525d704bf39e446e1a9ee80ebb7418635
parent cf45f22369f85397f113918a4f773b2613f0e19b

arch-riscv: initialize RISC-V's thread pointer register in clone syscall

This patch initializes thread pointer register to Thread Local Storage
(TLS)'s pointer given to a clone system call.

Change-Id: I03e2cf4763e6a0ed31f357772a513a05e1e3461b
Reviewed-on: https://gem5-review.googlesource.com/c/9622
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

src/arch/riscv/linux/linux.hh

diff --git a/src/arch/riscv/linux/linux.hh b/src/arch/riscv/linux/linux.hh
index 23b4fd5..441550a 100644
--- a/src/arch/riscv/linux/linux.hh
+++ b/src/arch/riscv/linux/linux.hh
@@ -196,6 +196,8 @@
               uint64_t stack, uint64_t tls)
     {
         RiscvISA::copyRegs(ptc, ctc);
+        if (flags & TGT_CLONE_SETTLS)
+            ctc->setIntReg(RiscvISA::ThreadPointerReg, tls);
         if (stack)
             ctc->setIntReg(RiscvISA::StackPointerReg, stack);
     }