commit 7eb0fb8b6ebffcb39b61964d4c7387455c262aae
author Andreas Sandberg <Andreas.Sandberg@ARM.com> Mon Jan 07 13:05:41 2013 -0500
committer Andreas Sandberg <Andreas.Sandberg@ARM.com> Mon Jan 07 13:05:41 2013 -0500
tree 99ded4ee2e8740b415c0b7b5ad7b808fbcbe405e
parent 94561dd5268d139b721561166cbce94170701c2c

cpu: Check that the memory system is in the correct mode

This patch adds checks to all CPU models to make sure that the memory
system is in the correct mode at startup and when resuming after a
drain.  Previously, we only checked that the memory system was in the
right mode when resuming. This is inadequate since this is a
configuration error that should be detected at startup as well as when
resuming. Additionally, since the check was done using an assert, it
wasn't performed when NDEBUG was set (e.g., the fast target).

src/cpu/inorder/cpu.cc

diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 1ca0657..3582e55 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -787,6 +787,12 @@
 {
     BaseCPU::init();
 
+    if (!params()->defer_registration &&
+        system->getMemoryMode() != Enums::timing) {
+        fatal("The in-order CPU requires the memory system to be in "
+              "'timing' mode.\n");
+    }
+
     for (ThreadID tid = 0; tid < numThreads; ++tid) {
         // Set noSquashFromTC so that the CPU doesn't squash when initially
         // setting up registers.

src/cpu/o3/cpu.cc

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 9de1bf6..2e972b7 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -647,6 +647,12 @@
 {
     BaseCPU::init();
 
+    if (!params()->defer_registration &&
+        system->getMemoryMode() != Enums::timing) {
+        fatal("The O3 CPU requires the memory system to be in "
+              "'timing' mode.\n");
+    }
+
     for (ThreadID tid = 0; tid < numThreads; ++tid) {
         // Set noSquashFromTC so that the CPU doesn't squash when initially
         // setting up registers.
@@ -1174,7 +1180,10 @@
     if (_status == SwitchedOut)
         return;
 
-    assert(system->getMemoryMode() == Enums::timing);
+    if (system->getMemoryMode() != Enums::timing) {
+        fatal("The O3 CPU requires the memory system to be in "
+              "'timing' mode.\n");
+    }
 
     if (!tickEvent.scheduled())
         schedule(tickEvent, nextCycle());

src/cpu/simple/atomic.cc

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index e63d998..fffbb55 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -83,6 +83,12 @@
 {
     BaseCPU::init();
 
+    if (!params()->defer_registration &&
+        system->getMemoryMode() != Enums::atomic) {
+        fatal("The atomic CPU requires the memory system to be in "
+              "'atomic' mode.\n");
+    }
+
     // Initialise the ThreadContext's memory proxies
     tcBase()->initMemProxies(tcBase());
 
@@ -155,7 +161,10 @@
         return;
 
     DPRINTF(SimpleCPU, "Resume\n");
-    assert(system->getMemoryMode() == Enums::atomic);
+    if (system->getMemoryMode() != Enums::atomic) {
+        fatal("The atomic CPU requires the memory system to be in "
+              "'atomic' mode.\n");
+    }
 
     setDrainState(Drainable::Running);
     if (thread->status() == ThreadContext::Active) {

src/cpu/simple/timing.cc

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 4176430..d3959c8 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -66,6 +66,12 @@
 {
     BaseCPU::init();
 
+    if (!params()->defer_registration &&
+        system->getMemoryMode() != Enums::timing) {
+        fatal("The timing CPU requires the memory system to be in "
+              "'timing' mode.\n");
+    }
+
     // Initialise the ThreadContext's memory proxies
     tcBase()->initMemProxies(tcBase());
 
@@ -140,7 +146,10 @@
 {
     DPRINTF(SimpleCPU, "Resume\n");
     if (_status != SwitchedOut && _status != Idle) {
-        assert(system->getMemoryMode() == Enums::timing);
+        if (system->getMemoryMode() != Enums::timing) {
+            fatal("The timing CPU requires the memory system to be in "
+                  "'timing' mode.\n");
+        }
 
         if (fetchEvent.scheduled())
            deschedule(fetchEvent);