tree c327a2d7211e1c3ddf26e531c55d65ad7c6d4d1d
parent ff7fc9de6955ba3e00898eb703b3da1a15fb417c
author Curtis Dunham <Curtis.Dunham@arm.com> 1525734368 -0500
committer Giacomo Travaglini <giacomo.travaglini@arm.com> 1546511902 +0000

arm: properly handle RES0/1 for SCTLRs

They were being treated as RAZ/RAO, which is incorrect.
Put the access masks in the register metadatabase now that we have one.

Also fix this for HVBAR.

Change-Id: I097c847e35be2d59fb8235fc621bb061ef514cfb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/10401
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>