commit 8e1a1418188b96ad5f6b27ab82aa463fc95f4179
author Javier Setoain <javier.setoain@arm.com> Thu Mar 14 18:06:05 2019 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Mon Mar 25 09:40:46 2019 +0000
tree 2fef7d24229e7c2ccea61ed13243237369a1b2bb
parent f838a332be4b98ddc039f388bef1e307567db37c

arch-arm: Add missing fall-through defaults

Change-Id: Ie64b83d754c4719a77c7788879be71304a9b786e
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17289
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andrea Mondelli <Andrea.Mondelli@ucf.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

src/arch/arm/isa/formats/sve_2nd_level.isa

diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa b/src/arch/arm/isa/formats/sve_2nd_level.isa
index 3c5e01c..ff7e50e 100644
--- a/src/arch/arm/isa/formats/sve_2nd_level.isa
+++ b/src/arch/arm/isa/formats/sve_2nd_level.isa
@@ -118,6 +118,7 @@
                         return new Unknown64(machInst);
                     }
                 }
+                break;
             }
           case 0x3:
             {
@@ -532,6 +533,7 @@
                             return new SveIndexII<int64_t>(machInst,
                                     zd, imm5, imm5b);
                     }
+                    break;
                 }
             case 1:
                 { // INDEX (scalar, immediate)
@@ -552,6 +554,7 @@
                             return new SveIndexRI<int64_t>(machInst,
                                     zd, zn, imm5);
                     }
+                    break;
                 }
             case 2:
                 { // INDEX (immediate, scalar)
@@ -572,6 +575,7 @@
                             return new SveIndexIR<int64_t>(machInst,
                                     zd, imm5, zm);
                     }
+                    break;
                 }
             case 3:
                 { // INDEX (scalars)

src/arch/arm/isa/formats/sve_top_level.isa

diff --git a/src/arch/arm/isa/formats/sve_top_level.isa b/src/arch/arm/isa/formats/sve_top_level.isa
index f4f1ab5..b8e1d46 100644
--- a/src/arch/arm/isa/formats/sve_top_level.isa
+++ b/src/arch/arm/isa/formats/sve_top_level.isa
@@ -128,6 +128,7 @@
                         return decodeSveIntArithUnaryPred(machInst);
                     }
                 }
+                break;
             }
           case 0x1:
             {
@@ -166,6 +167,7 @@
                   case 0x3:
                     return decodeSveElemCount(machInst);
                 }
+                break;
             }
           case 0x2:
             if (bits(machInst, 20)) {
@@ -195,6 +197,7 @@
                   case 0x3:
                     return decodeSveSelVec(machInst);
                 }
+                break;
             }
           case 0x4:
             return decodeSveIntCmpVec(machInst);
@@ -279,6 +282,7 @@
                               case 0x3:
                                   return decodeSveFpAccumReduc(machInst);
                             }
+                            break;
                         }
                       case 0x2:
                         return decodeSveFpArithPred(machInst);
@@ -286,6 +290,7 @@
                         return decodeSveFpUnaryPred(machInst);
                     }
                 }
+                break;
             }
           case 0x3:
             return decodeSveFpFusedMulAdd(machInst);