
---------- Begin Simulation Statistics ----------
sim_seconds                                  5.194946                       # Number of seconds simulated
sim_ticks                                5194946000500                       # Number of ticks simulated
final_tick                               5194946000500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 930999                       # Simulator instruction rate (inst/s)
host_op_rate                                  1794485                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            37656529565                       # Simulator tick rate (ticks/s)
host_mem_usage                                 609616                       # Number of bytes of host memory used
host_seconds                                   137.96                       # Real time elapsed on the host
sim_insts                                   128436892                       # Number of instructions simulated
sim_ops                                     247560077                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            821248                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9031168                       # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9881152                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       821248                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          821248                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8151616                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8151616                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              12832                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             141112                       # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                154393                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          127369                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               127369                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker             12                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               158086                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1738453                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide         5458                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1902070                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          158086                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             158086                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1569144                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1569144                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1569144                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker            12                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              158086                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1738453                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide         5458                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3471214                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        154393                       # Number of read requests accepted
system.physmem.writeReqs                       127369                       # Number of write requests accepted
system.physmem.readBursts                      154393                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     127369                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  9872000                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9152                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8149824                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   9881152                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8151616                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      143                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10087                       # Per bank write bursts
system.physmem.perBankRdBursts::1                9534                       # Per bank write bursts
system.physmem.perBankRdBursts::2                9814                       # Per bank write bursts
system.physmem.perBankRdBursts::3                9653                       # Per bank write bursts
system.physmem.perBankRdBursts::4               10130                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9948                       # Per bank write bursts
system.physmem.perBankRdBursts::6                9317                       # Per bank write bursts
system.physmem.perBankRdBursts::7                9200                       # Per bank write bursts
system.physmem.perBankRdBursts::8                8918                       # Per bank write bursts
system.physmem.perBankRdBursts::9                9357                       # Per bank write bursts
system.physmem.perBankRdBursts::10               9071                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9331                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9713                       # Per bank write bursts
system.physmem.perBankRdBursts::13               9915                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10131                       # Per bank write bursts
system.physmem.perBankRdBursts::15              10131                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8252                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7742                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7578                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7567                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7987                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8326                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7984                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7858                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7447                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8118                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7706                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7949                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8417                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8510                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8023                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7877                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          15                       # Number of times write queue was full causing retry
system.physmem.totGap                    5194945939500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  154393                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 127369                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    151022                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      2785                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        67                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        59                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        39                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        34                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        35                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        36                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2198                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3757                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     7707                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     7371                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6314                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6198                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6474                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7322                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6886                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     7581                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8523                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7183                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7744                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     9513                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7269                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6984                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7148                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1628                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      270                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      107                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      141                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      146                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       98                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       76                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       71                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      133                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       29                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       40                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        56869                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      316.898416                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     189.066814                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     329.232113                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          20064     35.28%     35.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        13820     24.30%     59.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6395     11.25%     70.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3441      6.05%     76.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2422      4.26%     81.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1595      2.80%     83.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1163      2.05%     85.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          983      1.73%     87.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         6986     12.28%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          56869                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5701                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        27.056657                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      634.190971                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           5700     99.98%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5701                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5700                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        22.339649                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.500075                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       17.394307                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            4849     85.07%     85.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             101      1.77%     86.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              44      0.77%     87.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              52      0.91%     88.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              17      0.30%     88.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              15      0.26%     89.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              60      1.05%     90.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               6      0.11%     90.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             207      3.63%     93.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              10      0.18%     94.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               6      0.11%     94.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              16      0.28%     94.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67              91      1.60%     96.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               6      0.11%     96.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               3      0.05%     96.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              36      0.63%     96.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83             144      2.53%     99.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.02%     99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.02%     99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            11      0.19%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.02%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             3      0.05%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             9      0.16%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.02%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.02%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             4      0.07%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             3      0.05%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-211             2      0.04%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5700                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1573374325                       # Total ticks spent queuing
system.physmem.totMemAccLat                4465561825                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    771250000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10200.16                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  28950.16                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.90                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.57                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.90                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.57                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.80                       # Average write queue length when enqueuing
system.physmem.readRowHits                     125550                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     99170                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.39                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  77.86                       # Row buffer hit rate for writes
system.physmem.avgGap                     18437354.72                       # Average gap between requests
system.physmem.pageHitRate                      79.80                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  210916440                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  115083375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 605927400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                410119200                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           339308180640                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           137084456790                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           2996714193750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             3474448877595                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.814114                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   4985194974722                       # Time in different power states
system.physmem_0.memoryStateTime::REF    173470440000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     36280536278                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  218998080                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  119493000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 597214800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                415018080                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           339308180640                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           137426526900                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           2996414132250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             3474499563750                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.823871                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   4984690777488                       # Time in different power states
system.physmem_1.memoryStateTime::REF    173470440000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     36784611512                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.numCycles                      10389892001                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
system.cpu.committedInsts                   128436892                       # Number of instructions committed
system.cpu.committedOps                     247560077                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             232158810                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
system.cpu.num_func_calls                     2315811                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     23152999                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    232158810                       # number of integer instructions
system.cpu.num_fp_insts                            48                       # number of float instructions
system.cpu.num_int_register_reads           434959716                       # number of times the integer registers were read
system.cpu.num_int_register_writes          197963277                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                   48                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_cc_register_reads            132873102                       # number of times the CC registers were read
system.cpu.num_cc_register_writes            95461248                       # number of times the CC registers were written
system.cpu.num_mem_refs                      22321002                       # number of memory refs
system.cpu.num_load_insts                    13911426                       # Number of load instructions
system.cpu.num_store_insts                    8409576                       # Number of store instructions
system.cpu.num_idle_cycles               9774021635.086119                       # Number of idle cycles
system.cpu.num_busy_cycles               615870365.913881                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.059276                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.940724                       # Percentage of idle cycles
system.cpu.Branches                          26327440                       # Number of branches fetched
system.cpu.op_class::No_OpClass                172203      0.07%      0.07% # Class of executed instruction
system.cpu.op_class::IntAlu                 224810530     90.81%     90.88% # Class of executed instruction
system.cpu.op_class::IntMult                   140088      0.06%     90.94% # Class of executed instruction
system.cpu.op_class::IntDiv                    122745      0.05%     90.99% # Class of executed instruction
system.cpu.op_class::FloatAdd                       0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::FloatCvt                      16      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc                  0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::MemRead                 13906455      5.62%     96.60% # Class of executed instruction
system.cpu.op_class::MemWrite                 8409576      3.40%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                  247561613                       # Class of executed instruction
system.cpu.dcache.tags.replacements           1623668                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.995482                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            20139358                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1624180                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             12.399708                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          81561500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.995482                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999991                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999991                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          353                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           58                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          88717633                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         88717633                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     12002599                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        12002599                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8075450                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8075450                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        59092                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         59092                       # number of SoftPFReq hits
system.cpu.dcache.demand_hits::cpu.data      20078049                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         20078049                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     20137141                       # number of overall hits
system.cpu.dcache.overall_hits::total        20137141                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       907290                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        907290                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       326130                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       326130                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       402796                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       402796                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      1233420                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1233420                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1636216                       # number of overall misses
system.cpu.dcache.overall_misses::total       1636216                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  13559380500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  13559380500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  18441171467                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  18441171467                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  32000551967                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  32000551967                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  32000551967                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  32000551967                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     12909889                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     12909889                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8401580                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8401580                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       461888                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       461888                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21311469                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21311469                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21773357                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21773357                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070279                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.070279                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.038818                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.038818                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.872064                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.872064                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.057876                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.057876                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.075148                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.075148                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14944.924445                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14944.924445                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56545.461831                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 56545.461831                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25944.570355                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 25944.570355                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19557.657404                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 19557.657404                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        19286                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               514                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    37.521401                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks      1540773                       # number of writebacks
system.cpu.dcache.writebacks::total           1540773                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          285                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          285                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data         9475                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total         9475                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data         9760                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total         9760                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data         9760                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total         9760                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       907005                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       907005                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       316655                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       316655                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402762                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       402762                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1223660                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1223660                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1626422                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1626422                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data       546346                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total       546346                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        13920                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        13920                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       560266                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total       560266                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12650383500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  12650383500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17142668967                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  17142668967                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   6518448000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   6518448000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29793052467                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  29793052467                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  36311500467                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  36311500467                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  95132085000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  95132085000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  95132085000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  95132085000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.070257                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.070257                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037690                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037690                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.871991                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.871991                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.057418                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.057418                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074698                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.074698                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13947.424215                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13947.424215                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54136.738618                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54136.738618                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16184.366946                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16184.366946                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24347.492332                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 24347.492332                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22326.001780                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22326.001780                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 174124.245442                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174124.245442                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 169798.069131                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 169798.069131                       # average overall mshr uncacheable latency
system.cpu.dtb_walker_cache.tags.replacements         7581                       # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse     5.052199                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs        13343                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs         7597                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs     1.756351                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 5163352546000                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.052199                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.315762                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total     0.315762                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           16                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dtb_walker_cache.tags.tag_accesses        53059                       # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses        53059                       # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        13343                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total        13343                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        13343                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total        13343                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        13343                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total        13343                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8791                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total         8791                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8791                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total         8791                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8791                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total         8791                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker     96450500                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total     96450500                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker     96450500                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total     96450500                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker     96450500                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total     96450500                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        22134                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total        22134                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        22134                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total        22134                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        22134                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total        22134                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.397172                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.397172                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.397172                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.397172                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.397172                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.397172                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10971.504948                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10971.504948                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10971.504948                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10971.504948                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10971.504948                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10971.504948                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.writebacks::writebacks         2983                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total         2983                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         8791                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         8791                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         8791                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total         8791                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         8791                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total         8791                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     87659500                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     87659500                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     87659500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     87659500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     87659500                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     87659500                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.397172                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.397172                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.397172                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.397172                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.397172                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.397172                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  9971.504948                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9971.504948                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  9971.504948                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  9971.504948                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  9971.504948                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  9971.504948                       # average overall mshr miss latency
system.cpu.icache.tags.replacements            790489                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.213579                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           144635934                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            791001                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            182.851771                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      164551519500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.213579                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.996511                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.996511                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          161                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          292                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         146217950                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        146217950                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    144635934                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       144635934                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     144635934                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        144635934                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    144635934                       # number of overall hits
system.cpu.icache.overall_hits::total       144635934                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       791008                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        791008                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       791008                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         791008                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       791008                       # number of overall misses
system.cpu.icache.overall_misses::total        791008                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  11846341000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  11846341000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  11846341000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  11846341000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  11846341000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  11846341000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    145426942                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    145426942                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    145426942                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    145426942                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    145426942                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    145426942                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005439                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.005439                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.005439                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.005439                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.005439                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.005439                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14976.259406                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14976.259406                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14976.259406                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14976.259406                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14976.259406                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14976.259406                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks       790489                       # number of writebacks
system.cpu.icache.writebacks::total            790489                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       791008                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       791008                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       791008                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       791008                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       791008                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       791008                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11055333000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  11055333000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11055333000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  11055333000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11055333000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  11055333000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005439                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005439                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005439                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.005439                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005439                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.005439                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13976.259406                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13976.259406                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13976.259406                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13976.259406                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13976.259406                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13976.259406                       # average overall mshr miss latency
system.cpu.itb_walker_cache.tags.replacements         3383                       # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse     3.069456                       # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs         7971                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs         3396                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs     2.347173                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5168951189500                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.069456                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.191841                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total     0.191841                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           13                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.812500                       # Percentage of cache occupancy per task id
system.cpu.itb_walker_cache.tags.tag_accesses        28685                       # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses        28685                       # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7970                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total         7970                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7972                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total         7972                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7972                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total         7972                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4247                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total         4247                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4247                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total         4247                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4247                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total         4247                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     44856000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total     44856000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     44856000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total     44856000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     44856000                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total     44856000                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12217                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        12217                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12219                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        12219                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12219                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        12219                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.347630                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.347630                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.347573                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.347573                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.347573                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.347573                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10561.808335                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10561.808335                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10561.808335                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10561.808335                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10561.808335                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10561.808335                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.writebacks::writebacks          773                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total          773                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4247                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4247                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4247                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total         4247                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4247                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total         4247                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     40609000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     40609000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     40609000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     40609000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     40609000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     40609000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.347630                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.347630                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.347573                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.347573                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.347573                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.347573                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9561.808335                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9561.808335                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9561.808335                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9561.808335                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9561.808335                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9561.808335                       # average overall mshr miss latency
system.cpu.l2cache.tags.replacements            87287                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64590.438483                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4366272                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           151983                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            28.728687                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50117.131899                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     0.006347                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.146883                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  3409.599295                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11063.554060                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.764727                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.052026                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.168816                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.985572                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        64696                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          128                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2801                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5467                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56270                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987183                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         39228445                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        39228445                       # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks      1544529                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      1544529                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks       790476                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total       790476                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          320                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          320                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       200921                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       200921                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       778162                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total       778162                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker         6471                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker         2853                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1280522                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      1289846                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker         6471                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         2853                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       778162                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1481443                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2268929                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker         6471                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         2853                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       778162                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1481443                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2268929                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1406                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1406                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       113511                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       113511                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        12833                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        12833                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker            1                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker            5                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        28496                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        28502                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker            1                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        12833                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       142007                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        154846                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker            1                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        12833                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       142007                       # number of overall misses
system.cpu.l2cache.overall_misses::total       154846                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     52182500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     52182500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14440315000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  14440315000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1688067000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   1688067000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker       119000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker       637500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3748293500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   3749050000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker       119000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       637500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1688067000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  18188608500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  19877432000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker       119000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       637500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1688067000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  18188608500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  19877432000                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks      1544529                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      1544529                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks       790476                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total       790476                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1726                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1726                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       314432                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       314432                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       790995                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total       790995                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker         6472                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker         2858                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1309018                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      1318348                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6472                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         2858                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       790995                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1623450                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2423775                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker         6472                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         2858                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       790995                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1623450                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2423775                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.814600                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.814600                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.361003                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.361003                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.016224                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.016224                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker     0.000155                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker     0.001749                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.021769                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.021619                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000155                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001749                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016224                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.087472                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.063886                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000155                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001749                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016224                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.087472                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.063886                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 37114.153627                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 37114.153627                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127215.115716                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127215.115716                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131541.104964                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131541.104964                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker       119000                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker       127500                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 131537.531583                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 131536.383412                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker       119000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       127500                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131541.104964                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128082.478329                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 128369.037624                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker       119000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       127500                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131541.104964                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128082.478329                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 128369.037624                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks        80702                       # number of writebacks
system.cpu.l2cache.writebacks::total            80702                       # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1406                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1406                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       113511                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       113511                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        12833                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        12833                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker            1                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker            5                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        28496                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        28502                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        12833                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       142007                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       154846                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            1                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        12833                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       142007                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       154846                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data       546346                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total       546346                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        13920                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        13920                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data       560266                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total       560266                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     96565500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     96565500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  13305205000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  13305205000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1559737000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1559737000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker       109000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker       587500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   3463333500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   3464030000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker       109000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       587500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1559737000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  16768538500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  18328972000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker       109000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       587500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1559737000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  16768538500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  18328972000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  88302755000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  88302755000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  88302755000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  88302755000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.814600                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.814600                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.361003                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.361003                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.016224                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.016224                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker     0.000155                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker     0.001749                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.021769                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.021619                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000155                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.001749                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016224                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087472                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.063886                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000155                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.001749                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016224                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087472                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.063886                       # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68681.009957                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68681.009957                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117215.115716                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117215.115716                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121541.104964                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121541.104964                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker       109000                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker       117500                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 121537.531583                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 121536.383412                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker       109000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       117500                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121541.104964                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118082.478329                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118369.037624                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker       109000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       117500                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121541.104964                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118082.478329                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118369.037624                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161624.236290                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161624.236290                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 157608.626974                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157608.626974                       # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests      4855602                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2425060                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        11070                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         1020                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1020                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadReq         546346                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2660470                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         13920                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        13920                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      1671913                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean       790489                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict        97528                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2230                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2230                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       314438                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       314438                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq       791008                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      1323647                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::MessageReq         1654                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq        46720                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2372492                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5996122                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        10488                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        22844                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8401946                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    101214976                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    204098920                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       232384                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       605120                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          306151400                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      189316                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      3174772                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.004492                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.077876                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            3163038     99.63%     99.63% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1               9206      0.29%     99.92% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2               2528      0.08%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        3174772                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     5049912000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       571290                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1186512000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2990732492                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy       6370500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      13186500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq               216035                       # Transaction distribution
system.iobus.trans_dist::ReadResp              216035                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57726                       # Transaction distribution
system.iobus.trans_dist::WriteResp              57726                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1654                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1654                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11088                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       408166                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27824                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio         2308                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       452398                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3308                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3308                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  550830                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6686                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       204083                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13912                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio         4477                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       232479                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027280                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027280                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  3266375                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              4014316                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy             10060500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy              1094500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                79000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                50500                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy            306124500                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy              1113000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy              177500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy            24285000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy           241923874                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy             1216500                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           441392000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            50036000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1654000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47507                       # number of replacements
system.iocache.tags.tagsinuse                0.108260                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47523                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         5048330957000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.108260                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.006766                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.006766                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428058                       # Number of tag accesses
system.iocache.tags.data_accesses              428058                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          842                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              842                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47562                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47562                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47562                       # number of overall misses
system.iocache.overall_misses::total            47562                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    138525690                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    138525690                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   5867864184                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   5867864184                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide   6006389874                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   6006389874                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide   6006389874                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   6006389874                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          842                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            842                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47562                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47562                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47562                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47562                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 164519.821853                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 164519.821853                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125596.408048                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125596.408048                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 126285.477356                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 126285.477356                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 126285.477356                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 126285.477356                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           428                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   33                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    12.969697                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          842                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          842                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        46720                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        47562                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        47562                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        47562                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        47562                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     96425690                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     96425690                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3530059456                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   3530059456                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   3626485146                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   3626485146                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   3626485146                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   3626485146                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 114519.821853                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75557.779452                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75557.779452                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76247.532610                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76247.532610                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76247.532610                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76247.532610                       # average overall mshr miss latency
system.membus.trans_dist::ReadReq              546346                       # Transaction distribution
system.membus.trans_dist::ReadResp             588523                       # Transaction distribution
system.membus.trans_dist::WriteReq              13920                       # Transaction distribution
system.membus.trans_dist::WriteResp             13920                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       127369                       # Transaction distribution
system.membus.trans_dist::CleanEvict             7403                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2156                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              18                       # Transaction distribution
system.membus.trans_dist::ReadExReq            113265                       # Transaction distribution
system.membus.trans_dist::ReadExResp           113265                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         42177                       # Transaction distribution
system.membus.trans_dist::MessageReq             1654                       # Transaction distribution
system.membus.trans_dist::MessageResp            1654                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3308                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3308                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       452398                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       668134                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       397971                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1518503                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        95512                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        95512                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1617323                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6616                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total         6616                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       232479                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1336265                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15017728                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16586472                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3015040                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      3015040                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                19608128                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             1571                       # Total snoops (count)
system.membus.snoop_fanout::samples            901025                       # Request fanout histogram
system.membus.snoop_fanout::mean             1.001836                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.042806                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  899371     99.82%     99.82% # Request fanout histogram
system.membus.snoop_fanout::2                    1654      0.18%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
system.membus.snoop_fanout::total              901025                       # Request fanout histogram
system.membus.reqLayer0.occupancy           344310500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           503566000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             4013684                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy           852733442                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            2359684                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1924956500                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer4.occupancy            4280140                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.

---------- End Simulation Statistics   ----------