)]}'
{
  "commit": "94a00fb6d9270990cd04ae293556297a3c2f2563",
  "tree": "a31ca3cc465712e6b34fa67544657477394b7e33",
  "parents": [
    "7bd864c144efd374adc36fe327339a0171ab4a72"
  ],
  "author": {
    "name": "Daniel",
    "email": "odanrc@yahoo.com.br",
    "time": "Thu Mar 14 00:51:35 2019 +0100"
  },
  "committer": {
    "name": "Daniel Carvalho",
    "email": "odanrc@yahoo.com.br",
    "time": "Fri Mar 15 14:06:11 2019 +0000"
  },
  "message": "mem-cache: Fix write hit latency calculation order\n\nPatch 6d8694a5fb5cfb905186249581cc6a3fde6cc38a changes the order\nat which the access latency is calculated for hits. This order\nis incorrect, since the calculations must use the blk\u0027s whenReady\nvalue before the access is satisfied.\n\nChange-Id: I30dae5435f54200cc8fdf71fd0dbd2cf9c6f8b17\nSigned-off-by: Daniel \u003codanrc@yahoo.com.br\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17190\nReviewed-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "9f708b30dc71f05e26eafbc9688f2f6b7d9f2f6c",
      "old_mode": 33188,
      "old_path": "src/mem/cache/base.cc",
      "new_id": "50622d776bf4b5dfddf86915e768fcd972167577",
      "new_mode": 33188,
      "new_path": "src/mem/cache/base.cc"
    }
  ]
}