tree 973f9dad0038300ba7fd761c3ef2cbfb1e56bf67
parent a7eebbfa693e3fa55c0a9c876b97adcf72662c71
author Andrea Mondelli <Andrea.Mondelli@ucf.edu> 1550852950 -0500
committer Andrea Mondelli <Andrea.Mondelli@ucf.edu> 1551458807 +0000

mem-cache: alias to mem::getMasterPort in TLB class

TLB:getMasterPort is used to obtain the PageWalkMasterPort if present and
hides the BaseTLB::getMasterPort().

The TLB::getMasterPort() is renamed according to the expected behavior.

Change-Id: If4f61189094a706d59805cd10f4f814e5830eda8
Reviewed-on: https://gem5-review.googlesource.com/c/16648
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>