arch-arm: Use VecElem instead of FloatReg for FP instruction
SIMD & FP Operations use FloatRegs in AArch32 mode and VecRegs in
AArch64 mode. The usage of two different register pools breaks
interprocessing between A32 and A64. This patch is changing definition
of arm operands so that they are backed by VecElems in A32, which are
mapped to the same storage as A64 VecRegs.
Change-Id: I54e2ea0ef1ae61d29aca57ab09acb589d82c1217
Reviewed-on: https://gem5-review.googlesource.com/c/15603
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 3c231b9..dc54ec2 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -260,53 +260,71 @@
'FpCondCodes': ccReg('CCREG_FP'),
#Abstracted floating point reg operands
- 'FpDest': floatReg('(dest + 0)'),
- 'FpDestP0': floatReg('(dest + 0)'),
- 'FpDestP1': floatReg('(dest + 1)'),
- 'FpDestP2': floatReg('(dest + 2)'),
- 'FpDestP3': floatReg('(dest + 3)'),
- 'FpDestP4': floatReg('(dest + 4)'),
- 'FpDestP5': floatReg('(dest + 5)'),
- 'FpDestP6': floatReg('(dest + 6)'),
- 'FpDestP7': floatReg('(dest + 7)'),
- 'FpDestS0P0': floatReg('(dest + step * 0 + 0)'),
- 'FpDestS0P1': floatReg('(dest + step * 0 + 1)'),
- 'FpDestS1P0': floatReg('(dest + step * 1 + 0)'),
- 'FpDestS1P1': floatReg('(dest + step * 1 + 1)'),
- 'FpDestS2P0': floatReg('(dest + step * 2 + 0)'),
- 'FpDestS2P1': floatReg('(dest + step * 2 + 1)'),
- 'FpDestS3P0': floatReg('(dest + step * 3 + 0)'),
- 'FpDestS3P1': floatReg('(dest + step * 3 + 1)'),
+ 'FpDest': vectorElem('dest / 4', 'dest % 4'),
+ 'FpDestP0': vectorElem('dest / 4', '(dest % 4) + 0'),
+ 'FpDestP1': vectorElem('dest / 4', '(dest % 4) + 1'),
+ 'FpDestP2': vectorElem('dest / 4', '(dest % 4) + 2'),
+ 'FpDestP3': vectorElem('dest / 4', '(dest % 4) + 3'),
+ 'FpDestP4': vectorElem('(dest / 4) + 1', '(dest % 4) + 0'),
+ 'FpDestP5': vectorElem('(dest / 4) + 1', '(dest % 4) + 1'),
+ 'FpDestP6': vectorElem('(dest / 4) + 1', '(dest % 4) + 2'),
+ 'FpDestP7': vectorElem('(dest / 4) + 1', '(dest % 4) + 3'),
- 'FpDest2': floatReg('(dest2 + 0)'),
- 'FpDest2P0': floatReg('(dest2 + 0)'),
- 'FpDest2P1': floatReg('(dest2 + 1)'),
- 'FpDest2P2': floatReg('(dest2 + 2)'),
- 'FpDest2P3': floatReg('(dest2 + 3)'),
+ 'FpDestS0P0': vectorElem(
+ '(dest + step * 0 + 0) / 4', '(dest + step * 0 + 0) % 4'),
+ 'FpDestS0P1': vectorElem(
+ '(dest + step * 0 + 1) / 4', '(dest + step * 0 + 1) % 4'),
+ 'FpDestS1P0': vectorElem(
+ '(dest + step * 1 + 0) / 4', '(dest + step * 1 + 0) % 4'),
+ 'FpDestS1P1': vectorElem(
+ '(dest + step * 1 + 1) / 4', '(dest + step * 1 + 1) % 4'),
+ 'FpDestS2P0': vectorElem(
+ '(dest + step * 2 + 0) / 4', '(dest + step * 2 + 0) % 4'),
+ 'FpDestS2P1': vectorElem(
+ '(dest + step * 2 + 1) / 4', '(dest + step * 2 + 1) % 4'),
+ 'FpDestS3P0': vectorElem(
+ '(dest + step * 3 + 0) / 4', '(dest + step * 3 + 0) % 4'),
+ 'FpDestS3P1': vectorElem(
+ '(dest + step * 3 + 1) / 4', '(dest + step * 3 + 1) % 4'),
- 'FpOp1': floatReg('(op1 + 0)'),
- 'FpOp1P0': floatReg('(op1 + 0)'),
- 'FpOp1P1': floatReg('(op1 + 1)'),
- 'FpOp1P2': floatReg('(op1 + 2)'),
- 'FpOp1P3': floatReg('(op1 + 3)'),
- 'FpOp1P4': floatReg('(op1 + 4)'),
- 'FpOp1P5': floatReg('(op1 + 5)'),
- 'FpOp1P6': floatReg('(op1 + 6)'),
- 'FpOp1P7': floatReg('(op1 + 7)'),
- 'FpOp1S0P0': floatReg('(op1 + step * 0 + 0)'),
- 'FpOp1S0P1': floatReg('(op1 + step * 0 + 1)'),
- 'FpOp1S1P0': floatReg('(op1 + step * 1 + 0)'),
- 'FpOp1S1P1': floatReg('(op1 + step * 1 + 1)'),
- 'FpOp1S2P0': floatReg('(op1 + step * 2 + 0)'),
- 'FpOp1S2P1': floatReg('(op1 + step * 2 + 1)'),
- 'FpOp1S3P0': floatReg('(op1 + step * 3 + 0)'),
- 'FpOp1S3P1': floatReg('(op1 + step * 3 + 1)'),
+ 'FpDest2': vectorElem('dest2 / 4', 'dest2 % 4'),
+ 'FpDest2P0': vectorElem('dest2 / 4', '(dest2 % 4) + 0'),
+ 'FpDest2P1': vectorElem('dest2 / 4', '(dest2 % 4) + 1'),
+ 'FpDest2P2': vectorElem('dest2 / 4', '(dest2 % 4) + 2'),
+ 'FpDest2P3': vectorElem('dest2 / 4', '(dest2 % 4) + 3'),
- 'FpOp2': floatReg('(op2 + 0)'),
- 'FpOp2P0': floatReg('(op2 + 0)'),
- 'FpOp2P1': floatReg('(op2 + 1)'),
- 'FpOp2P2': floatReg('(op2 + 2)'),
- 'FpOp2P3': floatReg('(op2 + 3)'),
+ 'FpOp1': vectorElem('op1 / 4', 'op1 % 4'),
+ 'FpOp1P0': vectorElem('op1 / 4', '(op1 % 4) + 0'),
+ 'FpOp1P1': vectorElem('op1 / 4', '(op1 % 4) + 1'),
+ 'FpOp1P2': vectorElem('op1 / 4', '(op1 % 4) + 2'),
+ 'FpOp1P3': vectorElem('op1 / 4', '(op1 % 4) + 3'),
+ 'FpOp1P4': vectorElem('(op1 / 4) + 1', '(op1 % 4) + 0'),
+ 'FpOp1P5': vectorElem('(op1 / 4) + 1', '(op1 % 4) + 1'),
+ 'FpOp1P6': vectorElem('(op1 / 4) + 1', '(op1 % 4) + 2'),
+ 'FpOp1P7': vectorElem('(op1 / 4) + 1', '(op1 % 4) + 3'),
+
+ 'FpOp1S0P0': vectorElem(
+ '(op1 + step * 0 + 0) / 4', '(op1 + step * 0 + 0) % 4'),
+ 'FpOp1S0P1': vectorElem(
+ '(op1 + step * 0 + 1) / 4', '(op1 + step * 0 + 1) % 4'),
+ 'FpOp1S1P0': vectorElem(
+ '(op1 + step * 1 + 0) / 4', '(op1 + step * 1 + 0) % 4'),
+ 'FpOp1S1P1': vectorElem(
+ '(op1 + step * 1 + 1) / 4', '(op1 + step * 1 + 1) % 4'),
+ 'FpOp1S2P0': vectorElem(
+ '(op1 + step * 2 + 0) / 4', '(op1 + step * 2 + 0) % 4'),
+ 'FpOp1S2P1': vectorElem(
+ '(op1 + step * 2 + 1) / 4', '(op1 + step * 2 + 1) % 4'),
+ 'FpOp1S3P0': vectorElem(
+ '(op1 + step * 3 + 0) / 4', '(op1 + step * 3 + 0) % 4'),
+ 'FpOp1S3P1': vectorElem(
+ '(op1 + step * 3 + 1) / 4', '(op1 + step * 3 + 1) % 4'),
+
+ 'FpOp2': vectorElem('op2 / 4', 'op2 % 4'),
+ 'FpOp2P0': vectorElem('op2 / 4', '(op2 % 4) + 0'),
+ 'FpOp2P1': vectorElem('op2 / 4', '(op2 % 4) + 1'),
+ 'FpOp2P2': vectorElem('op2 / 4', '(op2 % 4) + 2'),
+ 'FpOp2P3': vectorElem('op2 / 4', '(op2 % 4) + 3'),
# Create AArch64 unpacked view of the FP registers
# Name ::= 'AA64Vec' OpSpec [LaneSpec]
@@ -548,7 +566,7 @@
'XURa' : intRegX64('ura'),
'WURa' : intRegW64('ura'),
'IWRa' : intRegIWPC('ura'),
- 'Fa' : floatReg('ura'),
+ 'Fa' : vectorElem('ura / 4', 'ura % 4'),
'URb' : intReg('urb'),
'XURb' : intRegX64('urb'),
'URc' : intReg('urc'),
