tree e0ffc84fd48058c6358b6b41aeb5cf7637148da8
parent d8dd86d4ce94e3e10d9369c0cb4287dd402a9401
author Giacomo Travaglini <giacomo.travaglini@arm.com> 1545038862 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> 1548420927 +0000

arch-arm: Use VecElem instead of FloatReg for FP instruction

SIMD & FP Operations use FloatRegs in AArch32 mode and VecRegs in
AArch64 mode. The usage of two different register pools breaks
interprocessing between A32 and A64.  This patch is changing definition
of arm operands so that they are backed by VecElems in A32, which are
mapped to the same storage as A64 VecRegs.

Change-Id: I54e2ea0ef1ae61d29aca57ab09acb589d82c1217
Reviewed-on: https://gem5-review.googlesource.com/c/15603
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>