tree ccb4137833e783b988a562fc1fdab8dc2c36154a
parent 6c00d57cce58973094e9cacd1bf3431a3407e866
author Daniel R. Carvalho <odanrc@yahoo.com.br> 1543926198 +0100
committer Daniel Carvalho <odanrc@yahoo.com.br> 1551964029 +0000

mem-cache: Use header delay on latency calculation

Previously the bus delay was being ignored for the access latency
calculation, and then applied on top of the access latency. This
patch fixes the order, as first the packet must arrive before the
access starts.

Change-Id: I6d55299a911d54625c147814dd423bfc63ef1b65
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14876
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>