mem-cache: Add lookup latency to access' whenReady
When dealing with writebacks, as soon as the packet metadata arrives
there will be a tag lookup, done sequentially because a write can't
be done in parallel. While the tag lookup is being done, the payload
will arrive. When both the payload are present and the tag is correct
block entry is determined the fill happens.
Change-Id: If1a0085d742458b675bfc012b6d908d9d9a25e32
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14877
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 2043770..7ba3065 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -1037,9 +1037,12 @@
pkt->writeDataToBlock(blk->data, blkSize);
DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
incHitCount(pkt);
- // populate the time when the block will be ready to access.
+
+ // When the packet metadata arrives, the tag lookup will be done while
+ // the payload is arriving. Then the block will be ready to access as
+ // soon as the fill is done
blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay +
- pkt->payloadDelay);
+ std::max(cyclesToTicks(tag_latency), (uint64_t)pkt->payloadDelay));
return true;
} else if (pkt->cmd == MemCmd::CleanEvict) {
if (blk) {
@@ -1094,9 +1097,13 @@
DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
incHitCount(pkt);
- // populate the time when the block will be ready to access.
+
+ // When the packet metadata arrives, the tag lookup will be done while
+ // the payload is arriving. Then the block will be ready to access as
+ // soon as the fill is done
blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay +
- pkt->payloadDelay);
+ std::max(cyclesToTicks(tag_latency), (uint64_t)pkt->payloadDelay));
+
// if this a write-through packet it will be sent to cache
// below
return !pkt->writeThrough();
