commit 9b6f0a97680a825d7ebfe13878fe10490f97c0be
author Giacomo Travaglini <giacomo.travaglini@arm.com> Fri Jan 11 13:32:20 2019 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Fri Jan 25 12:55:27 2019 +0000
tree 8d63af4aad07f78d3937c297300eee1e351c41b1
parent 96e72d6ecdf703f09d2788d02d5bedcf7b4b43f8

arch-arm: Remove floatReg operand type

Change-Id: I87553257ce9c42d0e2514d5a1f010bc6e2e7f21e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15604
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/arch/arm/isa/operands.isa

diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index dc54ec2..025f757 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -129,9 +129,6 @@
     def vectorRegElem(elem, ext = 'sf', zeroing = False):
         return (elem, ext, zeroing)
 
-    def floatReg(idx):
-        return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal)
-
     def intReg(idx):
         return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
                 maybePCRead, maybePCWrite)