commit a93fe3f3cf2b2ad7b0c5b9916bc705a579ca231c
author Javier Setoain <javier.setoain@arm.com> Thu Mar 14 17:42:44 2019 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Thu Mar 28 10:28:11 2019 +0000
tree 3b395f98c47f59dbad26bb0aaafe26ef07d7d55b
parent 93ad0d4324acd674f1877a1146c58412a03b4c39

arch-arm: Fix use of bitwise operators on booleans

Change-Id: I3762b2921f1d00a9104d8dc11a19dc0a219581e5
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17288
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/arch/arm/isa/insts/sve.isa

diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index b1b946f..647ceaf 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -3182,9 +3182,9 @@
     sveBinInst('bic', 'BicPred', 'SimdAluOp', unsignedTypes, bicCode,
                PredType.MERGE, True)
     # BIC (vectors, unpredicated)
-    bicCode = 'destElem = srcElem1 & ~srcElem2;'
     sveBinInst('bic', 'BicUnpred', 'SimdAluOp', unsignedTypes, bicCode)
     # BIC, BICS (predicates)
+    bicCode = 'destElem = srcElem1 && !srcElem2;'
     svePredLogicalInst('bic', 'PredBic', 'SimdPredAluOp', ('uint8_t',),
                        bicCode)
     svePredLogicalInst('bics', 'PredBics', 'SimdPredAluOp', ('uint8_t',),