diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index b1b946f..647ceaf 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -3182,9 +3182,9 @@
     sveBinInst('bic', 'BicPred', 'SimdAluOp', unsignedTypes, bicCode,
                PredType.MERGE, True)
     # BIC (vectors, unpredicated)
-    bicCode = 'destElem = srcElem1 & ~srcElem2;'
     sveBinInst('bic', 'BicUnpred', 'SimdAluOp', unsignedTypes, bicCode)
     # BIC, BICS (predicates)
+    bicCode = 'destElem = srcElem1 && !srcElem2;'
     svePredLogicalInst('bic', 'PredBic', 'SimdPredAluOp', ('uint8_t',),
                        bicCode)
     svePredLogicalInst('bics', 'PredBics', 'SimdPredAluOp', ('uint8_t',),