tree b850b77d7877a6133d1dc83edc2871edf517b46e
parent e7c8154479b3d0dbdc26cbb91fbccc2b9870e394
author Giacomo Travaglini <giacomo.travaglini@arm.com> 1546618849 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> 1548420689 +0000

cpu: Fix VecElemClass bugs in cpu models

This patch is:

* Adding a missing VecElemClass entry
* Fixing assertion in rename map which was checking the number of free
  vector registers rather than free vector element registers
* Fixing assertion in read/setVecElemOperand APIs.
* Using the right register index in SimpleThread
* Using VecElem instead of VecReg on O3 readArchVecElem

Change-Id: I265320dcbe35eb47075991301dfc99333c5190c4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15598
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>