tree af8551a75cc2c32c16ece1796344f59cdfc7e03a
parent a3be0a4cbc2665b91e1d83e25cfe709dd100ce5d
author Alec Roelke <alec.roelke@gmail.com> 1531493281 -0400
committer Alec Roelke <alec.roelke@gmail.com> 1547598034 +0000

arch-riscv: Add interrupt handling

Implement the Interrupts SimObject for RISC-V. This basically just
handles setting and getting the values of the interrupt-pending and
interrupt-enable CSRs according to the privileged ISA reference chapter
3.1.14. Note that it does NOT implement the PLIC as defined in chapter
7, as that is used for handling external interrupts which are defined
based on peripherals that are available.

Change-Id: Ia1321430f870ff5a3950217266fde0511332485b
Reviewed-on: https://gem5-review.googlesource.com/c/14377
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>