diff --git a/src/dev/net/Ethernet.py b/src/dev/net/Ethernet.py
index 6e900e0..0cf37e2 100644
--- a/src/dev/net/Ethernet.py
+++ b/src/dev/net/Ethernet.py
@@ -127,6 +127,7 @@
     type = 'EtherDevice'
     abstract = True
     cxx_header = "dev/net/etherdevice.hh"
+    cxx_extra_bases = [ "EtherObject" ]
     interface = MasterPort("Ethernet Interface")
 
 class IGbE(EtherDevice):
diff --git a/src/dev/net/etherdevice.hh b/src/dev/net/etherdevice.hh
index 3ce5495..7101ec8 100644
--- a/src/dev/net/etherdevice.hh
+++ b/src/dev/net/etherdevice.hh
@@ -37,6 +37,7 @@
 #define __DEV_NET_ETHERDEVICE_HH__
 
 #include "base/statistics.hh"
+#include "dev/net/etherobject.hh"
 #include "dev/pci/device.hh"
 #include "params/EtherDevBase.hh"
 #include "params/EtherDevice.hh"
@@ -44,11 +45,7 @@
 
 class EtherInt;
 
-/**
- * The base EtherObject class, allows for an accesor function to a
- * simobj that returns the Port.
- */
-class EtherDevice : public PciDevice
+class EtherDevice : public PciDevice, public EtherObject
 {
   public:
     typedef EtherDeviceParams Params;
@@ -63,10 +60,6 @@
     }
 
   public:
-    /** Additional function to return the Port of a memory object. */
-    virtual EtherInt *getEthPort(const std::string &if_name, int idx = -1) = 0;
-
-  public:
     void regStats();
 
   protected: