diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index aadef30..13d2ff0 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -779,9 +779,9 @@
 system.cpu0.iew.iewIQFullEvents                 24728                       # Number of times the IQ has become full, causing a stall
 system.cpu0.iew.iewLSQFullEvents               127466                       # Number of times the LSQ has become full, causing a stall
 system.cpu0.iew.memOrderViolationEvents         18891                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        275684                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedTakenIncorrect        275682                       # Number of branches that were predicted taken incorrectly
 system.cpu0.iew.predictedNotTakenIncorrect       374727                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              650411                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.branchMispredicts              650409                       # Number of branch mispredicts detected at execute
 system.cpu0.iew.iewExecutedInsts            126563046                       # Number of executed instructions
 system.cpu0.iew.iewExecLoadInsts             22955767                       # Number of load instructions executed
 system.cpu0.iew.iewExecSquashedInsts           966765                       # Number of squashed instructions skipped in execute
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
index 0d34de9..670631f 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
@@ -321,10 +321,10 @@
 system.physmem_0.readEnergy                 362653200                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                256666320                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy           178852415040                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            68967490005                       # Energy for active background per rank (pJ)
+system.physmem_0.actBackEnergy            68967548145                       # Energy for active background per rank (pJ)
 system.physmem_0.preBackEnergy           1611945575250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1860586561230                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              667.497599                       # Core power per rank (mW)
+system.physmem_0.totalEnergy             1860586619370                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.497600                       # Core power per rank (mW)
 system.physmem_0.memoryStateTime::IDLE   2632498894488                       # Time in different power states
 system.physmem_0.memoryStateTime::REF     91437840000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
index d64fdbe..f764698 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
@@ -1,135 +1,80 @@
 
 ---------- Begin Simulation Statistics ----------
-final_tick                               51111152682000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-host_inst_rate                                 904753                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 665260                       # Number of bytes of host memory used
-host_op_rate                                  1063233                       # Simulator op (including micro ops) rate (op/s)
-host_seconds                                  1088.22                       # Real time elapsed on the host
-host_tick_rate                            46967646801                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   984570519                       # Number of instructions simulated
-sim_ops                                    1157031967                       # Number of ops (including micro ops) simulated
 sim_seconds                                 51.111153                       # Number of seconds simulated
 sim_ticks                                51111152682000                       # Number of ticks simulated
-system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
-system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
+final_tick                               51111152682000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 929959                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1092854                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            48276126697                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 712572                       # Number of bytes of host memory used
+host_seconds                                  1058.73                       # Real time elapsed on the host
+sim_insts                                   984570519                       # Number of instructions simulated
+sim_ops                                    1157031967                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.cpu.Branches                         220088562                       # Number of branches fetched
-system.cpu.committedInsts                   984570519                       # Number of instructions committed
-system.cpu.committedOps                    1157031967                       # Number of ops (including micro ops) committed
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4564266                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      4564266                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      4310545                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      4310545                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.055589                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.055589                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       253721                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       253721                       # number of LoadLockedReq misses
-system.cpu.dcache.ReadReq_accesses::cpu.data    177577339                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    177577339                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits::cpu.data    171567259                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       171567259                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.033845                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.033845                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::cpu.data      6010080                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       6010080                       # number of ReadReq misses
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      2008417                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      2008417                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_hits::cpu.data       424020                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        424020                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.788879                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.788879                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1584397                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1584397                       # number of SoftPFReq misses
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      4562465                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      4562465                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::cpu.data      4562464                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      4562464                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1583058                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::total      1583058                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_hits::cpu.data       337709                       # number of WriteInvalidateReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::total       337709                       # number of WriteInvalidateReq hits
-system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data     0.786673                       # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.786673                       # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_misses::cpu.data      1245349                       # number of WriteInvalidateReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::total      1245349                       # number of WriteInvalidateReq misses
-system.cpu.dcache.WriteReq_accesses::cpu.data    162093127                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    162093127                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits::cpu.data    159522870                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      159522870                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015857                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.015857                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::cpu.data      2570257                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2570257                       # number of WriteReq misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::cpu.data    339670466                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    339670466                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_hits::cpu.data     331090129                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        331090129                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_rate::cpu.data     0.025261                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.025261                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::cpu.data      8580337                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        8580337                       # number of demand (read+write) misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses::cpu.data    341678883                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    341678883                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_hits::cpu.data    331514149                       # number of overall hits
-system.cpu.dcache.overall_hits::total       331514149                       # number of overall hits
-system.cpu.dcache.overall_miss_rate::cpu.data     0.029749                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.029749                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::cpu.data     10164734                       # number of overall misses
-system.cpu.dcache.overall_misses::total      10164734                       # number of overall misses
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          198                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
-system.cpu.dcache.tags.avg_refs             29.345233                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.data_accesses       1421167352                       # Number of data accesses
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.999719                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999999                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.replacements          11612141                       # number of replacements
-system.cpu.dcache.tags.sampled_refs          11612653                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.tag_accesses        1421167352                       # Number of tag accesses
-system.cpu.dcache.tags.tagsinuse           511.999719                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           340776008                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          33050500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks::writebacks      8921315                       # number of writebacks
-system.cpu.dcache.writebacks::total           8921315                       # number of writebacks
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.physmem.bytes_read::cpu.dtb.walker       412352                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       376512                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5562740                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          74833672                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        441792                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             81627068                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5562740                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5562740                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    103042944                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         103063524                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         6443                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         5883                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             127325                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1169289                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6903                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1315843                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1610046                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1612619                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           8068                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           7367                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               108836                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1464136                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8644                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1597050                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          108836                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             108836                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2016056                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                 403                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2016459                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2016056                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          8068                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          7367                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              108836                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1464539                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8644                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3613509                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu.inst           96                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst           96                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst           24                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst             2                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst            2                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
+system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
@@ -137,28 +82,35 @@
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
 system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
 system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.dtb.accesses                     352512518                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                    82353                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                    1139                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               49771                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                         352246803                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                          265715                       # DTB misses
-system.cpu.dtb.perms_faults                     21651                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                   9303                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                184208233                       # DTB read accesses
-system.cpu.dtb.read_hits                    184014035                       # DTB read hits
-system.cpu.dtb.read_misses                     194198                       # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                    265715                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                265715                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walkWaitTime::samples       265715                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0          265715    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       265715                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walksPending::samples     22846000                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0        22846000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total     22846000                       # Table walker pending requests distribution
 system.cpu.dtb.walker.walkPageSizes::4K        204282     89.47%     89.47% # Table walker page sizes translated
 system.cpu.dtb.walker.walkPageSizes::2M         24037     10.53%    100.00% # Table walker page sizes translated
 system.cpu.dtb.walker.walkPageSizes::total       228319                       # Table walker page sizes translated
@@ -169,85 +121,28 @@
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::total       228319                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin::total       494034                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkWaitTime::samples       265715                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0          265715    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       265715                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walks                    265715                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                265715                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksPending::samples     22846000                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0        22846000    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total     22846000                       # Table walker pending requests distribution
-system.cpu.dtb.write_accesses               168304285                       # DTB write accesses
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                    184014035                       # DTB read hits
+system.cpu.dtb.read_misses                     194198                       # DTB read misses
 system.cpu.dtb.write_hits                   168232768                       # DTB write hits
 system.cpu.dtb.write_misses                     71517                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::cpu.inst    985162020                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    985162020                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_hits::cpu.inst    970865862                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       970865862                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014511                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.014511                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::cpu.inst     14296158                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      14296158                       # number of ReadReq misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::cpu.inst    985162020                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    985162020                       # number of demand (read+write) accesses
-system.cpu.icache.demand_hits::cpu.inst     970865862                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        970865862                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_rate::cpu.inst     0.014511                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.014511                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::cpu.inst     14296158                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       14296158                       # number of demand (read+write) misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses::cpu.inst    985162020                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    985162020                       # number of overall (read+write) accesses
-system.cpu.icache.overall_hits::cpu.inst    970865862                       # number of overall hits
-system.cpu.icache.overall_hits::total       970865862                       # number of overall hits
-system.cpu.icache.overall_miss_rate::cpu.inst     0.014511                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.014511                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::cpu.inst     14296158                       # number of overall misses
-system.cpu.icache.overall_misses::total      14296158                       # number of overall misses
-system.cpu.icache.tags.age_task_id_blocks_1024::0          169                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          255                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           88                       # Occupied blocks per task id
-system.cpu.icache.tags.avg_refs             67.910987                       # Average number of references to valid blocks.
-system.cpu.icache.tags.data_accesses        999458178                       # Number of data accesses
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.984599                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999970                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999970                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.replacements          14295641                       # number of replacements
-system.cpu.icache.tags.sampled_refs          14296153                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.tag_accesses         999458178                       # Number of tag accesses
-system.cpu.icache.tags.tagsinuse           511.984599                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           970865862                       # Total number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle        6061930000                       # Cycle when the warmup percentage was hit.
-system.cpu.idle_fraction                     0.988675                       # Percentage of idle cycles
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid               49771                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                    1139                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                    82353                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   9303                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                     21651                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                184208233                       # DTB read accesses
+system.cpu.dtb.write_accesses               168304285                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                         352246803                       # DTB hits
+system.cpu.dtb.misses                          265715                       # DTB misses
+system.cpu.dtb.accesses                     352512518                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
@@ -255,28 +150,35 @@
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
 system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
 system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.itb.accesses                     985174158                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                    58174                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                    1139                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               49771                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                         985047321                       # DTB hits
-system.cpu.itb.inst_accesses                985174158                       # ITB inst accesses
-system.cpu.itb.inst_hits                    985047321                       # ITB inst hits
-system.cpu.itb.inst_misses                     126837                       # ITB inst misses
-system.cpu.itb.misses                          126837                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                    126837                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                126837                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walkWaitTime::samples       126837                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0          126837    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       126837                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walksPending::samples     22844500                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0        22844500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total     22844500                       # Table walker pending requests distribution
 system.cpu.itb.walker.walkPageSizes::4K        113576     99.02%     99.02% # Table walker page sizes translated
 system.cpu.itb.walker.walkPageSizes::2M          1123      0.98%    100.00% # Table walker page sizes translated
 system.cpu.itb.walker.walkPageSizes::total       114699                       # Table walker page sizes translated
@@ -287,174 +189,52 @@
 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       114699                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::total       114699                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin::total       241536                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkWaitTime::samples       126837                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0          126837    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       126837                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walks                    126837                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                126837                       # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksPending::samples     22844500                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0        22844500    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total     22844500                       # Table walker pending requests distribution
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_hits                    985047321                       # ITB inst hits
+system.cpu.itb.inst_misses                     126837                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16775                       # number of quiesce instructions executed
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      2519117                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      2519117                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1692610                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1692610                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.328094                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.328094                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       826507                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       826507                       # number of ReadExReq misses
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       513055                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       261506                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst     14296158                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      7848198                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total     22918917                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       506612                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       255623                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst     14211921                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      7504232                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total       22478388                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.012558                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.022497                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.005892                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.043827                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.019221                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         6443                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         5883                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        84237                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       343966                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       440529                       # number of ReadReq misses
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            1                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total            1                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total            1                       # number of SCUpgradeReq misses
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data        51140                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total        51140                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_hits::cpu.data        11223                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total        11223                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.780544                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.780544                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data        39917                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total        39917                       # number of UpgradeReq misses
-system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data      1245349                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.l2cache.WriteInvalidateReq_accesses::total      1245349                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data       694333                       # number of WriteInvalidateReq hits
-system.cpu.l2cache.WriteInvalidateReq_hits::total       694333                       # number of WriteInvalidateReq hits
-system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data     0.442459                       # miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.WriteInvalidateReq_miss_rate::total     0.442459                       # miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data       551016                       # number of WriteInvalidateReq misses
-system.cpu.l2cache.WriteInvalidateReq_misses::total       551016                       # number of WriteInvalidateReq misses
-system.cpu.l2cache.Writeback_accesses::writebacks      8921315                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      8921315                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits::writebacks      8921315                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      8921315                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker       513055                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker       261506                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst     14296158                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data     10367315                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total     25438034                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_hits::cpu.dtb.walker       506612                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       255623                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     14211921                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      9196842                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        24170998                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.012558                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.022497                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005892                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.112900                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.049809                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker         6443                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker         5883                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        84237                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1170473                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1267036                       # number of demand (read+write) misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker       513055                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker       261506                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst     14296158                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data     10367315                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     25438034                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_hits::cpu.dtb.walker       506612                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       255623                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     14211921                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      9196842                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       24170998                       # number of overall hits
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.012558                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.022497                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005892                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.112900                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.049809                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker         6443                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker         5883                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        84237                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1170473                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1267036                       # number of overall misses
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          278                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          588                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2715                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4911                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54669                       # Occupied blocks per task id
-system.cpu.l2cache.tags.avg_refs            16.788135                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.data_accesses       290307620                       # Number of data accesses
-system.cpu.l2cache.tags.occ_blocks::writebacks 37141.715219                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   310.196824                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   443.735041                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  6261.263092                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 21184.952326                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.566738                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004733                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006771                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.095539                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.323257                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.997038                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          278                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        63019                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004242                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.961594                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.replacements          1722692                       # number of replacements
-system.cpu.l2cache.tags.sampled_refs          1785989                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.tag_accesses        290307620                       # Number of tag accesses
-system.cpu.l2cache.tags.tagsinuse        65341.862502                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           29983424                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle        395986000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks::writebacks      1503415                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1503415                       # number of writebacks
-system.cpu.not_idle_fraction                 0.011325                       # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid               49771                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                    1139                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                    58174                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                985174158                       # ITB inst accesses
+system.cpu.itb.hits                         985047321                       # DTB hits
+system.cpu.itb.misses                          126837                       # DTB misses
+system.cpu.itb.accesses                     985174158                       # DTB accesses
 system.cpu.numCycles                     102222322140                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles               1157678536.479939                       # Number of busy cycles
-system.cpu.num_cc_register_reads            264407058                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes           263829403                       # number of times the CC registers were written
-system.cpu.num_conditional_control_insts    151940834                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                 880805                       # Number of float alu accesses
-system.cpu.num_fp_insts                        880805                       # number of float instructions
-system.cpu.num_fp_register_reads              1418999                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              747920                       # number of times the floating registers were written
-system.cpu.num_func_calls                    57056367                       # number of times a function call or return occured
-system.cpu.num_idle_cycles               101064643603.520065                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                   984570519                       # Number of instructions committed
+system.cpu.committedOps                    1157031967                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1060455466                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                 880805                       # Number of float alu accesses
+system.cpu.num_func_calls                    57056367                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    151940834                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                   1060455466                       # number of integer instructions
+system.cpu.num_fp_insts                        880805                       # number of float instructions
 system.cpu.num_int_register_reads          1564002170                       # number of times the integer registers were read
 system.cpu.num_int_register_writes          842444791                       # number of times the integer registers were written
-system.cpu.num_load_insts                   184180431                       # Number of load instructions
+system.cpu.num_fp_register_reads              1418999                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              747920                       # number of times the floating registers were written
+system.cpu.num_cc_register_reads            264407058                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes           263829403                       # number of times the CC registers were written
 system.cpu.num_mem_refs                     352465606                       # number of memory refs
+system.cpu.num_load_insts                   184180431                       # Number of load instructions
 system.cpu.num_store_insts                  168285175                       # Number of store instructions
+system.cpu.num_idle_cycles               101064643603.520065                       # Number of idle cycles
+system.cpu.num_busy_cycles               1157678536.479939                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.011325                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.988675                       # Percentage of idle cycles
+system.cpu.Branches                         220088562                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     1      0.00%      0.00% # Class of executed instruction
 system.cpu.op_class::IntAlu                 802636616     69.33%     69.33% # Class of executed instruction
 system.cpu.op_class::IntMult                  2354747      0.20%     69.54% # Class of executed instruction
@@ -490,6 +270,294 @@
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                 1157666593                       # Class of executed instruction
+system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
+system.cpu.kern.inst.quiesce                    16775                       # number of quiesce instructions executed
+system.cpu.dcache.tags.replacements          11612141                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.999719                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           340776008                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          11612653                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.345233                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          33050500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.999719                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999999                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          198                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1421167352                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1421167352                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    171567259                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       171567259                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    159522870                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      159522870                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       424020                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        424020                       # number of SoftPFReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::cpu.data       337709                       # number of WriteInvalidateReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::total       337709                       # number of WriteInvalidateReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      4310545                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      4310545                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      4562464                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      4562464                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     331090129                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        331090129                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    331514149                       # number of overall hits
+system.cpu.dcache.overall_hits::total       331514149                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      6010080                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       6010080                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2570257                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2570257                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1584397                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1584397                       # number of SoftPFReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::cpu.data      1245349                       # number of WriteInvalidateReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::total      1245349                       # number of WriteInvalidateReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       253721                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       253721                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      8580337                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        8580337                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     10164734                       # number of overall misses
+system.cpu.dcache.overall_misses::total      10164734                       # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data    177577339                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    177577339                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    162093127                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    162093127                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      2008417                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      2008417                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1583058                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::total      1583058                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4564266                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      4564266                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      4562465                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      4562465                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    339670466                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    339670466                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    341678883                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    341678883                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.033845                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.033845                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015857                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.015857                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.788879                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.788879                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data     0.786673                       # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.786673                       # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.055589                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.055589                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.025261                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.025261                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.029749                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.029749                       # miss rate for overall accesses
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks      8921315                       # number of writebacks
+system.cpu.dcache.writebacks::total           8921315                       # number of writebacks
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements          14295641                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.984599                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           970865862                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          14296153                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             67.910987                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle        6061930000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.984599                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999970                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999970                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          169                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          255                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           88                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         999458178                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        999458178                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    970865862                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       970865862                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     970865862                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        970865862                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    970865862                       # number of overall hits
+system.cpu.icache.overall_hits::total       970865862                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst     14296158                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total      14296158                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst     14296158                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total       14296158                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst     14296158                       # number of overall misses
+system.cpu.icache.overall_misses::total      14296158                       # number of overall misses
+system.cpu.icache.ReadReq_accesses::cpu.inst    985162020                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    985162020                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    985162020                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    985162020                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    985162020                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    985162020                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014511                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.014511                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.014511                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.014511                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.014511                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.014511                       # miss rate for overall accesses
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.tags.replacements          1722692                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65341.862502                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           29983424                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1785989                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            16.788135                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle        395986000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 37141.715219                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   310.196824                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   443.735041                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  6261.263092                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 21184.952326                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.566738                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004733                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006771                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.095539                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.323257                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.997038                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023          278                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        63019                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          278                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          588                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2715                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4911                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54669                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004242                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.961594                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        290307620                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       290307620                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       506612                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       255623                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst     14211921                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      7504232                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total       22478388                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      8921315                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      8921315                       # number of Writeback hits
+system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data       694333                       # number of WriteInvalidateReq hits
+system.cpu.l2cache.WriteInvalidateReq_hits::total       694333                       # number of WriteInvalidateReq hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data        11223                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total        11223                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1692610                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1692610                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker       506612                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker       255623                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst     14211921                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      9196842                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total        24170998                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker       506612                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker       255623                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst     14211921                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      9196842                       # number of overall hits
+system.cpu.l2cache.overall_hits::total       24170998                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         6443                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         5883                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst        84237                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       343966                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       440529                       # number of ReadReq misses
+system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data       551016                       # number of WriteInvalidateReq misses
+system.cpu.l2cache.WriteInvalidateReq_misses::total       551016                       # number of WriteInvalidateReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data        39917                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total        39917                       # number of UpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::total            1                       # number of SCUpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       826507                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       826507                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker         6443                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker         5883                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        84237                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1170473                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1267036                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker         6443                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker         5883                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst        84237                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1170473                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1267036                       # number of overall misses
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       513055                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       261506                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst     14296158                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      7848198                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total     22918917                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      8921315                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      8921315                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data      1245349                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.l2cache.WriteInvalidateReq_accesses::total      1245349                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data        51140                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total        51140                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            1                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total            1                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      2519117                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      2519117                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker       513055                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker       261506                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst     14296158                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data     10367315                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total     25438034                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker       513055                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker       261506                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst     14296158                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data     10367315                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total     25438034                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.012558                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.022497                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.005892                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.043827                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.019221                       # miss rate for ReadReq accesses
+system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data     0.442459                       # miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.WriteInvalidateReq_miss_rate::total     0.442459                       # miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.780544                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.780544                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.328094                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.328094                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.012558                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.022497                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005892                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.112900                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.049809                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.012558                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.022497                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005892                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.112900                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.049809                       # miss rate for overall accesses
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks      1503415                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1503415                       # number of writebacks
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq       23372119                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      23372119                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         33606                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        33606                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      8921315                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1245349                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1245349                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        51140                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp        51141                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2519117                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2519117                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     28678566                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     32383245                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       758224                       # Packet count per connected master and slave (bytes)
@@ -500,6 +568,7 @@
 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      3032896                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6175776                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total         2238699610                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      116338                       # Total snoops (count)
 system.cpu.toL2Bus.snoop_fanout::samples     36147883                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        3.003196                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.056441                       # Request fanout histogram
@@ -513,20 +582,11 @@
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::total       36147883                       # Request fanout histogram
-system.cpu.toL2Bus.snoops                      116338                       # Total snoops (count)
-system.cpu.toL2Bus.trans_dist::ReadReq       23372119                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      23372119                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         33606                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        33606                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      8921315                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1245349                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1245349                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        51140                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        51141                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      2519117                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      2519117                       # Transaction distribution
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.iobus.trans_dist::ReadReq                40246                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40246                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136515                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              29851                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47598                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
@@ -569,77 +629,84 @@
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  7491976                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.trans_dist::ReadReq                40246                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40246                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136515                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              29851                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
-system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8817                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8854                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8817                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8854                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
-system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8817                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8857                       # number of demand (read+write) accesses
-system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8817                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8857                       # number of demand (read+write) misses
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8817                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8857                       # number of overall (read+write) accesses
-system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8817                       # number of overall misses
-system.iocache.overall_misses::total             8857                       # number of overall misses
-system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
+system.iocache.tags.replacements               115463                       # number of replacements
+system.iocache.tags.tagsinuse               10.407109                       # Cycle average of tags in use
+system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs               115479                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.data_accesses             1039686                       # Number of data accesses
+system.iocache.tags.warmup_cycle         13082113302009                       # Cycle when the warmup percentage was hit.
 system.iocache.tags.occ_blocks::realview.ethernet     3.554599                       # Average occupied blocks per requestor
 system.iocache.tags.occ_blocks::realview.ide     6.852510                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::realview.ethernet     0.222162                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::realview.ide     0.428282                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.650444                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.replacements               115463                       # number of replacements
-system.iocache.tags.sampled_refs               115479                       # Sample count of references to valid blocks.
 system.iocache.tags.tag_accesses              1039686                       # Number of tag accesses
-system.iocache.tags.tagsinuse               10.407109                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13082113302009                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.data_accesses             1039686                       # Number of data accesses
+system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8817                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8854                       # number of ReadReq misses
+system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
+system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
+system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8817                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8857                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
+system.iocache.overall_misses::realview.ide         8817                       # number of overall misses
+system.iocache.overall_misses::total             8857                       # number of overall misses
+system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8817                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8854                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8817                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8857                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8817                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8857                       # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq              526062                       # Transaction distribution
+system.membus.trans_dist::ReadResp             526062                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33606                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33606                       # Transaction distribution
+system.membus.trans_dist::Writeback           1610046                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq       657675                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp       657675                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            40484                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           40485                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            825948                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           825948                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122480                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6654                       # Packet count per connected master and slave (bytes)
@@ -656,6 +723,7 @@
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14217536                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total     14217536                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total               227117498                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoop_fanout::samples           3583537                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
@@ -667,115 +735,47 @@
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::total             3583537                       # Request fanout histogram
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.trans_dist::ReadReq              526062                       # Transaction distribution
-system.membus.trans_dist::ReadResp             526062                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33606                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33606                       # Transaction distribution
-system.membus.trans_dist::Writeback           1610046                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       657675                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       657675                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            40484                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           40485                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            825948                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           825948                       # Transaction distribution
-system.physmem.bw_inst_read::cpu.inst          108836                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             108836                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker           8068                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           7367                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               108836                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1464136                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8644                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1597050                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2016056                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          8068                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          7367                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              108836                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1464539                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8644                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3613509                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2016056                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data                 403                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2016459                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bytes_inst_read::cpu.inst      5562740                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5562740                       # Number of instructions bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker       412352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       376512                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5562740                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          74833672                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        441792                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             81627068                       # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks    103042944                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         103063524                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         6443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         5883                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             127325                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1169289                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6903                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1315843                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1610046                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1612619                       # Number of write requests responded to by this memory
-system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
-system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
-system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
-system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
-system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
-system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
+system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
+system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
-system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
-system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
 system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets                 3                       # Total Packets
 system.realview.ethernet.totBytes                 966                       # Total Bytes
 system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.totPackets                 3                       # Total Packets
-system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
-system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
-system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
-system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
 system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
-system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
 system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
-system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
-system.realview.nvmem.bw_inst_read::cpu.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu.inst             2                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst            2                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bytes_inst_read::cpu.inst           96                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_read::cpu.inst           96                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst           24                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
-system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
+system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index ba05761..63f3817 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
@@ -1,134 +1,134 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.154240                       # Number of seconds simulated
-sim_ticks                                5154239928000                       # Number of ticks simulated
-final_tick                               5154239928000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.162227                       # Number of seconds simulated
+sim_ticks                                5162226977000                       # Number of ticks simulated
+final_tick                               5162226977000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 177928                       # Simulator instruction rate (inst/s)
-host_op_rate                                   351699                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2247974259                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 809460                       # Number of bytes of host memory used
-host_seconds                                  2292.84                       # Real time elapsed on the host
-sim_insts                                   407959851                       # Number of instructions simulated
-sim_ops                                     806389826                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 127909                       # Simulator instruction rate (inst/s)
+host_op_rate                                   252832                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1618521974                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 804704                       # Number of bytes of host memory used
+host_seconds                                  3189.47                       # Real time elapsed on the host
+sim_insts                                   407963408                       # Number of instructions simulated
+sim_ops                                     806401326                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker         4224                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1048832                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10760128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         4608                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1045376                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10748480                       # Number of bytes read from this memory
 system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11841856                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1048832                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1048832                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9579968                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9579968                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker           66                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              16388                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             168127                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             11827200                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1045376                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1045376                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9574464                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9574464                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker           72                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              16334                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             167945                       # Number of read requests responded to by this memory
 system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                185029                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          149687                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               149687                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker            820                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               203489                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2087627                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide         5501                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2297498                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          203489                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             203489                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1858658                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1858658                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1858658                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           820                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              203489                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2087627                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide         5501                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4156156                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        185029                       # Number of read requests accepted
-system.physmem.writeReqs                       196407                       # Number of write requests accepted
-system.physmem.readBursts                      185029                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     196407                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11835328                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6528                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  10911872                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  11841856                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               12570048                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      102                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   25884                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           1735                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11576                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               11057                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               12153                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11198                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               11802                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               11348                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11143                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11153                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               11425                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               11213                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11332                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11504                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11762                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              12902                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              11974                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11385                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               11439                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               10429                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               10485                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9453                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               11713                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               11103                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               10277                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               10587                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               10639                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               10347                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              10880                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              10311                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              10712                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              11096                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              11110                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               9917                       # Per bank write bursts
+system.physmem.num_reads::total                184800                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          149601                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               149601                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker            893                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             74                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               202505                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2082140                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide         5492                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2291104                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          202505                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             202505                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1854716                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1854716                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1854716                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           893                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            74                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              202505                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2082140                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide         5492                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4145820                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        184800                       # Number of read requests accepted
+system.physmem.writeReqs                       196321                       # Number of write requests accepted
+system.physmem.readBursts                      184800                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     196321                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11821504                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      5696                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  10906560                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11827200                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               12564544                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       89                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                   25886                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           1718                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11628                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11143                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               12156                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11292                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               11683                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11167                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11068                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10875                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               11368                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               11325                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11465                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              11570                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11698                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12742                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              12203                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11328                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               11574                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               10551                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               10459                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9588                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               11508                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               10703                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               10513                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               10063                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               10551                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               10425                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              10702                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              10392                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              10604                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              11331                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              11278                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              10173                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          48                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5154239876000                       # Total gap between requests
+system.physmem.numWrRetry                          60                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5162226925000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  185029                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  184800                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 196407                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    170541                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     11600                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      1966                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       474                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 196321                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    170378                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     11550                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      1970                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       479                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                        56                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        41                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                        32                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        35                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                        30                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        37                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                        31                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        33                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                        33                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       25                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       26                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       26                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       25                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       24                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        7                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -156,300 +156,300 @@
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1636                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1926                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6237                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6870                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7339                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7830                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8415                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7894                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8094                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9954                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8496                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7725                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10840                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8567                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     8107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7987                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1631                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1321                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1459                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     2521                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     2967                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     2476                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     2901                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     3411                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     2551                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     2324                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     2194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     2613                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     2036                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1543                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1490                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     1243                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      899                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      438                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      382                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      298                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      219                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      192                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      174                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       57                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        73580                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      309.148356                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     181.632665                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     329.613307                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          27722     37.68%     37.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        17426     23.68%     61.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         7585     10.31%     71.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         4195      5.70%     77.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2982      4.05%     81.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2040      2.77%     84.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1416      1.92%     86.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1303      1.77%     87.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8911     12.11%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          73580                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6767                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.326437                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      584.974446                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6766     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1624                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1802                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6246                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6888                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     7036                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     7195                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7316                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7796                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8975                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7810                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9821                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8198                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7690                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    10574                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8617                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     8151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7972                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1675                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1396                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     1658                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     2900                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     2748                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     2598                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     2515                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     3090                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     2622                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     2336                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     2429                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     2344                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                     1866                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                     1717                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                     1639                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                     1214                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      790                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      410                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      379                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      268                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      332                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      225                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      252                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      281                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      193                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      106                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       75                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       81                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        73421                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      309.557211                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     181.985828                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     329.854749                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          27502     37.46%     37.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17545     23.90%     61.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         7551     10.28%     71.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         4202      5.72%     77.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2967      4.04%     81.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2030      2.76%     84.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1382      1.88%     86.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1321      1.80%     87.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8921     12.15%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          73421                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6763                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.310069                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      585.144514                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6762     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6767                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6767                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        25.195508                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.700984                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       42.210035                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31            6335     93.62%     93.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47              84      1.24%     94.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63              17      0.25%     95.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79              17      0.25%     95.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95              19      0.28%     95.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111             20      0.30%     95.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127            33      0.49%     96.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143            32      0.47%     96.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            26      0.38%     97.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175             8      0.12%     97.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191            61      0.90%     98.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            50      0.74%     99.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223            12      0.18%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239             1      0.01%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255             2      0.03%     99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287             3      0.04%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             2      0.03%     99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             2      0.03%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335             4      0.06%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351             9      0.13%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367            14      0.21%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383             6      0.09%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399             1      0.01%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415             1      0.01%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             2      0.03%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543             1      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559             3      0.04%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575             2      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6767                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2002245948                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5469627198                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    924635000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10827.22                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6763                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6763                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        25.198137                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.714181                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       42.096027                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-31            6327     93.55%     93.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-47              89      1.32%     94.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-63              13      0.19%     95.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-79              16      0.24%     95.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-95              24      0.35%     95.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-111             14      0.21%     95.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-127            33      0.49%     96.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-143            33      0.49%     96.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-159            38      0.56%     97.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-175            13      0.19%     97.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-191            44      0.65%     98.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-207            51      0.75%     98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-223            15      0.22%     99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-239             4      0.06%     99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-255             1      0.01%     99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-287             4      0.06%     99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-303             2      0.03%     99.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319             1      0.01%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-335             1      0.01%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-351             5      0.07%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-367            22      0.33%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::368-383             4      0.06%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::384-399             2      0.03%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::480-495             1      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527             1      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::544-559             1      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::560-575             3      0.04%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::656-671             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6763                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2002108102                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5465439352                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    923555000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10839.14                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29577.22                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.30                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.12                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.30                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.44                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29589.14                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.29                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.11                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.29                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.43                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.30                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     151945                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    129899                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.16                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  76.18                       # Row buffer hit rate for writes
-system.physmem.avgGap                     13512725.27                       # Average gap between requests
-system.physmem.pageHitRate                      79.29                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  271547640                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  148165875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 713146200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                553949280                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           336649428960                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           130302295830                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           2978239548750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             3446878082535                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.747042                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   4954509635136                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    172111160000                       # Time in different power states
+system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.03                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     151806                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    129898                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.19                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  76.22                       # Row buffer hit rate for writes
+system.physmem.avgGap                     13544850.39                       # Average gap between requests
+system.physmem.pageHitRate                      79.32                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  269075520                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  146817000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 709885800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                550534320                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           337171211520                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           130425108030                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           2982925034250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             3452197666440                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.742620                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   4962301533714                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    172377920000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     27619022864                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     27547412786                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  284717160                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  155351625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 729276600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                550877760                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           336649428960                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           130834885590                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           2977772364750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             3446976902445                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.766215                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   4953723422640                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    172111160000                       # Time in different power states
+system.physmem_1.actEnergy                  285987240                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  156044625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 730852200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                553754880                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           337171211520                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           131048206380                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           2982378456750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             3452324513595                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.767192                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   4961386282222                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    172377920000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     28398444860                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     28457517778                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                86886659                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          86886659                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            896606                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             80012064                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                78173158                       # Number of BTB hits
+system.cpu.branchPred.lookups                86892140                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          86892140                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            896476                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             79993842                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                78175387                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.701714                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1555790                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             180979                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             97.726756                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1559595                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             180975                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                        452015949                       # number of cpu cycles simulated
+system.cpu.numCycles                        451961239                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           27708415                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      429123541                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    86886659                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           79728948                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     420284778                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1879978                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     144708                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                58405                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        207121                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles           57                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          651                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   9181144                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                450119                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    5089                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          449344124                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.884391                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.047300                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           27669643                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      429138859                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    86892140                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           79734982                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     420292054                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1880326                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     139799                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                59635                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        206134                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles           79                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          545                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   9182224                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                451305                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    4827                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          449308052                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.884669                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.047434                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                283935319     63.19%     63.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2153229      0.48%     63.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 72170843     16.06%     79.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1584001      0.35%     80.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2141625      0.48%     80.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  2336888      0.52%     81.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1524270      0.34%     81.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1887238      0.42%     81.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 81610711     18.16%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                283889001     63.18%     63.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2152335      0.48%     63.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 72174656     16.06%     79.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1583547      0.35%     80.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2143406      0.48%     80.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  2336945      0.52%     81.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1526578      0.34%     81.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1885904      0.42%     81.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 81615680     18.16%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            449344124                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.192220                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.949355                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 23005123                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             267198709                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 150742142                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               7458161                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 939989                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              838443104                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                 939989                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 25847202                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               224345308                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       13466568                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 154654216                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              30090841                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              834933758                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                459142                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               12335285                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 199811                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               14823013                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           997303578                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1813575837                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1114848675                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               334                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             964352232                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 32951344                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             467055                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         470880                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  38821668                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             17323479                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            10180206                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1295686                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1069829                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  829469634                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1196558                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 824230120                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            243416                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        23349289                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     36028466                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         151024                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     449344124                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.834296                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.415438                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            449308052                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.192256                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.949504                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 22960534                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             267201307                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 150748201                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               7457847                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 940163                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              838480362                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                 940163                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 25806835                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               224389855                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       13453779                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 154655676                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              30061744                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              834963010                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                457566                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               12341140                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 186586                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               14798192                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           997326822                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1813638756                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1114908706                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               291                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             964358255                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 32968562                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             467477                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         471287                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  38845539                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             17334604                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            10181445                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1298649                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1067040                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  829488885                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1196680                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 824229235                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            243657                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        23357015                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     36101946                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         150898                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     449308052                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.834441                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.415481                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           265024726     58.98%     58.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            14037592      3.12%     62.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             9914300      2.21%     64.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7059540      1.57%     65.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            74309398     16.54%     82.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4399488      0.98%     83.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            72817937     16.21%     99.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1206490      0.27%     99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              574653      0.13%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           264987396     58.98%     58.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            14037441      3.12%     62.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             9917964      2.21%     64.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7059297      1.57%     65.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            74310664     16.54%     82.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4394298      0.98%     83.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            72818105     16.21%     99.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1207897      0.27%     99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              574990      0.13%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       449344124                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       449308052                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 1987162     71.98%     71.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                    137      0.00%     71.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                     645      0.02%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     72.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 611861     22.16%     94.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                160804      5.82%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 1986642     71.94%     71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                    137      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                     673      0.02%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 612859     22.19%     94.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                161094      5.83%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            290308      0.04%      0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             795868269     96.56%     96.59% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               150766      0.02%     96.61% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                125160      0.02%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass            292031      0.04%      0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             795863777     96.56%     96.59% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               150844      0.02%     96.61% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                125129      0.02%     96.63% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.63% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                  92      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                  78      0.00%     96.63% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.63% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.63% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.63% # Type of FU issued
@@ -473,98 +473,98 @@
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.63% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.63% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             18401922      2.23%     98.86% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             9393603      1.14%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             18406058      2.23%     98.86% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             9391318      1.14%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              824230120                       # Type of FU issued
-system.cpu.iq.rate                           1.823454                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2760609                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.003349                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2100807897                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         854027763                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    819692227                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 491                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                488                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          172                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              826700185                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     236                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1868049                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              824229235                       # Type of FU issued
+system.cpu.iq.rate                           1.823672                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2761405                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.003350                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2100771128                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         854054980                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    819688520                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 455                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                442                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          164                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              826698389                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     220                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1868749                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      3330814                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14803                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        14207                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1754572                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      3338025                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        14795                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        14329                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1756067                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2207477                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         74768                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2207525                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         74436                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 939989                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles               205903045                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles              10169335                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           830666192                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            152285                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              17323479                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             10180206                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             703380                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 416558                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               8857895                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          14207                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         510302                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       537060                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1047362                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             822616274                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              18004247                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1478799                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 940163                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               205965159                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles              10145461                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           830685565                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            152778                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              17334627                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             10181445                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             703446                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 417328                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               8832506                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          14329                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         509833                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       537197                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1047030                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             822615157                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              18006824                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1479252                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     27174393                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 83301836                       # Number of branches executed
-system.cpu.iew.exec_stores                    9170146                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.819883                       # Inst execution rate
-system.cpu.iew.wb_sent                      822114086                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     819692399                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 640992347                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1050518142                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     27175476                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 83299971                       # Number of branches executed
+system.cpu.iew.exec_stores                    9168652                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.820101                       # Inst execution rate
+system.cpu.iew.wb_sent                      822110525                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     819688684                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 640992243                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1050515204                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.813415                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.610168                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.813626                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.610169                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        24149765                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1045534                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            907960                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    445713409                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.809212                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.671420                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        24158442                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1045781                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            908032                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    445675381                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.809392                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.671516                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    274913705     61.68%     61.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     11179565      2.51%     64.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3571950      0.80%     64.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     74564778     16.73%     81.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      2421074      0.54%     82.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1628213      0.37%     82.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       937027      0.21%     82.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     71052272     15.94%     98.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5444825      1.22%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    274876482     61.68%     61.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     11176587      2.51%     64.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3572419      0.80%     64.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     74567842     16.73%     81.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2417950      0.54%     82.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1626837      0.37%     82.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       937685      0.21%     82.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     71052352     15.94%     98.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5447227      1.22%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    445713409                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            407959851                       # Number of instructions committed
-system.cpu.commit.committedOps              806389826                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    445675381                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            407963408                       # Number of instructions committed
+system.cpu.commit.committedOps              806401326                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       22418298                       # Number of memory references committed
-system.cpu.commit.loads                      13992664                       # Number of loads committed
-system.cpu.commit.membars                      471797                       # Number of memory barriers committed
-system.cpu.commit.branches                   82198639                       # Number of branches committed
+system.cpu.commit.refs                       22421978                       # Number of memory references committed
+system.cpu.commit.loads                      13996600                       # Number of loads committed
+system.cpu.commit.membars                      471855                       # Number of memory barriers committed
+system.cpu.commit.branches                   82197677                       # Number of branches committed
 system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 735203522                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              1155963                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass       171777      0.02%      0.02% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        783535872     97.17%     97.19% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          144976      0.02%     97.21% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv           121468      0.02%     97.22% # Class of committed instruction
+system.cpu.commit.int_insts                 735212771                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1156131                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass       171861      0.02%      0.02% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        783543527     97.17%     97.19% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          145013      0.02%     97.20% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv           121508      0.02%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt             16      0.00%     97.22% # Class of committed instruction
@@ -591,166 +591,166 @@
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        13990083      1.73%     98.96% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite        8425634      1.04%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        13994023      1.74%     98.96% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        8425378      1.04%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         806389826                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               5444825                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1270729806                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1664729387                       # The number of ROB writes
-system.cpu.timesIdled                          294275                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         2671825                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   9856461520                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   407959851                       # Number of Instructions Simulated
-system.cpu.committedOps                     806389826                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.107991                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.107991                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.902534                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.902534                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1092541258                       # number of integer regfile reads
-system.cpu.int_regfile_writes               656084038                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       176                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                 416293281                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                322054452                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               265591845                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 400328                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           1659836                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.989699                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            19130413                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1660348                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             11.521930                       # Average number of references to valid blocks.
+system.cpu.commit.op_class_0::total         806401326                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               5447227                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1270709490                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1664771633                       # The number of ROB writes
+system.cpu.timesIdled                          294088                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         2653187                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   9872490334                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   407963408                       # Number of Instructions Simulated
+system.cpu.committedOps                     806401326                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.107847                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.107847                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.902651                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.902651                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1092540236                       # number of integer regfile reads
+system.cpu.int_regfile_writes               656081112                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       164                       # number of floating regfile reads
+system.cpu.cc_regfile_reads                 416269777                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                322038455                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               265590229                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 400570                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           1660860                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.966923                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            19133185                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1661372                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             11.516497                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          41264250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.989699                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999980                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999980                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.966923                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999935                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999935                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          306                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          197                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          297                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          88364873                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         88364873                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     10981747                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        10981747                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8081553                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8081553                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        64328                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         64328                       # number of SoftPFReq hits
-system.cpu.dcache.demand_hits::cpu.data      19063300                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         19063300                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     19127628                       # number of overall hits
-system.cpu.dcache.overall_hits::total        19127628                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1807734                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1807734                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       334390                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       334390                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       406367                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       406367                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      2142124                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2142124                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2548491                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2548491                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  27237843437                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  27237843437                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  13894605384                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  13894605384                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  41132448821                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  41132448821                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  41132448821                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  41132448821                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     12789481                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     12789481                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8415943                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8415943                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       470695                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       470695                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21205424                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21205424                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21676119                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21676119                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.141345                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.141345                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039733                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.039733                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.863334                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.863334                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.101018                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.101018                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.117571                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.117571                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15067.395666                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15067.395666                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41552.096008                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 41552.096008                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 19201.712329                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 19201.712329                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16139.923124                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16139.923124                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       413510                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            7                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             44186                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.358394                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets            7                       # average number of cycles each access was blocked
+system.cpu.dcache.tags.tag_accesses          88373649                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         88373649                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     10984709                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        10984709                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8081292                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8081292                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        64363                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         64363                       # number of SoftPFReq hits
+system.cpu.dcache.demand_hits::cpu.data      19066001                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         19066001                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     19130364                       # number of overall hits
+system.cpu.dcache.overall_hits::total        19130364                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1806694                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1806694                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       334372                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       334372                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       406627                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       406627                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      2141066                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2141066                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2547693                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2547693                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  27203829960                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  27203829960                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  13876174615                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  13876174615                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  41080004575                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  41080004575                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  41080004575                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  41080004575                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     12791403                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     12791403                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8415664                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8415664                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       470990                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       470990                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21207067                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21207067                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21678057                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21678057                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.141243                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.141243                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039732                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.039732                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.863345                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.863345                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.100960                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.100960                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.117524                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.117524                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15057.242654                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15057.242654                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41499.212299                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 41499.212299                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 19186.706330                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 19186.706330                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16124.393549                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 16124.393549                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       418738                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             44180                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.477999                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1561658                       # number of writebacks
-system.cpu.dcache.writebacks::total           1561658                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       837908                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       837908                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44444                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        44444                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       882352                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       882352                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       882352                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       882352                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       969826                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       969826                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289946                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       289946                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402900                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       402900                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1259772                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1259772                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1662672                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1662672                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12862571524                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  12862571524                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12285238213                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  12285238213                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   5938147500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   5938147500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25147809737                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  25147809737                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31085957237                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  31085957237                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97453049000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97453049000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2592894500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2592894500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100045943500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 100045943500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075830                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075830                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034452                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034452                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.855968                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.855968                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059408                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.059408                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076705                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.076705                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13262.762108                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13262.762108                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42370.780121                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42370.780121                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14738.514520                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14738.514520                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19962.191362                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 19962.191362                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18696.385840                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 18696.385840                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      1562601                       # number of writebacks
+system.cpu.dcache.writebacks::total           1562601                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       836073                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       836073                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44459                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        44459                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       880532                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       880532                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       880532                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       880532                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       970621                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       970621                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289913                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       289913                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       403165                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       403165                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1260534                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1260534                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1663699                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1663699                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12878267529                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  12878267529                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12265177974                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  12265177974                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   5946557500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   5946557500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25143445503                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  25143445503                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31090003003                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  31090003003                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97454738500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97454738500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2595624500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2595624500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100050363000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 100050363000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075881                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075881                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034449                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034449                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.855995                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.855995                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059439                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.059439                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076746                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.076746                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13268.070162                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13268.070162                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42306.409074                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42306.409074                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14749.686853                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14749.686853                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19946.661893                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 19946.661893                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18687.276366                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 18687.276366                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -758,58 +758,57 @@
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements        73822                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse    15.784353                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs       116295                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs        73836                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.575045                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.replacements        73201                       # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse    15.783499                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs       115173                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs        73217                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs     1.573036                       # Average number of references to valid blocks.
 system.cpu.dtb_walker_cache.tags.warmup_cycle 194860088500                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.784353                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.986522                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total     0.986522                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses       457427                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses       457427                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       116311                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total       116311                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       116311                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total       116311                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       116311                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total       116311                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        74935                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total        74935                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        74935                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total        74935                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        74935                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total        74935                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    914897711                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    914897711                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    914897711                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total    914897711                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    914897711                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total    914897711                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       191246                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total       191246                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       191246                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total       191246                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       191246                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total       191246                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.391825                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.391825                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.391825                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.391825                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.391825                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.391825                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12209.217468                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12209.217468                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12209.217468                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12209.217468                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12209.217468                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12209.217468                       # average overall miss latency
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.783499                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.986469                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_percent::total     0.986469                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           16                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0           10                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dtb_walker_cache.tags.tag_accesses       453261                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses       453261                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       115173                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total       115173                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       115173                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total       115173                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       115173                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total       115173                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        74305                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total        74305                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        74305                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total        74305                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        74305                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total        74305                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    909823965                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    909823965                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    909823965                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total    909823965                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    909823965                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total    909823965                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       189478                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total       189478                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       189478                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total       189478                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       189478                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total       189478                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.392156                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.392156                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.392156                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.392156                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.392156                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.392156                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12244.451450                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12244.451450                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12244.451450                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12244.451450                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12244.451450                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12244.451450                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -818,180 +817,181 @@
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks        20337                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total        20337                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        74935                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        74935                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        74935                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total        74935                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        74935                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total        74935                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    802357975                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    802357975                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    802357975                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    802357975                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    802357975                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    802357975                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.391825                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.391825                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.391825                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.391825                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.391825                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.391825                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10707.386068                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10707.386068                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10707.386068                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks        20777                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total        20777                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        74305                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        74305                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        74305                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total        74305                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        74305                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total        74305                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    798246705                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    798246705                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    798246705                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    798246705                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    798246705                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    798246705                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.392156                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.392156                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.392156                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.392156                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.392156                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.392156                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10742.839715                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10742.839715                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10742.839715                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10742.839715                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10742.839715                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10742.839715                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1000631                       # number of replacements
-system.cpu.icache.tags.tagsinuse           508.729229                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             8114183                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1001143                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              8.104919                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements            998549                       # number of replacements
+system.cpu.icache.tags.tagsinuse           508.782510                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             8117400                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            999061                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              8.125029                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle      148026169000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   508.729229                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.993612                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.993612                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   508.782510                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.993716                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.993716                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          233                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          172                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          242                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          166                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          10182374                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         10182374                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst      8114183                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         8114183                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       8114183                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          8114183                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      8114183                       # number of overall hits
-system.cpu.icache.overall_hits::total         8114183                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1066954                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1066954                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1066954                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1066954                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1066954                       # number of overall misses
-system.cpu.icache.overall_misses::total       1066954                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  14925731792                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  14925731792                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  14925731792                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  14925731792                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  14925731792                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  14925731792                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      9181137                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9181137                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      9181137                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9181137                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      9181137                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9181137                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.116212                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.116212                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.116212                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.116212                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.116212                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.116212                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13989.105240                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13989.105240                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13989.105240                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13989.105240                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13989.105240                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13989.105240                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        10002                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          10181383                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         10181383                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst      8117400                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         8117400                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       8117400                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          8117400                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      8117400                       # number of overall hits
+system.cpu.icache.overall_hits::total         8117400                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1064820                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1064820                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1064820                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1064820                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1064820                       # number of overall misses
+system.cpu.icache.overall_misses::total       1064820                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  14888205043                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  14888205043                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  14888205043                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  14888205043                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  14888205043                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  14888205043                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      9182220                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9182220                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      9182220                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      9182220                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      9182220                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      9182220                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.115965                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.115965                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.115965                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.115965                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.115965                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.115965                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13981.898389                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13981.898389                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13981.898389                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13981.898389                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13981.898389                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13981.898389                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         8289                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               328                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               307                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    30.493902                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs           27                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        65717                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        65717                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        65717                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        65717                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        65717                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        65717                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1001237                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1001237                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1001237                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1001237                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1001237                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1001237                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12740674547                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  12740674547                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12740674547                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  12740674547                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12740674547                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  12740674547                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.109054                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.109054                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.109054                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.109054                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.109054                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.109054                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12724.933804                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12724.933804                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12724.933804                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12724.933804                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12724.933804                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12724.933804                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        65657                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        65657                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        65657                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        65657                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        65657                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        65657                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       999163                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       999163                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       999163                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       999163                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       999163                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       999163                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12710822780                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  12710822780                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12710822780                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12710822780                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12710822780                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  12710822780                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.108815                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.108815                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.108815                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.108815                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.108815                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.108815                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12721.470651                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12721.470651                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12721.470651                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12721.470651                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12721.470651                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12721.470651                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.tags.replacements        14933                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     6.063651                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs        25583                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs        14948                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs     1.711466                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5108134601500                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.063651                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.378978                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total     0.378978                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.replacements        13893                       # number of replacements
+system.cpu.itb_walker_cache.tags.tagsinuse     6.071844                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.total_refs        25336                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.sampled_refs        13905                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.tags.avg_refs     1.822078                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.warmup_cycle 5120509210500                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.071844                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.379490                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total     0.379490                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           12                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
-system.cpu.itb_walker_cache.tags.tag_accesses        98613                       # Number of tag accesses
-system.cpu.itb_walker_cache.tags.data_accesses        98613                       # Number of data accesses
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        25588                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total        25588                       # number of ReadReq hits
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.750000                       # Percentage of cache occupancy per task id
+system.cpu.itb_walker_cache.tags.tag_accesses        95038                       # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses        95038                       # Number of data accesses
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        25353                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total        25353                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        25590                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total        25590                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        25590                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total        25590                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        15811                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total        15811                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        15811                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total        15811                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        15811                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total        15811                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    183242996                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total    183242996                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    183242996                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total    183242996                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    183242996                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total    183242996                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        41399                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        41399                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        25355                       # number of demand (read+write) hits
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+system.cpu.itb_walker_cache.overall_hits::total        25355                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        14776                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total        14776                       # number of ReadReq misses
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+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    169038743                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total    169038743                       # number of ReadReq miss cycles
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+system.cpu.itb_walker_cache.demand_miss_latency::total    169038743                       # number of demand (read+write) miss cycles
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+system.cpu.itb_walker_cache.overall_miss_latency::total    169038743                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        40129                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        40129                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        41401                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        41401                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        41401                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        41401                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.381917                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.381917                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.381899                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.381899                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.381899                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.381899                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11589.589273                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11589.589273                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11589.589273                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11589.589273                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11589.589273                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11589.589273                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        40131                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        40131                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        40131                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        40131                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.368213                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.368213                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.368194                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.368194                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.368194                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.368194                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11440.088184                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11440.088184                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11440.088184                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11440.088184                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11440.088184                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11440.088184                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -1000,177 +1000,177 @@
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks         3310                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total         3310                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        15811                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        15811                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        15811                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total        15811                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        15811                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total        15811                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    159511522                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    159511522                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    159511522                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    159511522                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    159511522                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    159511522                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.381917                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.381917                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.381899                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.381899                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.381899                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.381899                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10088.642211                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10088.642211                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10088.642211                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10088.642211                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10088.642211                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10088.642211                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks         2930                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total         2930                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        14776                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        14776                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        14776                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total        14776                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        14776                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total        14776                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    146855281                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    146855281                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    146855281                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    146855281                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    146855281                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    146855281                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.368213                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.368213                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.368194                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.368194                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.368194                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.368194                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9938.771048                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9938.771048                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9938.771048                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9938.771048                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9938.771048                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9938.771048                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           112684                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64825.802499                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3846196                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           176714                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            21.765089                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           112586                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64823.777262                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3838448                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           176580                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            21.737728                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50361.141250                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    15.517179                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.137228                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3161.997282                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11287.009561                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.768450                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000237                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 50334.465140                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    16.515711                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.150651                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3177.784987                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 11294.860772                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.768043                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000252                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.048248                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.172226                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.989163                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        64030                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          558                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3484                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5616                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54343                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.977020                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         35101682                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        35101682                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        67331                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        13137                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       984666                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1336353                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2401487                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1585305                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1585305                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data          326                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total          326                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       154346                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       154346                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        67331                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker        13137                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       984666                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1490699                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2555833                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        67331                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker        13137                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       984666                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1490699                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2555833                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           66                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        16391                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        35623                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        52085                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         1473                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         1473                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       133459                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       133459                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker           66                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        16391                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       169082                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        185544                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker           66                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        16391                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       169082                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       185544                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      6193250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       446000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1375483774                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   3059797000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   4441920024                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     22673320                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     22673320                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10319199473                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  10319199473                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      6193250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       446000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1375483774                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  13378996473                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  14761119497                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      6193250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       446000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1375483774                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  13378996473                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  14761119497                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        67397                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        13142                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      1001057                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1371976                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2453572                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      1585305                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1585305                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1799                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         1799                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       287805                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       287805                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker        67397                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker        13142                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst      1001057                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1659781                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2741377                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        67397                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker        13142                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1001057                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1659781                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2741377                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000979                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000380                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016374                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.025965                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.021228                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.818788                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.818788                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.463713                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.463713                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000979                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000380                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016374                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.101870                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.067683                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000979                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000380                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016374                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.101870                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.067683                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 93837.121212                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        89200                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83917.013849                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85893.860708                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 85282.135432                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15392.613714                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15392.613714                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77321.120891                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77321.120891                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 93837.121212                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        89200                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83917.013849                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79127.266492                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79555.897776                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 93837.121212                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        89200                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83917.013849                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79127.266492                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79555.897776                       # average overall miss latency
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.048489                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.172346                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.989132                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        63994                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          578                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3409                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4787                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55160                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.976471                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         35090469                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        35090469                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        67085                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        12024                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst       982640                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1337375                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        2399124                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1586308                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1586308                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data          347                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total          347                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       154552                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       154552                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker        67085                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker        12024                       # number of demand (read+write) hits
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+system.cpu.l2cache.overall_avg_miss_latency::total 79565.104111                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1179,99 +1179,99 @@
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       103019                       # number of writebacks
-system.cpu.l2cache.writebacks::total           103019                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            3                       # number of ReadReq MSHR hits
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 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            4                       # number of ReadReq MSHR hits
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 system.cpu.l2cache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
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 system.cpu.l2cache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
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-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11265846277                       # number of demand (read+write) MSHR miss cycles
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-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  88987317500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  88987317500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2410942500                       # number of WriteReq MSHR uncacheable cycles
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-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91398260000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000979                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000380                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016371                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.025964                       # mshr miss rate for ReadReq accesses
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-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.818788                       # mshr miss rate for UpgradeReq accesses
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-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.463713                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000979                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000380                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016371                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.101869                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.067681                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000979                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000380                       # mshr miss rate for overall accesses
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-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.101869                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.067681                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 81238.636364                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        76600                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71405.737491                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73412.238224                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72791.089380                       # average ReadReq mshr miss latency
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-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18332.284453                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64819.574004                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64819.574004                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 81238.636364                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        76600                       # average overall mshr miss latency
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66629.877260                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67057.175019                       # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        76600                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71405.737491                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66629.877260                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67057.175019                       # average overall mshr miss latency
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+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133212                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       133212                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           72                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            6                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        16334                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       168905                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       185317                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           72                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            6                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        16334                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       168905                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       185317                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      5474000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       443250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1164107250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2626406248                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3796430748                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     26736438                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     26736438                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8631944528                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8631944528                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      5474000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       443250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1164107250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11258350776                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  12428375276                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      5474000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       443250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1164107250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11258350776                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  12428375276                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  88988870500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  88988870500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2413772500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2413772500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91402643000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91402643000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001072                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000499                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016351                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.025995                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021257                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.807543                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.807543                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.462921                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.462921                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001072                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000499                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016351                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.101699                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.067659                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001072                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000499                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016351                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.101699                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.067659                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76027.777778                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        73875                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71268.963512                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73583.230549                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72861.160119                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18362.938187                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18362.938187                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64798.550641                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64798.550641                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76027.777778                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        73875                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71268.963512                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66654.928960                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67065.489275                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76027.777778                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        73875                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71268.963512                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66654.928960                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67065.489275                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1279,70 +1279,70 @@
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        3070183                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3069642                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         13919                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        13919                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1585305                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        46754                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2280                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2280                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       287814                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       287814                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError            8                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2002294                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6123530                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        32263                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       162669                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8320756                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     64067648                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207974818                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      1052928                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5614976                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          278710370                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       59545                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4387643                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        3.010865                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.103666                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadReq        3067519                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3066979                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         13939                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        13939                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1586308                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        46766                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2284                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2284                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       287771                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       287771                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError            7                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1998141                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6126615                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        29736                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       162239                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8316731                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     63934592                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    208102552                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       957440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5627776                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          278622360                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       59218                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      4385945                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        3.010871                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.103697                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3            4339973     98.91%     98.91% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4              47670      1.09%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3            4338264     98.91%     98.91% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4              47681      1.09%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4387643                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4071571970                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        4385945                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4071743474                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       574500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       573000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1506228195                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1503118459                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3139390437                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3140913916                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      23723987                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      22173731                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy     112471118                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy     111517380                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq               223900                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              223900                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               57738                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              11018                       # Transaction distribution
+system.iobus.trans_dist::ReadReq               223909                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              223909                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               57755                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              11035                       # Transaction distribution
 system.iobus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1650                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1650                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1653                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1653                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11134                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       423734                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1218                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27824                       # Packet count per connected master and slave (bytes)
@@ -1351,22 +1351,22 @@
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       468004                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95272                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95272                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3300                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3300                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  566576                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       468058                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95270                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95270                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3306                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3306                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  566634                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6712                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6738                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       211867                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2436                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13912                       # Cumulative packet size per connected master and slave (bytes)
@@ -1375,19 +1375,19 @@
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       240285                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027872                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027872                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6600                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6600                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  3274757                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              3933000                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total       240327                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027864                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027864                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6612                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6612                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  3274803                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              3940376                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy              8851000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy              8889000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
@@ -1401,7 +1401,7 @@
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer9.occupancy            211868000                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy             1014000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy             1020000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer11.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
@@ -1417,54 +1417,54 @@
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy           257352407                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy           257361146                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy             1064000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           456986000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           457023000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            50389253                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            50384761                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy             1650000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy             1653000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47582                       # number of replacements
-system.iocache.tags.tagsinuse                0.177916                       # Cycle average of tags in use
+system.iocache.tags.replacements                47580                       # number of replacements
+system.iocache.tags.tagsinuse                0.202391                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47598                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47596                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         4993302485000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.177916                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.011120                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.011120                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         4993301800000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.202391                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.012649                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.012649                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428724                       # Number of tag accesses
-system.iocache.tags.data_accesses              428724                       # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide          916                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              916                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               428715                       # Number of tag accesses
+system.iocache.tags.data_accesses              428715                       # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide          915                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              915                       # number of ReadReq misses
 system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq misses
 system.iocache.WriteInvalidateReq_misses::total        46720                       # number of WriteInvalidateReq misses
-system.iocache.demand_misses::pc.south_bridge.ide          916                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               916                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide          916                       # number of overall misses
-system.iocache.overall_misses::total              916                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    144791938                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    144791938                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide   8565273216                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   8565273216                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    144791938                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    144791938                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    144791938                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    144791938                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          916                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            916                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide          915                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               915                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide          915                       # number of overall misses
+system.iocache.overall_misses::total              915                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    146193424                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    146193424                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide   8577113961                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   8577113961                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    146193424                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    146193424                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    146193424                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    146193424                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          915                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            915                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide          916                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             916                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide          916                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            916                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide          915                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             915                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide          915                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            915                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteInvalidateReq accesses
@@ -1473,40 +1473,40 @@
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158069.801310                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 158069.801310                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 183332.046575                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 183332.046575                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158069.801310                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 158069.801310                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158069.801310                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 158069.801310                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         29224                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 159774.233880                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 159774.233880                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 183585.487179                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 183585.487179                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 159774.233880                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 159774.233880                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 159774.233880                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 159774.233880                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         29604                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 4409                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 4403                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     6.628260                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     6.723598                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           46668                       # number of writebacks
-system.iocache.writebacks::total                46668                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          916                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          916                       # number of ReadReq MSHR misses
+system.iocache.writebacks::writebacks           46667                       # number of writebacks
+system.iocache.writebacks::total                46667                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          915                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          915                       # number of ReadReq MSHR misses
 system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq MSHR misses
 system.iocache.WriteInvalidateReq_mshr_misses::total        46720                       # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide          916                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          916                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide          916                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          916                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     96734432                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     96734432                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   6135821228                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6135821228                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     96734432                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     96734432                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     96734432                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     96734432                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide          915                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          915                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide          915                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          915                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     98194936                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     98194936                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   6147663971                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6147663971                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     98194936                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     98194936                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     98194936                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     98194936                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
@@ -1515,75 +1515,75 @@
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 105605.275109                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 131331.789983                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131331.789983                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 105605.275109                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 105605.275109                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 107316.869945                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 107316.869945                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 131585.273352                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131585.273352                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 107316.869945                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 107316.869945                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 107316.869945                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 107316.869945                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              657690                       # Transaction distribution
-system.membus.trans_dist::ReadResp             657682                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13919                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13919                       # Transaction distribution
-system.membus.trans_dist::Writeback            149687                       # Transaction distribution
+system.membus.trans_dist::ReadReq              657723                       # Transaction distribution
+system.membus.trans_dist::ReadResp             657716                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13939                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13939                       # Transaction distribution
+system.membus.trans_dist::Writeback            149601                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2233                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1752                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            133182                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           133180                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1650                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1650                       # Transaction distribution
-system.membus.trans_dist::BadAddressError            8                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3300                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3300                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       468004                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       769220                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       476828                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           16                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1714068                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141467                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       141467                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1858835                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6600                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total         6600                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       240285                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1538437                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18406720                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20185442                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      6005184                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      6005184                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                26197226                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             1640                       # Total snoops (count)
-system.membus.snoop_fanout::samples            384867                       # Request fanout histogram
+system.membus.trans_dist::UpgradeReq             2217                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1736                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            132934                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           132932                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1653                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1653                       # Transaction distribution
+system.membus.trans_dist::BadAddressError            7                       # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3306                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         3306                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       468058                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       769226                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       476258                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           14                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1713556                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141465                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       141465                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1858327                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6612                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total         6612                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       240327                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1538449                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18386624                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20165400                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      6005120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      6005120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                26177132                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             1646                       # Total snoops (count)
+system.membus.snoop_fanout::samples            384552                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  384867    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  384552    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              384867                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           357799000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              384552                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           357825500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           388520500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           388164500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3300000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3306000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy          1203232654                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy          1202618637                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy               10500                       # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy                8500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            1650000                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            1653000                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         2208381292                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         2206854286                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer4.occupancy           51518747                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy           51509239                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt
index 68d3c49..52df6c3 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt
@@ -1,127 +1,76 @@
 
 ---------- Begin Simulation Statistics ----------
-final_tick                               2783867052000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-host_inst_rate                                 976886                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 567972                       # Number of bytes of host memory used
-host_op_rate                                  1189202                       # Simulator op (including micro ops) rate (op/s)
-host_seconds                                   146.15                       # Real time elapsed on the host
-host_tick_rate                            19047880334                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   142772879                       # Number of instructions simulated
-sim_ops                                     173803124                       # Number of ops (including micro ops) simulated
 sim_seconds                                  2.783867                       # Number of seconds simulated
 sim_ticks                                2783867052000                       # Number of ticks simulated
-system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
-system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
+final_tick                               2783867052000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 903946                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1100409                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            17625645989                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 615176                       # Number of bytes of host memory used
+host_seconds                                   157.94                       # Real time elapsed on the host
+sim_insts                                   142772879                       # Number of instructions simulated
+sim_ops                                     173803124                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.cpu.Branches                          36396981                       # Number of branches fetched
-system.cpu.committedInsts                   142772879                       # Number of instructions committed
-system.cpu.committedOps                     173803124                       # Number of ops (including micro ops) committed
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465959                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       465959                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       457347                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       457347                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.018482                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.018482                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data         8612                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total         8612                       # number of LoadLockedReq misses
-system.cpu.dcache.ReadReq_accesses::cpu.data     30525328                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     30525328                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits::cpu.data     30129052                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        30129052                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012982                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.012982                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::cpu.data       396276                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        396276                       # number of ReadReq misses
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       511200                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       511200                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_hits::cpu.data       395080                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        395080                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.227152                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.227152                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       116120                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       116120                       # number of SoftPFReq misses
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460138                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460138                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460136                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460136                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.WriteReq_accesses::cpu.data     22641788                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     22641788                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits::cpu.data     22340110                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       22340110                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013324                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.013324                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::cpu.data       301678                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       301678                       # number of WriteReq misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::cpu.data     53167116                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     53167116                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_hits::cpu.data      52469162                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         52469162                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_rate::cpu.data     0.013128                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.013128                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::cpu.data       697954                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         697954                       # number of demand (read+write) misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses::cpu.data     53678316                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     53678316                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_hits::cpu.data     52864242                       # number of overall hits
-system.cpu.dcache.overall_hits::total        52864242                       # number of overall hits
-system.cpu.dcache.overall_miss_rate::cpu.data     0.015166                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.015166                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::cpu.data       814074                       # number of overall misses
-system.cpu.dcache.overall_misses::total        814074                       # number of overall misses
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          286                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          196                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
-system.cpu.dcache.tags.avg_refs             65.597713                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.data_accesses        219237582                       # Number of data accesses
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.997174                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999994                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.replacements            819402                       # number of replacements
-system.cpu.dcache.tags.sampled_refs            819914                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.tag_accesses         219237582                       # Number of tag accesses
-system.cpu.dcache.tags.tagsinuse           511.997174                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            53784483                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          23053500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks::writebacks       682059                       # number of writebacks
-system.cpu.dcache.writebacks::total            682059                       # number of writebacks
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.physmem.bytes_read::cpu.dtb.walker          448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1210788                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10328292                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             11540616                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1210788                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1210788                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8837568                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8855092                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker            7                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              27372                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             161899                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                189295                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          138087                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               142468                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker            161                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             46                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               434930                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3710052                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide              345                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4145534                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          434930                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             434930                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3174565                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                6295                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3180860                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3174565                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           161                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            46                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              434930                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3716347                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             345                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7326394                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst             7                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total                7                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total            7                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst            7                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total               7                       # Total bandwidth to/from this memory (bytes/s)
+system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
@@ -129,28 +78,35 @@
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
 system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
 system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.dtb.accesses                      54660704                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                     4349                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                          54650675                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                           10029                       # DTB misses
-system.cpu.dtb.perms_faults                       445                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                   1613                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                 31534804                       # DTB read accesses
-system.cpu.dtb.read_hits                     31526223                       # DTB read hits
-system.cpu.dtb.read_misses                       8581                       # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                     10029                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                10029                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walkWaitTime::samples        10029                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0           10029    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total        10029                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walksPending::samples      6705500                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0         6705500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total      6705500                       # Table walker pending requests distribution
 system.cpu.dtb.walker.walkPageSizes::4K          6354     80.79%     80.79% # Table walker page sizes translated
 system.cpu.dtb.walker.walkPageSizes::1M          1511     19.21%    100.00% # Table walker page sizes translated
 system.cpu.dtb.walker.walkPageSizes::total         7865                       # Table walker page sizes translated
@@ -161,86 +117,28 @@
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7865                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin::total        17894                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkWaitTime::samples        10029                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0           10029    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total        10029                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walks                     10029                       # Table walker walks requested
-system.cpu.dtb.walker.walksPending::samples      6705500                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0         6705500    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total      6705500                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksShort                10029                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.write_accesses                23125900                       # DTB write accesses
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                     31526223                       # DTB read hits
+system.cpu.dtb.read_misses                       8581                       # DTB read misses
 system.cpu.dtb.write_hits                    23124452                       # DTB write hits
 system.cpu.dtb.write_misses                      1448                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::cpu.inst    147042453                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    147042453                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_hits::cpu.inst    145342721                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       145342721                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.011559                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.011559                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::cpu.inst      1699732                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1699732                       # number of ReadReq misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::cpu.inst    147042453                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    147042453                       # number of demand (read+write) accesses
-system.cpu.icache.demand_hits::cpu.inst     145342721                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        145342721                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_rate::cpu.inst     0.011559                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.011559                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::cpu.inst      1699732                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1699732                       # number of demand (read+write) misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses::cpu.inst    147042453                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    147042453                       # number of overall (read+write) accesses
-system.cpu.icache.overall_hits::cpu.inst    145342721                       # number of overall hits
-system.cpu.icache.overall_hits::total       145342721                       # number of overall hits
-system.cpu.icache.overall_miss_rate::cpu.inst     0.011559                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.011559                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::cpu.inst      1699732                       # number of overall misses
-system.cpu.icache.overall_misses::total       1699732                       # number of overall misses
-system.cpu.icache.tags.age_task_id_blocks_1024::0          197                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           77                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          233                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
-system.cpu.icache.tags.avg_refs             85.509500                       # Average number of references to valid blocks.
-system.cpu.icache.tags.data_accesses        148742185                       # Number of data accesses
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.663681                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999343                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999343                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.replacements           1699214                       # number of replacements
-system.cpu.icache.tags.sampled_refs           1699726                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.tag_accesses         148742185                       # Number of tag accesses
-system.cpu.icache.tags.tagsinuse           511.663681                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           145342721                       # Total number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle        7831491500                       # Cycle when the warmup percentage was hit.
-system.cpu.idle_fraction                     0.968015                       # Percentage of idle cycles
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                     4349                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   1613                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                       445                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 31534804                       # DTB read accesses
+system.cpu.dtb.write_accesses                23125900                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                          54650675                       # DTB hits
+system.cpu.dtb.misses                           10029                       # DTB misses
+system.cpu.dtb.accesses                      54660704                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
@@ -248,28 +146,35 @@
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
 system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
 system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.itb.accesses                     147044108                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                     2913                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                           64                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                         147039346                       # DTB hits
-system.cpu.itb.inst_accesses                147044108                       # ITB inst accesses
-system.cpu.itb.inst_hits                    147039346                       # ITB inst hits
-system.cpu.itb.inst_misses                       4762                       # ITB inst misses
-system.cpu.itb.misses                            4762                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                      4762                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                 4762                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walkWaitTime::samples         4762                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0            4762    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total         4762                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walksPending::samples      6702500                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0         6702500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total      6702500                       # Table walker pending requests distribution
 system.cpu.itb.walker.walkPageSizes::4K          2798     90.05%     90.05% # Table walker page sizes translated
 system.cpu.itb.walker.walkPageSizes::1M           309      9.95%    100.00% # Table walker page sizes translated
 system.cpu.itb.walker.walkPageSizes::total         3107                       # Table walker page sizes translated
@@ -280,166 +185,52 @@
 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3107                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::total         3107                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin::total         7869                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkWaitTime::samples         4762                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0            4762    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total         4762                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walks                      4762                       # Table walker walks requested
-system.cpu.itb.walker.walksPending::samples      6702500                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0         6702500    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total      6702500                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksShort                 4762                       # Table walker walks initiated with short descriptors
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_hits                    147039346                       # ITB inst hits
+system.cpu.itb.inst_misses                       4762                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     3083                       # number of quiesce instructions executed
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       298922                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       298922                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_hits::cpu.data       151058                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       151058                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.494657                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.494657                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       147864                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       147864                       # number of ReadExReq misses
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         7608                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3623                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      1699714                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       521008                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2231953                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7601                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3621                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst      1681357                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       505474                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2198053                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000552                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.010800                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.029815                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.015188                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            7                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        18357                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        15534                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        33900                       # number of ReadReq misses
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2756                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2756                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           28                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           28                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.989840                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.989840                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2728                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2728                       # number of UpgradeReq misses
-system.cpu.l2cache.Writeback_accesses::writebacks       682059                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       682059                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits::writebacks       682059                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       682059                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7608                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker         3623                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst      1699714                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       819930                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2530875                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_hits::cpu.dtb.walker         7601                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker         3621                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst      1681357                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       656532                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2349111                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000552                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010800                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.199283                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.071819                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker            7                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        18357                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       163398                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        181764                       # number of demand (read+write) misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7608                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker         3623                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1699714                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       819930                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2530875                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_hits::cpu.dtb.walker         7601                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker         3621                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst      1681357                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       656532                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2349111                       # number of overall hits
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000552                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010800                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.199283                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.071819                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker            7                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        18357                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       163398                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       181764                       # number of overall misses
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          180                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3716                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        10700                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        50640                       # Occupied blocks per task id
-system.cpu.l2cache.tags.avg_refs            15.560628                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.data_accesses        26204344                       # Number of data accesses
-system.cpu.l2cache.tags.occ_blocks::writebacks 48893.401643                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     2.931998                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.004345                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  9064.654943                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  7194.316179                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.746054                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000045                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.138316                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.109777                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.994191                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65276                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.996033                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.replacements           110026                       # number of replacements
-system.cpu.l2cache.tags.sampled_refs           175307                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.tag_accesses         26204344                       # Number of tag accesses
-system.cpu.l2cache.tags.tagsinuse        65155.309107                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2727887                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks::writebacks       101897                       # number of writebacks
-system.cpu.l2cache.writebacks::total           101897                       # number of writebacks
-system.cpu.not_idle_fraction                 0.031985                       # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb                           64                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                     2913                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                147044108                       # ITB inst accesses
+system.cpu.itb.hits                         147039346                       # DTB hits
+system.cpu.itb.misses                            4762                       # DTB misses
+system.cpu.itb.accesses                     147044108                       # DTB accesses
 system.cpu.numCycles                       5567737188                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles               178083441.067325                       # Number of busy cycles
-system.cpu.num_cc_register_reads            530854003                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            62364299                       # number of times the CC registers were written
-system.cpu.num_conditional_control_insts     18730330                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                  11484                       # Number of float alu accesses
-system.cpu.num_fp_insts                         11484                       # number of float instructions
-system.cpu.num_fp_register_reads                 8772                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                2716                       # number of times the floating registers were written
-system.cpu.num_func_calls                    16873899                       # number of times a function call or return occured
-system.cpu.num_idle_cycles               5389653746.932674                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                   142772879                       # Number of instructions committed
+system.cpu.committedOps                     173803124                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             153162683                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                  11484                       # Number of float alu accesses
+system.cpu.num_func_calls                    16873899                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     18730330                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    153162683                       # number of integer instructions
+system.cpu.num_fp_insts                         11484                       # number of float instructions
 system.cpu.num_int_register_reads           285059803                       # number of times the integer registers were read
 system.cpu.num_int_register_writes          107179480                       # number of times the integer registers were written
-system.cpu.num_load_insts                    31855884                       # Number of load instructions
+system.cpu.num_fp_register_reads                 8772                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                2716                       # number of times the floating registers were written
+system.cpu.num_cc_register_reads            530854003                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            62364299                       # number of times the CC registers were written
 system.cpu.num_mem_refs                      55939276                       # number of memory refs
+system.cpu.num_load_insts                    31855884                       # Number of load instructions
 system.cpu.num_store_insts                   24083392                       # Number of store instructions
+system.cpu.num_idle_cycles               5389653746.932674                       # Number of idle cycles
+system.cpu.num_busy_cycles               178083441.067325                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.031985                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.968015                       # Percentage of idle cycles
+system.cpu.Branches                          36396981                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                  2337      0.00%      0.00% # Class of executed instruction
 system.cpu.op_class::IntAlu                 121152838     68.36%     68.36% # Class of executed instruction
 system.cpu.op_class::IntMult                   116892      0.07%     68.43% # Class of executed instruction
@@ -475,6 +266,277 @@
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  177219912                       # Class of executed instruction
+system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
+system.cpu.kern.inst.quiesce                     3083                       # number of quiesce instructions executed
+system.cpu.dcache.tags.replacements            819402                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.997174                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            53784483                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            819914                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             65.597713                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          23053500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.997174                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999994                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          286                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          196                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         219237582                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        219237582                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     30129052                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        30129052                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     22340110                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       22340110                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       395080                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        395080                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       457347                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       457347                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460136                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460136                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      52469162                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         52469162                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     52864242                       # number of overall hits
+system.cpu.dcache.overall_hits::total        52864242                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       396276                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        396276                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       301678                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       301678                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       116120                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       116120                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data         8612                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total         8612                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data       697954                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         697954                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       814074                       # number of overall misses
+system.cpu.dcache.overall_misses::total        814074                       # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data     30525328                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     30525328                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     22641788                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     22641788                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       511200                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       511200                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465959                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       465959                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460138                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460138                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     53167116                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     53167116                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     53678316                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     53678316                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012982                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.012982                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013324                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.013324                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.227152                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.227152                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.018482                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.018482                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.013128                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.013128                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.015166                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.015166                       # miss rate for overall accesses
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       682059                       # number of writebacks
+system.cpu.dcache.writebacks::total            682059                       # number of writebacks
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements           1699214                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.663681                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           145342721                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1699726                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             85.509500                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle        7831491500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.663681                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999343                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999343                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          197                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           77                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          233                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         148742185                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        148742185                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    145342721                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       145342721                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     145342721                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        145342721                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    145342721                       # number of overall hits
+system.cpu.icache.overall_hits::total       145342721                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1699732                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1699732                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1699732                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1699732                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1699732                       # number of overall misses
+system.cpu.icache.overall_misses::total       1699732                       # number of overall misses
+system.cpu.icache.ReadReq_accesses::cpu.inst    147042453                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    147042453                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    147042453                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    147042453                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    147042453                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    147042453                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.011559                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.011559                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.011559                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.011559                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.011559                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.011559                       # miss rate for overall accesses
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.tags.replacements           110026                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65155.309107                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            2727887                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           175307                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            15.560628                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 48893.401643                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     2.931998                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.004345                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  9064.654943                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  7194.316179                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.746054                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000045                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.138316                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.109777                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.994191                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65276                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          180                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3716                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        10700                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        50640                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.996033                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         26204344                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        26204344                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7601                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3621                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst      1681357                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       505474                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        2198053                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       682059                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       682059                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           28                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           28                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       151058                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       151058                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker         7601                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker         3621                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst      1681357                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       656532                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2349111                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker         7601                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker         3621                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst      1681357                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       656532                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2349111                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            7                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst        18357                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        15534                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        33900                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         2728                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         2728                       # number of UpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       147864                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       147864                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker            7                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        18357                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       163398                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        181764                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker            7                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst        18357                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       163398                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       181764                       # number of overall misses
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         7608                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3623                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst      1699714                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       521008                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2231953                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       682059                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       682059                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2756                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         2756                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       298922                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       298922                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7608                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker         3623                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst      1699714                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       819930                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2530875                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7608                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker         3623                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1699714                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       819930                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2530875                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000552                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.010800                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.029815                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.015188                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.989840                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.989840                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.494657                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.494657                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000552                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010800                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.199283                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.071819                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000552                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010800                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.199283                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.071819                       # miss rate for overall accesses
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks       101897                       # number of writebacks
+system.cpu.l2cache.writebacks::total           101897                       # number of writebacks
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq        2288542                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2288542                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         27546                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        27546                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       682059                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2756                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2758                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       298922                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       298922                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3417508                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2444657                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        18430                       # Packet count per connected master and slave (bytes)
@@ -485,6 +547,7 @@
 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        36860                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        74000                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total          205239845                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       36631                       # Total snoops (count)
 system.cpu.toL2Bus.snoop_fanout::samples      3268658                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        3.011156                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.105030                       # Request fanout histogram
@@ -498,18 +561,11 @@
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::total        3268658                       # Request fanout histogram
-system.cpu.toL2Bus.snoops                       36631                       # Total snoops (count)
-system.cpu.toL2Bus.trans_dist::ReadReq        2288542                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2288542                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         27546                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        27546                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       682059                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2756                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2758                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       298922                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       298922                       # Transaction distribution
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.iobus.trans_dist::ReadReq                30164                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               30164                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               59002                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              22778                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
@@ -560,60 +616,67 @@
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321152                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321152                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480213                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.trans_dist::ReadReq                30164                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               30164                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               59002                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              22778                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.iocache.ReadReq_accesses::realview.ide          240                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            240                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_misses::realview.ide          240                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              240                       # number of ReadReq misses
-system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.demand_accesses::realview.ide          240                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             240                       # number of demand (read+write) accesses
-system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.demand_misses::realview.ide          240                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               240                       # number of demand (read+write) misses
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.overall_accesses::realview.ide          240                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            240                       # number of overall (read+write) accesses
-system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.overall_misses::realview.ide          240                       # number of overall misses
-system.iocache.overall_misses::total              240                       # number of overall misses
-system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
+system.iocache.tags.replacements                36430                       # number of replacements
+system.iocache.tags.tagsinuse                0.909961                       # Cycle average of tags in use
+system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs                36446                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.data_accesses              328176                       # Number of data accesses
+system.iocache.tags.warmup_cycle         227409731009                       # Cycle when the warmup percentage was hit.
 system.iocache.tags.occ_blocks::realview.ide     0.909961                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::realview.ide     0.056873                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.056873                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.replacements                36430                       # number of replacements
-system.iocache.tags.sampled_refs                36446                       # Sample count of references to valid blocks.
 system.iocache.tags.tag_accesses               328176                       # Number of tag accesses
-system.iocache.tags.tagsinuse                0.909961                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.warmup_cycle         227409731009                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.data_accesses              328176                       # Number of data accesses
+system.iocache.ReadReq_misses::realview.ide          240                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              240                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
+system.iocache.demand_misses::realview.ide          240                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               240                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide          240                       # number of overall misses
+system.iocache.overall_misses::total              240                       # number of overall misses
+system.iocache.ReadReq_accesses::realview.ide          240                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            240                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ide          240                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             240                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide          240                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            240                       # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq               74227                       # Transaction distribution
+system.membus.trans_dist::ReadResp              74227                       # Transaction distribution
+system.membus.trans_dist::WriteReq              27546                       # Transaction distribution
+system.membus.trans_dist::WriteResp             27546                       # Transaction distribution
+system.membus.trans_dist::Writeback            138087                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4507                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4509                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            146085                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           146085                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105404                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         1946                       # Packet count per connected master and slave (bytes)
@@ -630,6 +693,7 @@
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4649856                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      4649856                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                22909145                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoop_fanout::samples            359045                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
@@ -641,100 +705,36 @@
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::total              359045                       # Request fanout histogram
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.trans_dist::ReadReq               74227                       # Transaction distribution
-system.membus.trans_dist::ReadResp              74227                       # Transaction distribution
-system.membus.trans_dist::WriteReq              27546                       # Transaction distribution
-system.membus.trans_dist::WriteResp             27546                       # Transaction distribution
-system.membus.trans_dist::Writeback            138087                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4507                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4509                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            146085                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           146085                       # Transaction distribution
-system.physmem.bw_inst_read::cpu.inst          434930                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             434930                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker            161                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             46                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               434930                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3710052                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide              345                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4145534                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3174565                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           161                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            46                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              434930                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3716347                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide             345                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7326394                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3174565                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data                6295                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3180860                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bytes_inst_read::cpu.inst      1210788                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1210788                       # Number of instructions bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker          448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1210788                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10328292                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11540616                       # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks      8837568                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8855092                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker            7                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              27372                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             161899                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                189295                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          138087                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               142468                       # Number of write requests responded to by this memory
-system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
-system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
-system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
-system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
-system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
-system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
-system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
-system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
-system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
 system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
-system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
-system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
 system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
+system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
 system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
-system.realview.nvmem.bw_inst_read::cpu.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total            7                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu.inst             7                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total                7                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst            7                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total               7                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
-system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
+system.realview.ethernet.droppedPackets             0                       # number of packets dropped
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
index 3b5938e..456f8f9 100644
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
@@ -4,13 +4,306 @@
 sim_ticks                                200409271000                       # Number of ticks simulated
 final_tick                               4321213476000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                               15445218                       # Simulator instruction rate (inst/s)
-host_op_rate                                 15445213                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5909651303                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 534848                       # Number of bytes of host memory used
-host_seconds                                    33.91                       # Real time elapsed on the host
+host_inst_rate                               10268281                       # Simulator instruction rate (inst/s)
+host_op_rate                                 10268278                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3928851236                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 533084                       # Number of bytes of host memory used
+host_seconds                                    51.01                       # Real time elapsed on the host
 sim_insts                                   523780905                       # Number of instructions simulated
 sim_ops                                     523780905                       # Number of ops (including micro ops) simulated
+drivesys.voltage_domain.voltage                     1                       # Voltage in Volts
+drivesys.clk_domain.clock                        1000                       # Clock period in ticks
+drivesys.physmem.bytes_read::cpu.inst        76205572                       # Number of bytes read from this memory
+drivesys.physmem.bytes_read::cpu.data        26284292                       # Number of bytes read from this memory
+drivesys.physmem.bytes_read::tsunami.ethernet     57260550                       # Number of bytes read from this memory
+drivesys.physmem.bytes_read::total          159750414                       # Number of bytes read from this memory
+drivesys.physmem.bytes_inst_read::cpu.inst     76205572                       # Number of instructions bytes read from this memory
+drivesys.physmem.bytes_inst_read::total      76205572                       # Number of instructions bytes read from this memory
+drivesys.physmem.bytes_written::cpu.data     14619632                       # Number of bytes written to this memory
+drivesys.physmem.bytes_written::tsunami.ethernet         1064                       # Number of bytes written to this memory
+drivesys.physmem.bytes_written::total        14620696                       # Number of bytes written to this memory
+drivesys.physmem.num_reads::cpu.inst         19051393                       # Number of read requests responded to by this memory
+drivesys.physmem.num_reads::cpu.data          3647049                       # Number of read requests responded to by this memory
+drivesys.physmem.num_reads::tsunami.ethernet      2385839                       # Number of read requests responded to by this memory
+drivesys.physmem.num_reads::total            25084281                       # Number of read requests responded to by this memory
+drivesys.physmem.num_writes::cpu.data         2024776                       # Number of write requests responded to by this memory
+drivesys.physmem.num_writes::tsunami.ethernet           37                       # Number of write requests responded to by this memory
+drivesys.physmem.num_writes::total            2024813                       # Number of write requests responded to by this memory
+drivesys.physmem.bw_read::cpu.inst          380249734                       # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::cpu.data          131153074                       # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::tsunami.ethernet    285718069                       # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::total             797120878                       # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_inst_read::cpu.inst     380249734                       # Instruction read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_inst_read::total        380249734                       # Instruction read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_write::cpu.data          72948881                       # Write bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_write::tsunami.ethernet         5309                       # Write bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_write::total             72954190                       # Write bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_total::cpu.inst         380249734                       # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::cpu.data         204101955                       # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::tsunami.ethernet    285723379                       # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::total            870075068                       # Total bandwidth to/from this memory (bytes/s)
+drivesys.cpu.clk_domain.clock                     250                       # Clock period in ticks
+drivesys.cpu.dtb.fetch_hits                         0                       # ITB hits
+drivesys.cpu.dtb.fetch_misses                       0                       # ITB misses
+drivesys.cpu.dtb.fetch_acv                          0                       # ITB acv
+drivesys.cpu.dtb.fetch_accesses                     0                       # ITB accesses
+drivesys.cpu.dtb.read_hits                    3725273                       # DTB read hits
+drivesys.cpu.dtb.read_misses                      487                       # DTB read misses
+drivesys.cpu.dtb.read_acv                          30                       # DTB read access violations
+drivesys.cpu.dtb.read_accesses                 267991                       # DTB read accesses
+drivesys.cpu.dtb.write_hits                   2084079                       # DTB write hits
+drivesys.cpu.dtb.write_misses                      82                       # DTB write misses
+drivesys.cpu.dtb.write_acv                         10                       # DTB write access violations
+drivesys.cpu.dtb.write_accesses                133239                       # DTB write accesses
+drivesys.cpu.dtb.data_hits                    5809352                       # DTB hits
+drivesys.cpu.dtb.data_misses                      569                       # DTB misses
+drivesys.cpu.dtb.data_acv                          40                       # DTB access violations
+drivesys.cpu.dtb.data_accesses                 401230                       # DTB accesses
+drivesys.cpu.itb.fetch_hits                   4197628                       # ITB hits
+drivesys.cpu.itb.fetch_misses                     194                       # ITB misses
+drivesys.cpu.itb.fetch_acv                         22                       # ITB acv
+drivesys.cpu.itb.fetch_accesses               4197822                       # ITB accesses
+drivesys.cpu.itb.read_hits                          0                       # DTB read hits
+drivesys.cpu.itb.read_misses                        0                       # DTB read misses
+drivesys.cpu.itb.read_acv                           0                       # DTB read access violations
+drivesys.cpu.itb.read_accesses                      0                       # DTB read accesses
+drivesys.cpu.itb.write_hits                         0                       # DTB write hits
+drivesys.cpu.itb.write_misses                       0                       # DTB write misses
+drivesys.cpu.itb.write_acv                          0                       # DTB write access violations
+drivesys.cpu.itb.write_accesses                     0                       # DTB write accesses
+drivesys.cpu.itb.data_hits                          0                       # DTB hits
+drivesys.cpu.itb.data_misses                        0                       # DTB misses
+drivesys.cpu.itb.data_acv                           0                       # DTB access violations
+drivesys.cpu.itb.data_accesses                      0                       # DTB accesses
+drivesys.cpu.numCycles                      801651324                       # number of cpu cycles simulated
+drivesys.cpu.numWorkItemsStarted                    0                       # number of work items this cpu started
+drivesys.cpu.numWorkItemsCompleted                  0                       # number of work items this cpu completed
+drivesys.cpu.committedInsts                  19050784                       # Number of instructions committed
+drivesys.cpu.committedOps                    19050784                       # Number of ops (including micro ops) committed
+drivesys.cpu.num_int_alu_accesses            17740632                       # Number of integer alu accesses
+drivesys.cpu.num_fp_alu_accesses                 1412                       # Number of float alu accesses
+drivesys.cpu.num_func_calls                   1265024                       # number of times a function call or return occured
+drivesys.cpu.num_conditional_control_insts      1264985                       # number of instructions that are conditional controls
+drivesys.cpu.num_int_insts                   17740632                       # number of integer instructions
+drivesys.cpu.num_fp_insts                        1412                       # number of float instructions
+drivesys.cpu.num_int_register_reads          23072330                       # number of times the integer registers were read
+drivesys.cpu.num_int_register_writes         13981107                       # number of times the integer registers were written
+drivesys.cpu.num_fp_register_reads                760                       # number of times the floating registers were read
+drivesys.cpu.num_fp_register_writes               766                       # number of times the floating registers were written
+drivesys.cpu.num_mem_refs                     5830788                       # number of memory refs
+drivesys.cpu.num_load_insts                   3746196                       # Number of load instructions
+drivesys.cpu.num_store_insts                  2084592                       # Number of store instructions
+drivesys.cpu.num_idle_cycles             782619252.927065                       # Number of idle cycles
+drivesys.cpu.num_busy_cycles             19032071.072935                       # Number of busy cycles
+drivesys.cpu.not_idle_fraction               0.023741                       # Percentage of non-idle cycles
+drivesys.cpu.idle_fraction                   0.976259                       # Percentage of idle cycles
+drivesys.cpu.Branches                         2793313                       # Number of branches fetched
+drivesys.cpu.op_class::No_OpClass              623554      3.27%      3.27% # Class of executed instruction
+drivesys.cpu.op_class::IntAlu                11538627     60.57%     63.84% # Class of executed instruction
+drivesys.cpu.op_class::IntMult                  20663      0.11%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::IntDiv                       0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::FloatAdd                   141      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::FloatCmp                     0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::FloatCvt                     0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::FloatMult                    0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::FloatDiv                    23      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::FloatSqrt                    0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdAdd                      0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdAddAcc                   0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdAlu                      0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdCmp                      0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdCvt                      0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdMisc                     0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdMult                     0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdMultAcc                  0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdShift                    0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdShiftAcc                 0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdSqrt                     0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatAdd                 0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatAlu                 0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatCmp                 0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatCvt                 0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatDiv                 0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatMisc                0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatMult                0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatMultAcc             0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatSqrt                0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::MemRead                4026028     21.13%     85.08% # Class of executed instruction
+drivesys.cpu.op_class::MemWrite               2085021     10.94%     96.02% # Class of executed instruction
+drivesys.cpu.op_class::IprAccess               757336      3.98%    100.00% # Class of executed instruction
+drivesys.cpu.op_class::InstPrefetch                 0      0.00%    100.00% # Class of executed instruction
+drivesys.cpu.op_class::total                 19051393                       # Class of executed instruction
+drivesys.cpu.kern.inst.arm                          0                       # number of arm instructions executed
+drivesys.cpu.kern.inst.quiesce                  19876                       # number of quiesce instructions executed
+drivesys.cpu.kern.inst.hwrei                   143591                       # number of hwrei instructions executed
+drivesys.cpu.kern.ipl_count::0                  60359     42.42%     42.42% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::21                 19727     13.86%     56.28% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::22                   205      0.14%     56.42% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::31                 62011     43.58%    100.00% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::total             142302                       # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_good::0                   60359     42.91%     42.91% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::21                  19727     14.03%     56.94% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::22                    205      0.15%     57.09% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::31                  60360     42.91%    100.00% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::total              140651                       # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_ticks::0           197399332500     98.50%     98.50% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::21             798910750      0.40%     98.90% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::22               4407500      0.00%     98.90% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::31            2205211250      1.10%    100.00% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::total       200407862000                       # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_used::0                       1                       # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.ipl_used::21                      1                       # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.ipl_used::22                      1                       # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.ipl_used::31               0.973376                       # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.ipl_used::total            0.988398                       # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.syscall::2                        1      4.55%      4.55% # number of syscalls executed
+drivesys.cpu.kern.syscall::6                        3     13.64%     18.18% # number of syscalls executed
+drivesys.cpu.kern.syscall::17                       2      9.09%     27.27% # number of syscalls executed
+drivesys.cpu.kern.syscall::97                       1      4.55%     31.82% # number of syscalls executed
+drivesys.cpu.kern.syscall::99                       2      9.09%     40.91% # number of syscalls executed
+drivesys.cpu.kern.syscall::101                      2      9.09%     50.00% # number of syscalls executed
+drivesys.cpu.kern.syscall::102                      3     13.64%     63.64% # number of syscalls executed
+drivesys.cpu.kern.syscall::104                      1      4.55%     68.18% # number of syscalls executed
+drivesys.cpu.kern.syscall::105                      3     13.64%     81.82% # number of syscalls executed
+drivesys.cpu.kern.syscall::106                      1      4.55%     86.36% # number of syscalls executed
+drivesys.cpu.kern.syscall::118                      2      9.09%     95.45% # number of syscalls executed
+drivesys.cpu.kern.syscall::150                      1      4.55%    100.00% # number of syscalls executed
+drivesys.cpu.kern.syscall::total                   22                       # number of syscalls executed
+drivesys.cpu.kern.callpal::swpctx                  72      0.06%      0.06% # number of callpals executed
+drivesys.cpu.kern.callpal::tbi                      5      0.00%      0.06% # number of callpals executed
+drivesys.cpu.kern.callpal::swpipl              102333     83.31%     83.37% # number of callpals executed
+drivesys.cpu.kern.callpal::rdps                   354      0.29%     83.66% # number of callpals executed
+drivesys.cpu.kern.callpal::rdusp                    1      0.00%     83.66% # number of callpals executed
+drivesys.cpu.kern.callpal::rti                  20038     16.31%     99.97% # number of callpals executed
+drivesys.cpu.kern.callpal::callsys                 25      0.02%     99.99% # number of callpals executed
+drivesys.cpu.kern.callpal::imb                      7      0.01%    100.00% # number of callpals executed
+drivesys.cpu.kern.callpal::total               122835                       # number of callpals executed
+drivesys.cpu.kern.mode_switch::kernel             214                       # number of protection mode switches
+drivesys.cpu.kern.mode_switch::user               140                       # number of protection mode switches
+drivesys.cpu.kern.mode_switch::idle             19896                       # number of protection mode switches
+drivesys.cpu.kern.mode_good::kernel               144                      
+drivesys.cpu.kern.mode_good::user                 140                      
+drivesys.cpu.kern.mode_good::idle                   4                      
+drivesys.cpu.kern.mode_switch_good::kernel     0.672897                       # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good::user            1                       # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good::idle     0.000201                       # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good::total     0.014222                       # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_ticks::kernel         78134250      2.63%      2.63% # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_ticks::user          319668250     10.78%     13.41% # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_ticks::idle         2567942000     86.59%    100.00% # number of ticks spent at the given mode
+drivesys.cpu.kern.swap_context                     72                       # number of times the context was actually changed
+drivesys.disk0.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
+drivesys.disk0.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
+drivesys.disk0.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
+drivesys.disk0.dma_write_full_pages                 0                       # Number of full page size DMA writes.
+drivesys.disk0.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
+drivesys.disk0.dma_write_txs                        0                       # Number of DMA write transactions.
+drivesys.disk2.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
+drivesys.disk2.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
+drivesys.disk2.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
+drivesys.disk2.dma_write_full_pages                 0                       # Number of full page size DMA writes.
+drivesys.disk2.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
+drivesys.disk2.dma_write_txs                        0                       # Number of DMA write transactions.
+drivesys.iobus.trans_dist::ReadReq            2484469                       # Transaction distribution
+drivesys.iobus.trans_dist::ReadResp           2484469                       # Transaction distribution
+drivesys.iobus.trans_dist::WriteReq             39723                       # Transaction distribution
+drivesys.iobus.trans_dist::WriteResp            39723                       # Transaction distribution
+drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.cchip.pio       197670                       # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.ethernet.pio        78962                       # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.bridge.master::total       276632                       # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave      4771752                       # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::total      4771752                       # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count::total               5048384                       # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.cchip.pio       790680                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.ethernet.pio       157924                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.bridge.master::total       948604                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave     57261614                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total     57261614                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size::total               58210218                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.trans_dist::ReadReq          25081955                       # Transaction distribution
+drivesys.membus.trans_dist::ReadResp         25182911                       # Transaction distribution
+drivesys.membus.trans_dist::WriteReq          1963575                       # Transaction distribution
+drivesys.membus.trans_dist::WriteResp         1963575                       # Transaction distribution
+drivesys.membus.trans_dist::LoadLockedReq       100956                       # Transaction distribution
+drivesys.membus.trans_dist::StoreCondReq       100924                       # Transaction distribution
+drivesys.membus.trans_dist::StoreCondResp       100924                       # Transaction distribution
+drivesys.membus.pkt_count_drivesys.cpu.icache_port::drivesys.physmem.port     38102786                       # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.icache_port::total     38102786                       # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.bridge.slave       276632                       # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.physmem.port     11343650                       # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.dcache_port::total     11620282                       # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.iobridge.master::drivesys.physmem.port      4771752                       # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.iobridge.master::total      4771752                       # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count::total             54494820                       # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.icache_port::drivesys.physmem.port     76205572                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.icache_port::total     76205572                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.bridge.slave       948604                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.physmem.port     40903924                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.dcache_port::total     41852528                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port     57261614                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.iobridge.master::total     57261614                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size::total             175319714                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.snoops                              0                       # Total snoops (count)
+drivesys.membus.snoop_fanout::samples        27109094                       # Request fanout histogram
+drivesys.membus.snoop_fanout::mean           0.790778                       # Request fanout histogram
+drivesys.membus.snoop_fanout::stdev          0.406753                       # Request fanout histogram
+drivesys.membus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+drivesys.membus.snoop_fanout::0               5671825     20.92%     20.92% # Request fanout histogram
+drivesys.membus.snoop_fanout::1              21437269     79.08%    100.00% # Request fanout histogram
+drivesys.membus.snoop_fanout::overflows             0      0.00%    100.00% # Request fanout histogram
+drivesys.membus.snoop_fanout::min_value             0                       # Request fanout histogram
+drivesys.membus.snoop_fanout::max_value             1                       # Request fanout histogram
+drivesys.membus.snoop_fanout::total          27109094                       # Request fanout histogram
+drivesys.tsunami.ethernet.clk_domain.clock         2000                       # Clock period in ticks
+drivesys.tsunami.ethernet.txBytes                 798                       # Bytes Transmitted
+drivesys.tsunami.ethernet.rxBytes                 960                       # Bytes Received
+drivesys.tsunami.ethernet.txPackets                 5                       # Number of Packets Transmitted
+drivesys.tsunami.ethernet.rxPackets                 8                       # Number of Packets Received
+drivesys.tsunami.ethernet.txIpChecksums             2                       # Number of tx IP Checksums done by device
+drivesys.tsunami.ethernet.rxIpChecksums             8                       # Number of rx IP Checksums done by device
+drivesys.tsunami.ethernet.txTcpChecksums            2                       # Number of tx TCP Checksums done by device
+drivesys.tsunami.ethernet.rxTcpChecksums            8                       # Number of rx TCP Checksums done by device
+drivesys.tsunami.ethernet.txUdpChecksums            0                       # Number of tx UDP Checksums done by device
+drivesys.tsunami.ethernet.rxUdpChecksums            0                       # Number of rx UDP Checksums done by device
+drivesys.tsunami.ethernet.descDMAReads        2385810                       # Number of descriptors the device read w/ DMA
+drivesys.tsunami.ethernet.descDMAWrites            13                       # Number of descriptors the device wrote w/ DMA
+drivesys.tsunami.ethernet.descDmaReadBytes     57259440                       # number of descriptor bytes read w/ DMA
+drivesys.tsunami.ethernet.descDmaWriteBytes          104                       # number of descriptor bytes write w/ DMA
+drivesys.tsunami.ethernet.totBandwidth          70176                       # Total Bandwidth (bits/s)
+drivesys.tsunami.ethernet.totPackets               13                       # Total Packets
+drivesys.tsunami.ethernet.totBytes               1758                       # Total Bytes
+drivesys.tsunami.ethernet.totPPS                   65                       # Total Tranmission Rate (packets/s)
+drivesys.tsunami.ethernet.txBandwidth           31855                       # Transmit Bandwidth (bits/s)
+drivesys.tsunami.ethernet.rxBandwidth           38322                       # Receive Bandwidth (bits/s)
+drivesys.tsunami.ethernet.txPPS                    25                       # Packet Tranmission Rate (packets/s)
+drivesys.tsunami.ethernet.rxPPS                    40                       # Packet Reception Rate (packets/s)
+drivesys.tsunami.ethernet.postedSwi                 0                       # number of software interrupts posted to CPU
+drivesys.tsunami.ethernet.coalescedSwi              0                       # average number of Swi's coalesced into each post
+drivesys.tsunami.ethernet.totalSwi                  0                       # total number of Swi written to ISR
+drivesys.tsunami.ethernet.postedRxIdle              0                       # number of rxIdle interrupts posted to CPU
+drivesys.tsunami.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
+drivesys.tsunami.ethernet.totalRxIdle               0                       # total number of RxIdle written to ISR
+drivesys.tsunami.ethernet.postedRxOk                0                       # number of RxOk interrupts posted to CPU
+drivesys.tsunami.ethernet.coalescedRxOk             0                       # average number of RxOk's coalesced into each post
+drivesys.tsunami.ethernet.totalRxOk                 0                       # total number of RxOk written to ISR
+drivesys.tsunami.ethernet.postedRxDesc              8                       # number of RxDesc interrupts posted to CPU
+drivesys.tsunami.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
+drivesys.tsunami.ethernet.totalRxDesc               8                       # total number of RxDesc written to ISR
+drivesys.tsunami.ethernet.postedTxOk                0                       # number of TxOk interrupts posted to CPU
+drivesys.tsunami.ethernet.coalescedTxOk             0                       # average number of TxOk's coalesced into each post
+drivesys.tsunami.ethernet.totalTxOk                 0                       # total number of TxOk written to ISR
+drivesys.tsunami.ethernet.postedTxIdle          19726                       # number of TxIdle interrupts posted to CPU
+drivesys.tsunami.ethernet.coalescedTxIdle            1                       # average number of TxIdle's coalesced into each post
+drivesys.tsunami.ethernet.totalTxIdle         2385810                       # total number of TxIdle written to ISR
+drivesys.tsunami.ethernet.postedTxDesc              0                       # number of TxDesc interrupts posted to CPU
+drivesys.tsunami.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
+drivesys.tsunami.ethernet.totalTxDesc               0                       # total number of TxDesc written to ISR
+drivesys.tsunami.ethernet.postedRxOrn               0                       # number of RxOrn posted to CPU
+drivesys.tsunami.ethernet.coalescedRxOrn            0                       # average number of RxOrn's coalesced into each post
+drivesys.tsunami.ethernet.totalRxOrn                0                       # total number of RxOrn written to ISR
+drivesys.tsunami.ethernet.coalescedTotal            1                       # average number of interrupts coalesced into each post
+drivesys.tsunami.ethernet.postedInterrupts      2385831                       # number of posts to CPU
+drivesys.tsunami.ethernet.droppedPackets            0                       # number of packets dropped
 testsys.voltage_domain.voltage                      1                       # Voltage in Volts
 testsys.clk_domain.clock                         1000                       # Clock period in ticks
 testsys.physmem.bytes_read::cpu.inst         81044080                       # Number of bytes read from this memory
@@ -42,52 +335,6 @@
 testsys.physmem.bw_total::cpu.data          221698925                       # Total bandwidth to/from this memory (bytes/s)
 testsys.physmem.bw_total::tsunami.ethernet    285722301                       # Total bandwidth to/from this memory (bytes/s)
 testsys.physmem.bw_total::total             911814095                       # Total bandwidth to/from this memory (bytes/s)
-testsys.membus.trans_dist::ReadReq           26478762                       # Transaction distribution
-testsys.membus.trans_dist::ReadResp          26587372                       # Transaction distribution
-testsys.membus.trans_dist::WriteReq           2189273                       # Transaction distribution
-testsys.membus.trans_dist::WriteResp          2189273                       # Transaction distribution
-testsys.membus.trans_dist::LoadLockedReq       108610                       # Transaction distribution
-testsys.membus.trans_dist::StoreCondReq        108528                       # Transaction distribution
-testsys.membus.trans_dist::StoreCondResp       108528                       # Transaction distribution
-testsys.membus.pkt_count_testsys.cpu.icache_port::testsys.physmem.port     40522040                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.icache_port::total     40522040                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.bridge.slave       275298                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.physmem.port     12201274                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.dcache_port::total     12476572                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.iobridge.master::testsys.physmem.port      4771734                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.iobridge.master::total      4771734                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count::total              57770346                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.icache_port::testsys.physmem.port     81044080                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.icache_port::total     81044080                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.bridge.slave       942152                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.physmem.port     44430520                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.dcache_port::total     45372672                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port     57261398                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.iobridge.master::total     57261398                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size::total              183678150                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.snoops                               0                       # Total snoops (count)
-testsys.membus.snoop_fanout::samples         28747524                       # Request fanout histogram
-testsys.membus.snoop_fanout::mean            0.787786                       # Request fanout histogram
-testsys.membus.snoop_fanout::stdev           0.408876                       # Request fanout histogram
-testsys.membus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-testsys.membus.snoop_fanout::0                6100637     21.22%     21.22% # Request fanout histogram
-testsys.membus.snoop_fanout::1               22646887     78.78%    100.00% # Request fanout histogram
-testsys.membus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-testsys.membus.snoop_fanout::min_value              0                       # Request fanout histogram
-testsys.membus.snoop_fanout::max_value              1                       # Request fanout histogram
-testsys.membus.snoop_fanout::total           28747524                       # Request fanout histogram
-testsys.disk0.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
-testsys.disk0.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk0.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
-testsys.disk0.dma_write_full_pages                  0                       # Number of full page size DMA writes.
-testsys.disk0.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
-testsys.disk0.dma_write_txs                         0                       # Number of DMA write transactions.
-testsys.disk2.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
-testsys.disk2.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk2.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
-testsys.disk2.dma_write_full_pages                  0                       # Number of full page size DMA writes.
-testsys.disk2.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
-testsys.disk2.dma_write_txs                         0                       # Number of DMA write transactions.
 testsys.cpu.clk_domain.clock                      500                       # Clock period in ticks
 testsys.cpu.dtb.fetch_hits                          0                       # ITB hits
 testsys.cpu.dtb.fetch_misses                        0                       # ITB misses
@@ -248,6 +495,72 @@
 testsys.cpu.kern.mode_ticks::user           533088000     32.15%     92.11% # number of ticks spent at the given mode
 testsys.cpu.kern.mode_ticks::idle           130749000      7.89%    100.00% # number of ticks spent at the given mode
 testsys.cpu.kern.swap_context                     438                       # number of times the context was actually changed
+testsys.disk0.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
+testsys.disk0.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
+testsys.disk0.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
+testsys.disk0.dma_write_full_pages                  0                       # Number of full page size DMA writes.
+testsys.disk0.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
+testsys.disk0.dma_write_txs                         0                       # Number of DMA write transactions.
+testsys.disk2.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
+testsys.disk2.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
+testsys.disk2.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
+testsys.disk2.dma_write_full_pages                  0                       # Number of full page size DMA writes.
+testsys.disk2.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
+testsys.disk2.dma_write_txs                         0                       # Number of DMA write transactions.
+testsys.iobus.trans_dist::ReadReq             2483943                       # Transaction distribution
+testsys.iobus.trans_dist::ReadResp            2483943                       # Transaction distribution
+testsys.iobus.trans_dist::WriteReq              39573                       # Transaction distribution
+testsys.iobus.trans_dist::WriteResp             39573                       # Transaction distribution
+testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.cchip.pio       196204                       # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.io.pio          336                       # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.uart.pio          428                       # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.ethernet.pio        78330                       # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.bridge.master::total       275298                       # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::testsys.iobridge.slave      4771734                       # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::total      4771734                       # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count::total                5047032                       # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.cchip.pio       784816                       # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.io.pio          462                       # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.uart.pio          214                       # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.ethernet.pio       156660                       # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::total       942152                       # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave     57261398                       # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total     57261398                       # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size::total                58203550                       # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.trans_dist::ReadReq           26478762                       # Transaction distribution
+testsys.membus.trans_dist::ReadResp          26587372                       # Transaction distribution
+testsys.membus.trans_dist::WriteReq           2189273                       # Transaction distribution
+testsys.membus.trans_dist::WriteResp          2189273                       # Transaction distribution
+testsys.membus.trans_dist::LoadLockedReq       108610                       # Transaction distribution
+testsys.membus.trans_dist::StoreCondReq        108528                       # Transaction distribution
+testsys.membus.trans_dist::StoreCondResp       108528                       # Transaction distribution
+testsys.membus.pkt_count_testsys.cpu.icache_port::testsys.physmem.port     40522040                       # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.icache_port::total     40522040                       # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.bridge.slave       275298                       # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.physmem.port     12201274                       # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.dcache_port::total     12476572                       # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.iobridge.master::testsys.physmem.port      4771734                       # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.iobridge.master::total      4771734                       # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count::total              57770346                       # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.icache_port::testsys.physmem.port     81044080                       # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.icache_port::total     81044080                       # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.bridge.slave       942152                       # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.physmem.port     44430520                       # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.dcache_port::total     45372672                       # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port     57261398                       # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.iobridge.master::total     57261398                       # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size::total              183678150                       # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.snoops                               0                       # Total snoops (count)
+testsys.membus.snoop_fanout::samples         28747524                       # Request fanout histogram
+testsys.membus.snoop_fanout::mean            0.787786                       # Request fanout histogram
+testsys.membus.snoop_fanout::stdev           0.408876                       # Request fanout histogram
+testsys.membus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
+testsys.membus.snoop_fanout::0                6100637     21.22%     21.22% # Request fanout histogram
+testsys.membus.snoop_fanout::1               22646887     78.78%    100.00% # Request fanout histogram
+testsys.membus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
+testsys.membus.snoop_fanout::min_value              0                       # Request fanout histogram
+testsys.membus.snoop_fanout::max_value              1                       # Request fanout histogram
+testsys.membus.snoop_fanout::total           28747524                       # Request fanout histogram
 testsys.tsunami.ethernet.clk_domain.clock         2000                       # Clock period in ticks
 testsys.tsunami.ethernet.txBytes                  960                       # Bytes Transmitted
 testsys.tsunami.ethernet.rxBytes                  798                       # Bytes Received
@@ -298,319 +611,6 @@
 testsys.tsunami.ethernet.coalescedTotal             1                       # average number of interrupts coalesced into each post
 testsys.tsunami.ethernet.postedInterrupts      2385819                       # number of posts to CPU
 testsys.tsunami.ethernet.droppedPackets             0                       # number of packets dropped
-testsys.iobus.trans_dist::ReadReq             2483943                       # Transaction distribution
-testsys.iobus.trans_dist::ReadResp            2483943                       # Transaction distribution
-testsys.iobus.trans_dist::WriteReq              39573                       # Transaction distribution
-testsys.iobus.trans_dist::WriteResp             39573                       # Transaction distribution
-testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.cchip.pio       196204                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.io.pio          336                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.uart.pio          428                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.ethernet.pio        78330                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.bridge.master::total       275298                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::testsys.iobridge.slave      4771734                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::total      4771734                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count::total                5047032                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.cchip.pio       784816                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.io.pio          462                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.uart.pio          214                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.ethernet.pio       156660                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::total       942152                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave     57261398                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total     57261398                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size::total                58203550                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.voltage_domain.voltage                     1                       # Voltage in Volts
-drivesys.clk_domain.clock                        1000                       # Clock period in ticks
-drivesys.physmem.bytes_read::cpu.inst        76205572                       # Number of bytes read from this memory
-drivesys.physmem.bytes_read::cpu.data        26284292                       # Number of bytes read from this memory
-drivesys.physmem.bytes_read::tsunami.ethernet     57260550                       # Number of bytes read from this memory
-drivesys.physmem.bytes_read::total          159750414                       # Number of bytes read from this memory
-drivesys.physmem.bytes_inst_read::cpu.inst     76205572                       # Number of instructions bytes read from this memory
-drivesys.physmem.bytes_inst_read::total      76205572                       # Number of instructions bytes read from this memory
-drivesys.physmem.bytes_written::cpu.data     14619632                       # Number of bytes written to this memory
-drivesys.physmem.bytes_written::tsunami.ethernet         1064                       # Number of bytes written to this memory
-drivesys.physmem.bytes_written::total        14620696                       # Number of bytes written to this memory
-drivesys.physmem.num_reads::cpu.inst         19051393                       # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::cpu.data          3647049                       # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::tsunami.ethernet      2385839                       # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::total            25084281                       # Number of read requests responded to by this memory
-drivesys.physmem.num_writes::cpu.data         2024776                       # Number of write requests responded to by this memory
-drivesys.physmem.num_writes::tsunami.ethernet           37                       # Number of write requests responded to by this memory
-drivesys.physmem.num_writes::total            2024813                       # Number of write requests responded to by this memory
-drivesys.physmem.bw_read::cpu.inst          380249734                       # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::cpu.data          131153074                       # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::tsunami.ethernet    285718069                       # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::total             797120878                       # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::cpu.inst     380249734                       # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::total        380249734                       # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::cpu.data          72948881                       # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::tsunami.ethernet         5309                       # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::total             72954190                       # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.inst         380249734                       # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.data         204101955                       # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::tsunami.ethernet    285723379                       # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::total            870075068                       # Total bandwidth to/from this memory (bytes/s)
-drivesys.membus.trans_dist::ReadReq          25081955                       # Transaction distribution
-drivesys.membus.trans_dist::ReadResp         25182911                       # Transaction distribution
-drivesys.membus.trans_dist::WriteReq          1963575                       # Transaction distribution
-drivesys.membus.trans_dist::WriteResp         1963575                       # Transaction distribution
-drivesys.membus.trans_dist::LoadLockedReq       100956                       # Transaction distribution
-drivesys.membus.trans_dist::StoreCondReq       100924                       # Transaction distribution
-drivesys.membus.trans_dist::StoreCondResp       100924                       # Transaction distribution
-drivesys.membus.pkt_count_drivesys.cpu.icache_port::drivesys.physmem.port     38102786                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.icache_port::total     38102786                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.bridge.slave       276632                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.physmem.port     11343650                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.dcache_port::total     11620282                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.iobridge.master::drivesys.physmem.port      4771752                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.iobridge.master::total      4771752                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count::total             54494820                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.icache_port::drivesys.physmem.port     76205572                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.icache_port::total     76205572                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.bridge.slave       948604                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.physmem.port     40903924                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.dcache_port::total     41852528                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port     57261614                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.iobridge.master::total     57261614                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size::total             175319714                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.snoops                              0                       # Total snoops (count)
-drivesys.membus.snoop_fanout::samples        27109094                       # Request fanout histogram
-drivesys.membus.snoop_fanout::mean           0.790778                       # Request fanout histogram
-drivesys.membus.snoop_fanout::stdev          0.406753                       # Request fanout histogram
-drivesys.membus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-drivesys.membus.snoop_fanout::0               5671825     20.92%     20.92% # Request fanout histogram
-drivesys.membus.snoop_fanout::1              21437269     79.08%    100.00% # Request fanout histogram
-drivesys.membus.snoop_fanout::overflows             0      0.00%    100.00% # Request fanout histogram
-drivesys.membus.snoop_fanout::min_value             0                       # Request fanout histogram
-drivesys.membus.snoop_fanout::max_value             1                       # Request fanout histogram
-drivesys.membus.snoop_fanout::total          27109094                       # Request fanout histogram
-drivesys.disk0.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
-drivesys.disk0.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
-drivesys.disk0.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
-drivesys.disk0.dma_write_full_pages                 0                       # Number of full page size DMA writes.
-drivesys.disk0.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
-drivesys.disk0.dma_write_txs                        0                       # Number of DMA write transactions.
-drivesys.disk2.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
-drivesys.disk2.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
-drivesys.disk2.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
-drivesys.disk2.dma_write_full_pages                 0                       # Number of full page size DMA writes.
-drivesys.disk2.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
-drivesys.disk2.dma_write_txs                        0                       # Number of DMA write transactions.
-drivesys.cpu.clk_domain.clock                     250                       # Clock period in ticks
-drivesys.cpu.dtb.fetch_hits                         0                       # ITB hits
-drivesys.cpu.dtb.fetch_misses                       0                       # ITB misses
-drivesys.cpu.dtb.fetch_acv                          0                       # ITB acv
-drivesys.cpu.dtb.fetch_accesses                     0                       # ITB accesses
-drivesys.cpu.dtb.read_hits                    3725273                       # DTB read hits
-drivesys.cpu.dtb.read_misses                      487                       # DTB read misses
-drivesys.cpu.dtb.read_acv                          30                       # DTB read access violations
-drivesys.cpu.dtb.read_accesses                 267991                       # DTB read accesses
-drivesys.cpu.dtb.write_hits                   2084079                       # DTB write hits
-drivesys.cpu.dtb.write_misses                      82                       # DTB write misses
-drivesys.cpu.dtb.write_acv                         10                       # DTB write access violations
-drivesys.cpu.dtb.write_accesses                133239                       # DTB write accesses
-drivesys.cpu.dtb.data_hits                    5809352                       # DTB hits
-drivesys.cpu.dtb.data_misses                      569                       # DTB misses
-drivesys.cpu.dtb.data_acv                          40                       # DTB access violations
-drivesys.cpu.dtb.data_accesses                 401230                       # DTB accesses
-drivesys.cpu.itb.fetch_hits                   4197628                       # ITB hits
-drivesys.cpu.itb.fetch_misses                     194                       # ITB misses
-drivesys.cpu.itb.fetch_acv                         22                       # ITB acv
-drivesys.cpu.itb.fetch_accesses               4197822                       # ITB accesses
-drivesys.cpu.itb.read_hits                          0                       # DTB read hits
-drivesys.cpu.itb.read_misses                        0                       # DTB read misses
-drivesys.cpu.itb.read_acv                           0                       # DTB read access violations
-drivesys.cpu.itb.read_accesses                      0                       # DTB read accesses
-drivesys.cpu.itb.write_hits                         0                       # DTB write hits
-drivesys.cpu.itb.write_misses                       0                       # DTB write misses
-drivesys.cpu.itb.write_acv                          0                       # DTB write access violations
-drivesys.cpu.itb.write_accesses                     0                       # DTB write accesses
-drivesys.cpu.itb.data_hits                          0                       # DTB hits
-drivesys.cpu.itb.data_misses                        0                       # DTB misses
-drivesys.cpu.itb.data_acv                           0                       # DTB access violations
-drivesys.cpu.itb.data_accesses                      0                       # DTB accesses
-drivesys.cpu.numCycles                      801651324                       # number of cpu cycles simulated
-drivesys.cpu.numWorkItemsStarted                    0                       # number of work items this cpu started
-drivesys.cpu.numWorkItemsCompleted                  0                       # number of work items this cpu completed
-drivesys.cpu.committedInsts                  19050784                       # Number of instructions committed
-drivesys.cpu.committedOps                    19050784                       # Number of ops (including micro ops) committed
-drivesys.cpu.num_int_alu_accesses            17740632                       # Number of integer alu accesses
-drivesys.cpu.num_fp_alu_accesses                 1412                       # Number of float alu accesses
-drivesys.cpu.num_func_calls                   1265024                       # number of times a function call or return occured
-drivesys.cpu.num_conditional_control_insts      1264985                       # number of instructions that are conditional controls
-drivesys.cpu.num_int_insts                   17740632                       # number of integer instructions
-drivesys.cpu.num_fp_insts                        1412                       # number of float instructions
-drivesys.cpu.num_int_register_reads          23072330                       # number of times the integer registers were read
-drivesys.cpu.num_int_register_writes         13981107                       # number of times the integer registers were written
-drivesys.cpu.num_fp_register_reads                760                       # number of times the floating registers were read
-drivesys.cpu.num_fp_register_writes               766                       # number of times the floating registers were written
-drivesys.cpu.num_mem_refs                     5830788                       # number of memory refs
-drivesys.cpu.num_load_insts                   3746196                       # Number of load instructions
-drivesys.cpu.num_store_insts                  2084592                       # Number of store instructions
-drivesys.cpu.num_idle_cycles             782619252.927065                       # Number of idle cycles
-drivesys.cpu.num_busy_cycles             19032071.072935                       # Number of busy cycles
-drivesys.cpu.not_idle_fraction               0.023741                       # Percentage of non-idle cycles
-drivesys.cpu.idle_fraction                   0.976259                       # Percentage of idle cycles
-drivesys.cpu.Branches                         2793313                       # Number of branches fetched
-drivesys.cpu.op_class::No_OpClass              623554      3.27%      3.27% # Class of executed instruction
-drivesys.cpu.op_class::IntAlu                11538627     60.57%     63.84% # Class of executed instruction
-drivesys.cpu.op_class::IntMult                  20663      0.11%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::IntDiv                       0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::FloatAdd                   141      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::FloatCmp                     0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::FloatCvt                     0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::FloatMult                    0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::FloatDiv                    23      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::FloatSqrt                    0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdAdd                      0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdAddAcc                   0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdAlu                      0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdCmp                      0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdCvt                      0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdMisc                     0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdMult                     0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdMultAcc                  0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdShift                    0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdShiftAcc                 0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdSqrt                     0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatAdd                 0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatAlu                 0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatCmp                 0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatCvt                 0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatDiv                 0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatMisc                0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatMult                0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatMultAcc             0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatSqrt                0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::MemRead                4026028     21.13%     85.08% # Class of executed instruction
-drivesys.cpu.op_class::MemWrite               2085021     10.94%     96.02% # Class of executed instruction
-drivesys.cpu.op_class::IprAccess               757336      3.98%    100.00% # Class of executed instruction
-drivesys.cpu.op_class::InstPrefetch                 0      0.00%    100.00% # Class of executed instruction
-drivesys.cpu.op_class::total                 19051393                       # Class of executed instruction
-drivesys.cpu.kern.inst.arm                          0                       # number of arm instructions executed
-drivesys.cpu.kern.inst.quiesce                  19876                       # number of quiesce instructions executed
-drivesys.cpu.kern.inst.hwrei                   143591                       # number of hwrei instructions executed
-drivesys.cpu.kern.ipl_count::0                  60359     42.42%     42.42% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::21                 19727     13.86%     56.28% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::22                   205      0.14%     56.42% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::31                 62011     43.58%    100.00% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::total             142302                       # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_good::0                   60359     42.91%     42.91% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::21                  19727     14.03%     56.94% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::22                    205      0.15%     57.09% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::31                  60360     42.91%    100.00% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::total              140651                       # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_ticks::0           197399332500     98.50%     98.50% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::21             798910750      0.40%     98.90% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::22               4407500      0.00%     98.90% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::31            2205211250      1.10%    100.00% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::total       200407862000                       # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_used::0                       1                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::21                      1                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::22                      1                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::31               0.973376                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::total            0.988398                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.syscall::2                        1      4.55%      4.55% # number of syscalls executed
-drivesys.cpu.kern.syscall::6                        3     13.64%     18.18% # number of syscalls executed
-drivesys.cpu.kern.syscall::17                       2      9.09%     27.27% # number of syscalls executed
-drivesys.cpu.kern.syscall::97                       1      4.55%     31.82% # number of syscalls executed
-drivesys.cpu.kern.syscall::99                       2      9.09%     40.91% # number of syscalls executed
-drivesys.cpu.kern.syscall::101                      2      9.09%     50.00% # number of syscalls executed
-drivesys.cpu.kern.syscall::102                      3     13.64%     63.64% # number of syscalls executed
-drivesys.cpu.kern.syscall::104                      1      4.55%     68.18% # number of syscalls executed
-drivesys.cpu.kern.syscall::105                      3     13.64%     81.82% # number of syscalls executed
-drivesys.cpu.kern.syscall::106                      1      4.55%     86.36% # number of syscalls executed
-drivesys.cpu.kern.syscall::118                      2      9.09%     95.45% # number of syscalls executed
-drivesys.cpu.kern.syscall::150                      1      4.55%    100.00% # number of syscalls executed
-drivesys.cpu.kern.syscall::total                   22                       # number of syscalls executed
-drivesys.cpu.kern.callpal::swpctx                  72      0.06%      0.06% # number of callpals executed
-drivesys.cpu.kern.callpal::tbi                      5      0.00%      0.06% # number of callpals executed
-drivesys.cpu.kern.callpal::swpipl              102333     83.31%     83.37% # number of callpals executed
-drivesys.cpu.kern.callpal::rdps                   354      0.29%     83.66% # number of callpals executed
-drivesys.cpu.kern.callpal::rdusp                    1      0.00%     83.66% # number of callpals executed
-drivesys.cpu.kern.callpal::rti                  20038     16.31%     99.97% # number of callpals executed
-drivesys.cpu.kern.callpal::callsys                 25      0.02%     99.99% # number of callpals executed
-drivesys.cpu.kern.callpal::imb                      7      0.01%    100.00% # number of callpals executed
-drivesys.cpu.kern.callpal::total               122835                       # number of callpals executed
-drivesys.cpu.kern.mode_switch::kernel             214                       # number of protection mode switches
-drivesys.cpu.kern.mode_switch::user               140                       # number of protection mode switches
-drivesys.cpu.kern.mode_switch::idle             19896                       # number of protection mode switches
-drivesys.cpu.kern.mode_good::kernel               144                      
-drivesys.cpu.kern.mode_good::user                 140                      
-drivesys.cpu.kern.mode_good::idle                   4                      
-drivesys.cpu.kern.mode_switch_good::kernel     0.672897                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::user            1                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::idle     0.000201                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::total     0.014222                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_ticks::kernel         78134250      2.63%      2.63% # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks::user          319668250     10.78%     13.41% # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks::idle         2567942000     86.59%    100.00% # number of ticks spent at the given mode
-drivesys.cpu.kern.swap_context                     72                       # number of times the context was actually changed
-drivesys.tsunami.ethernet.clk_domain.clock         2000                       # Clock period in ticks
-drivesys.tsunami.ethernet.txBytes                 798                       # Bytes Transmitted
-drivesys.tsunami.ethernet.rxBytes                 960                       # Bytes Received
-drivesys.tsunami.ethernet.txPackets                 5                       # Number of Packets Transmitted
-drivesys.tsunami.ethernet.rxPackets                 8                       # Number of Packets Received
-drivesys.tsunami.ethernet.txIpChecksums             2                       # Number of tx IP Checksums done by device
-drivesys.tsunami.ethernet.rxIpChecksums             8                       # Number of rx IP Checksums done by device
-drivesys.tsunami.ethernet.txTcpChecksums            2                       # Number of tx TCP Checksums done by device
-drivesys.tsunami.ethernet.rxTcpChecksums            8                       # Number of rx TCP Checksums done by device
-drivesys.tsunami.ethernet.txUdpChecksums            0                       # Number of tx UDP Checksums done by device
-drivesys.tsunami.ethernet.rxUdpChecksums            0                       # Number of rx UDP Checksums done by device
-drivesys.tsunami.ethernet.descDMAReads        2385810                       # Number of descriptors the device read w/ DMA
-drivesys.tsunami.ethernet.descDMAWrites            13                       # Number of descriptors the device wrote w/ DMA
-drivesys.tsunami.ethernet.descDmaReadBytes     57259440                       # number of descriptor bytes read w/ DMA
-drivesys.tsunami.ethernet.descDmaWriteBytes          104                       # number of descriptor bytes write w/ DMA
-drivesys.tsunami.ethernet.totBandwidth          70176                       # Total Bandwidth (bits/s)
-drivesys.tsunami.ethernet.totPackets               13                       # Total Packets
-drivesys.tsunami.ethernet.totBytes               1758                       # Total Bytes
-drivesys.tsunami.ethernet.totPPS                   65                       # Total Tranmission Rate (packets/s)
-drivesys.tsunami.ethernet.txBandwidth           31855                       # Transmit Bandwidth (bits/s)
-drivesys.tsunami.ethernet.rxBandwidth           38322                       # Receive Bandwidth (bits/s)
-drivesys.tsunami.ethernet.txPPS                    25                       # Packet Tranmission Rate (packets/s)
-drivesys.tsunami.ethernet.rxPPS                    40                       # Packet Reception Rate (packets/s)
-drivesys.tsunami.ethernet.postedSwi                 0                       # number of software interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedSwi              0                       # average number of Swi's coalesced into each post
-drivesys.tsunami.ethernet.totalSwi                  0                       # total number of Swi written to ISR
-drivesys.tsunami.ethernet.postedRxIdle              0                       # number of rxIdle interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-drivesys.tsunami.ethernet.totalRxIdle               0                       # total number of RxIdle written to ISR
-drivesys.tsunami.ethernet.postedRxOk                0                       # number of RxOk interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedRxOk             0                       # average number of RxOk's coalesced into each post
-drivesys.tsunami.ethernet.totalRxOk                 0                       # total number of RxOk written to ISR
-drivesys.tsunami.ethernet.postedRxDesc              8                       # number of RxDesc interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-drivesys.tsunami.ethernet.totalRxDesc               8                       # total number of RxDesc written to ISR
-drivesys.tsunami.ethernet.postedTxOk                0                       # number of TxOk interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedTxOk             0                       # average number of TxOk's coalesced into each post
-drivesys.tsunami.ethernet.totalTxOk                 0                       # total number of TxOk written to ISR
-drivesys.tsunami.ethernet.postedTxIdle          19726                       # number of TxIdle interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedTxIdle            1                       # average number of TxIdle's coalesced into each post
-drivesys.tsunami.ethernet.totalTxIdle         2385810                       # total number of TxIdle written to ISR
-drivesys.tsunami.ethernet.postedTxDesc              0                       # number of TxDesc interrupts posted to CPU
-drivesys.tsunami.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-drivesys.tsunami.ethernet.totalTxDesc               0                       # total number of TxDesc written to ISR
-drivesys.tsunami.ethernet.postedRxOrn               0                       # number of RxOrn posted to CPU
-drivesys.tsunami.ethernet.coalescedRxOrn            0                       # average number of RxOrn's coalesced into each post
-drivesys.tsunami.ethernet.totalRxOrn                0                       # total number of RxOrn written to ISR
-drivesys.tsunami.ethernet.coalescedTotal            1                       # average number of interrupts coalesced into each post
-drivesys.tsunami.ethernet.postedInterrupts      2385831                       # number of posts to CPU
-drivesys.tsunami.ethernet.droppedPackets            0                       # number of packets dropped
-drivesys.iobus.trans_dist::ReadReq            2484469                       # Transaction distribution
-drivesys.iobus.trans_dist::ReadResp           2484469                       # Transaction distribution
-drivesys.iobus.trans_dist::WriteReq             39723                       # Transaction distribution
-drivesys.iobus.trans_dist::WriteResp            39723                       # Transaction distribution
-drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.cchip.pio       197670                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.ethernet.pio        78962                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.bridge.master::total       276632                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave      4771752                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::total      4771752                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count::total               5048384                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.cchip.pio       790680                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.ethernet.pio       157924                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.bridge.master::total       948604                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave     57261614                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total     57261614                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size::total               58210218                       # Cumulative packet size per connected master and slave (bytes)
 
 ---------- End Simulation Statistics   ----------
 
@@ -619,267 +619,13 @@
 sim_ticks                                   407341500                       # Number of ticks simulated
 final_tick                               4321620817500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                             7893991697                       # Simulator instruction rate (inst/s)
-host_op_rate                               7892445581                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6135954870                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 534848                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                             5226750004                       # Simulator instruction rate (inst/s)
+host_op_rate                               5225740576                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4062718512                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 533084                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                   523853183                       # Number of instructions simulated
 sim_ops                                     523853183                       # Number of ops (including micro ops) simulated
-testsys.voltage_domain.voltage                      1                       # Voltage in Volts
-testsys.clk_domain.clock                         1000                       # Clock period in ticks
-testsys.physmem.bytes_read::cpu.inst           144504                       # Number of bytes read from this memory
-testsys.physmem.bytes_read::cpu.data            49936                       # Number of bytes read from this memory
-testsys.physmem.bytes_read::tsunami.ethernet       116376                       # Number of bytes read from this memory
-testsys.physmem.bytes_read::total              310816                       # Number of bytes read from this memory
-testsys.physmem.bytes_inst_read::cpu.inst       144504                       # Number of instructions bytes read from this memory
-testsys.physmem.bytes_inst_read::total         144504                       # Number of instructions bytes read from this memory
-testsys.physmem.bytes_written::cpu.data         27704                       # Number of bytes written to this memory
-testsys.physmem.bytes_written::total            27704                       # Number of bytes written to this memory
-testsys.physmem.num_reads::cpu.inst             36126                       # Number of read requests responded to by this memory
-testsys.physmem.num_reads::cpu.data              6905                       # Number of read requests responded to by this memory
-testsys.physmem.num_reads::tsunami.ethernet         4849                       # Number of read requests responded to by this memory
-testsys.physmem.num_reads::total                47880                       # Number of read requests responded to by this memory
-testsys.physmem.num_writes::cpu.data             3814                       # Number of write requests responded to by this memory
-testsys.physmem.num_writes::total                3814                       # Number of write requests responded to by this memory
-testsys.physmem.bw_read::cpu.inst           354749025                       # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::cpu.data           122590014                       # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::tsunami.ethernet    285696400                       # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::total              763035438                       # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::cpu.inst      354749025                       # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::total         354749025                       # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::cpu.data           68011730                       # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::total              68011730                       # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.inst          354749025                       # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.data          190601743                       # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::tsunami.ethernet    285696400                       # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::total             831047168                       # Total bandwidth to/from this memory (bytes/s)
-testsys.membus.trans_dist::ReadReq              47876                       # Transaction distribution
-testsys.membus.trans_dist::ReadResp             48080                       # Transaction distribution
-testsys.membus.trans_dist::WriteReq              3691                       # Transaction distribution
-testsys.membus.trans_dist::WriteResp             3691                       # Transaction distribution
-testsys.membus.trans_dist::LoadLockedReq          204                       # Transaction distribution
-testsys.membus.trans_dist::StoreCondReq           204                       # Transaction distribution
-testsys.membus.trans_dist::StoreCondResp          204                       # Transaction distribution
-testsys.membus.pkt_count_testsys.cpu.icache_port::testsys.physmem.port        72252                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.icache_port::total        72252                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.bridge.slave          562                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.physmem.port        21438                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.cpu.dcache_port::total        22000                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.iobridge.master::testsys.physmem.port         9698                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count_testsys.iobridge.master::total         9698                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_count::total                103950                       # Packet count per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.icache_port::testsys.physmem.port       144504                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.icache_port::total       144504                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.bridge.slave         1928                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.physmem.port        77640                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.cpu.dcache_port::total        79568                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port       116376                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size_testsys.iobridge.master::total       116376                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.pkt_size::total                 340448                       # Cumulative packet size per connected master and slave (bytes)
-testsys.membus.snoops                               0                       # Total snoops (count)
-testsys.membus.snoop_fanout::samples            51694                       # Request fanout histogram
-testsys.membus.snoop_fanout::mean            0.792645                       # Request fanout histogram
-testsys.membus.snoop_fanout::stdev           0.405416                       # Request fanout histogram
-testsys.membus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-testsys.membus.snoop_fanout::0                  10719     20.74%     20.74% # Request fanout histogram
-testsys.membus.snoop_fanout::1                  40975     79.26%    100.00% # Request fanout histogram
-testsys.membus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-testsys.membus.snoop_fanout::min_value              0                       # Request fanout histogram
-testsys.membus.snoop_fanout::max_value              1                       # Request fanout histogram
-testsys.membus.snoop_fanout::total              51694                       # Request fanout histogram
-testsys.disk0.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
-testsys.disk0.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk0.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
-testsys.disk0.dma_write_full_pages                  0                       # Number of full page size DMA writes.
-testsys.disk0.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
-testsys.disk0.dma_write_txs                         0                       # Number of DMA write transactions.
-testsys.disk2.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
-testsys.disk2.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk2.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
-testsys.disk2.dma_write_full_pages                  0                       # Number of full page size DMA writes.
-testsys.disk2.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
-testsys.disk2.dma_write_txs                         0                       # Number of DMA write transactions.
-testsys.cpu.clk_domain.clock                      500                       # Clock period in ticks
-testsys.cpu.dtb.fetch_hits                          0                       # ITB hits
-testsys.cpu.dtb.fetch_misses                        0                       # ITB misses
-testsys.cpu.dtb.fetch_acv                           0                       # ITB acv
-testsys.cpu.dtb.fetch_accesses                      0                       # ITB accesses
-testsys.cpu.dtb.read_hits                        7065                       # DTB read hits
-testsys.cpu.dtb.read_misses                         0                       # DTB read misses
-testsys.cpu.dtb.read_acv                            0                       # DTB read access violations
-testsys.cpu.dtb.read_accesses                       0                       # DTB read accesses
-testsys.cpu.dtb.write_hits                       3935                       # DTB write hits
-testsys.cpu.dtb.write_misses                        0                       # DTB write misses
-testsys.cpu.dtb.write_acv                           0                       # DTB write access violations
-testsys.cpu.dtb.write_accesses                      0                       # DTB write accesses
-testsys.cpu.dtb.data_hits                       11000                       # DTB hits
-testsys.cpu.dtb.data_misses                         0                       # DTB misses
-testsys.cpu.dtb.data_acv                            0                       # DTB access violations
-testsys.cpu.dtb.data_accesses                       0                       # DTB accesses
-testsys.cpu.itb.fetch_hits                       5992                       # ITB hits
-testsys.cpu.itb.fetch_misses                        0                       # ITB misses
-testsys.cpu.itb.fetch_acv                           0                       # ITB acv
-testsys.cpu.itb.fetch_accesses                   5992                       # ITB accesses
-testsys.cpu.itb.read_hits                           0                       # DTB read hits
-testsys.cpu.itb.read_misses                         0                       # DTB read misses
-testsys.cpu.itb.read_acv                            0                       # DTB read access violations
-testsys.cpu.itb.read_accesses                       0                       # DTB read accesses
-testsys.cpu.itb.write_hits                          0                       # DTB write hits
-testsys.cpu.itb.write_misses                        0                       # DTB write misses
-testsys.cpu.itb.write_acv                           0                       # DTB write access violations
-testsys.cpu.itb.write_accesses                      0                       # DTB write accesses
-testsys.cpu.itb.data_hits                           0                       # DTB hits
-testsys.cpu.itb.data_misses                         0                       # DTB misses
-testsys.cpu.itb.data_acv                            0                       # DTB access violations
-testsys.cpu.itb.data_accesses                       0                       # DTB accesses
-testsys.cpu.numCycles                          821056                       # number of cpu cycles simulated
-testsys.cpu.numWorkItemsStarted                     0                       # number of work items this cpu started
-testsys.cpu.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-testsys.cpu.committedInsts                      36126                       # Number of instructions committed
-testsys.cpu.committedOps                        36126                       # Number of ops (including micro ops) committed
-testsys.cpu.num_int_alu_accesses                33492                       # Number of integer alu accesses
-testsys.cpu.num_fp_alu_accesses                     0                       # Number of float alu accesses
-testsys.cpu.num_func_calls                       2384                       # number of times a function call or return occured
-testsys.cpu.num_conditional_control_insts         2346                       # number of instructions that are conditional controls
-testsys.cpu.num_int_insts                       33492                       # number of integer instructions
-testsys.cpu.num_fp_insts                            0                       # number of float instructions
-testsys.cpu.num_int_register_reads              43747                       # number of times the integer registers were read
-testsys.cpu.num_int_register_writes             26476                       # number of times the integer registers were written
-testsys.cpu.num_fp_register_reads                   0                       # number of times the floating registers were read
-testsys.cpu.num_fp_register_writes                  0                       # number of times the floating registers were written
-testsys.cpu.num_mem_refs                        11041                       # number of memory refs
-testsys.cpu.num_load_insts                       7105                       # Number of load instructions
-testsys.cpu.num_store_insts                      3936                       # Number of store instructions
-testsys.cpu.num_idle_cycles              784687.711054                       # Number of idle cycles
-testsys.cpu.num_busy_cycles              36368.288946                       # Number of busy cycles
-testsys.cpu.not_idle_fraction                0.044295                       # Percentage of non-idle cycles
-testsys.cpu.idle_fraction                    0.955705                       # Percentage of idle cycles
-testsys.cpu.Branches                             5238                       # Number of branches fetched
-testsys.cpu.op_class::No_OpClass                 1261      3.49%      3.49% # Class of executed instruction
-testsys.cpu.op_class::IntAlu                    21664     59.97%     63.46% # Class of executed instruction
-testsys.cpu.op_class::IntMult                      44      0.12%     63.58% # Class of executed instruction
-testsys.cpu.op_class::IntDiv                        0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatAdd                      0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatCmp                      0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatCvt                      0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatMult                     0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatDiv                      0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatSqrt                     0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdAdd                       0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdAddAcc                    0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdAlu                       0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdCmp                       0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdCvt                       0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdMisc                      0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdMult                      0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdMultAcc                   0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdShift                     0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdShiftAcc                  0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdSqrt                      0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatAdd                  0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatAlu                  0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatCmp                  0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatCvt                  0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatDiv                  0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatMisc                 0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatMult                 0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatMultAcc              0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatSqrt                 0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::MemRead                    7674     21.24%     84.82% # Class of executed instruction
-testsys.cpu.op_class::MemWrite                   3938     10.90%     95.72% # Class of executed instruction
-testsys.cpu.op_class::IprAccess                  1545      4.28%    100.00% # Class of executed instruction
-testsys.cpu.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-testsys.cpu.op_class::total                     36126                       # Class of executed instruction
-testsys.cpu.kern.inst.arm                           0                       # number of arm instructions executed
-testsys.cpu.kern.inst.quiesce                      40                       # number of quiesce instructions executed
-testsys.cpu.kern.inst.hwrei                       295                       # number of hwrei instructions executed
-testsys.cpu.kern.ipl_count::0                     123     41.84%     41.84% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::21                     40     13.61%     55.44% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::22                      1      0.34%     55.78% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::31                    130     44.22%    100.00% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::total                 294                       # number of times we switched to this ipl
-testsys.cpu.kern.ipl_good::0                      123     42.86%     42.86% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::21                      40     13.94%     56.79% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::22                       1      0.35%     57.14% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::31                     123     42.86%    100.00% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::total                  287                       # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_ticks::0               397967000     96.95%     96.95% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::21                3240000      0.79%     97.73% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::22                  43000      0.01%     97.74% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::31                9258000      2.26%    100.00% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::total           410508000                       # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_used::0                        1                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::31                0.946154                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::total             0.976190                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.callpal::swpipl                  212     83.46%     83.46% # number of callpals executed
-testsys.cpu.kern.callpal::rdps                      1      0.39%     83.86% # number of callpals executed
-testsys.cpu.kern.callpal::rti                      41     16.14%    100.00% # number of callpals executed
-testsys.cpu.kern.callpal::total                   254                       # number of callpals executed
-testsys.cpu.kern.mode_switch::kernel                0                       # number of protection mode switches
-testsys.cpu.kern.mode_switch::user                  0                       # number of protection mode switches
-testsys.cpu.kern.mode_switch::idle                 41                       # number of protection mode switches
-testsys.cpu.kern.mode_good::kernel                  0                      
-testsys.cpu.kern.mode_good::user                    0                      
-testsys.cpu.kern.mode_good::idle                    0                      
-testsys.cpu.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::user           nan                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::idle             0                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::total            0                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_ticks::kernel                 0                       # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
-testsys.cpu.kern.swap_context                       0                       # number of times the context was actually changed
-testsys.tsunami.ethernet.clk_domain.clock         2000                       # Clock period in ticks
-testsys.tsunami.ethernet.descDMAReads            4849                       # Number of descriptors the device read w/ DMA
-testsys.tsunami.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
-testsys.tsunami.ethernet.descDmaReadBytes       116376                       # number of descriptor bytes read w/ DMA
-testsys.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-testsys.tsunami.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
-testsys.tsunami.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-testsys.tsunami.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-testsys.tsunami.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
-testsys.tsunami.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
-testsys.tsunami.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-testsys.tsunami.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-testsys.tsunami.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
-testsys.tsunami.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
-testsys.tsunami.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
-testsys.tsunami.ethernet.postedTxIdle              40                       # number of TxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxIdle            1                       # average number of TxIdle's coalesced into each post
-testsys.tsunami.ethernet.totalTxIdle             4849                       # total number of TxIdle written to ISR
-testsys.tsunami.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-testsys.tsunami.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-testsys.tsunami.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
-testsys.tsunami.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
-testsys.tsunami.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-testsys.tsunami.ethernet.coalescedTotal             1                       # average number of interrupts coalesced into each post
-testsys.tsunami.ethernet.postedInterrupts         4849                       # number of posts to CPU
-testsys.tsunami.ethernet.droppedPackets             0                       # number of packets dropped
-testsys.iobus.trans_dist::ReadReq                5049                       # Transaction distribution
-testsys.iobus.trans_dist::ReadResp               5049                       # Transaction distribution
-testsys.iobus.trans_dist::WriteReq                 81                       # Transaction distribution
-testsys.iobus.trans_dist::WriteResp                81                       # Transaction distribution
-testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.cchip.pio          402                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.ethernet.pio          160                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.bridge.master::total          562                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::testsys.iobridge.slave         9698                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::total         9698                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_count::total                  10260                       # Packet count per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.cchip.pio         1608                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.ethernet.pio          320                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.bridge.master::total         1928                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave       116376                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total       116376                       # Cumulative packet size per connected master and slave (bytes)
-testsys.iobus.pkt_size::total                  118304                       # Cumulative packet size per connected master and slave (bytes)
 drivesys.voltage_domain.voltage                     1                       # Voltage in Volts
 drivesys.clk_domain.clock                        1000                       # Clock period in ticks
 drivesys.physmem.bytes_read::cpu.inst          144608                       # Number of bytes read from this memory
@@ -908,52 +654,6 @@
 drivesys.physmem.bw_total::cpu.data         190601743                       # Total bandwidth to/from this memory (bytes/s)
 drivesys.physmem.bw_total::tsunami.ethernet    285755318                       # Total bandwidth to/from this memory (bytes/s)
 drivesys.physmem.bw_total::total            831361401                       # Total bandwidth to/from this memory (bytes/s)
-drivesys.membus.trans_dist::ReadReq             47907                       # Transaction distribution
-drivesys.membus.trans_dist::ReadResp            48111                       # Transaction distribution
-drivesys.membus.trans_dist::WriteReq             3689                       # Transaction distribution
-drivesys.membus.trans_dist::WriteResp            3689                       # Transaction distribution
-drivesys.membus.trans_dist::LoadLockedReq          204                       # Transaction distribution
-drivesys.membus.trans_dist::StoreCondReq          204                       # Transaction distribution
-drivesys.membus.trans_dist::StoreCondResp          204                       # Transaction distribution
-drivesys.membus.pkt_count_drivesys.cpu.icache_port::drivesys.physmem.port        72304                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.icache_port::total        72304                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.bridge.slave          562                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.physmem.port        21442                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.cpu.dcache_port::total        22004                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.iobridge.master::drivesys.physmem.port         9700                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count_drivesys.iobridge.master::total         9700                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_count::total               104008                       # Packet count per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.icache_port::drivesys.physmem.port       144608                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.icache_port::total       144608                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.bridge.slave         1928                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.physmem.port        77640                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.cpu.dcache_port::total        79568                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port       116400                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size_drivesys.iobridge.master::total       116400                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.pkt_size::total                340576                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.membus.snoops                              0                       # Total snoops (count)
-drivesys.membus.snoop_fanout::samples           51723                       # Request fanout histogram
-drivesys.membus.snoop_fanout::mean           0.792723                       # Request fanout histogram
-drivesys.membus.snoop_fanout::stdev          0.405360                       # Request fanout histogram
-drivesys.membus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-drivesys.membus.snoop_fanout::0                 10721     20.73%     20.73% # Request fanout histogram
-drivesys.membus.snoop_fanout::1                 41002     79.27%    100.00% # Request fanout histogram
-drivesys.membus.snoop_fanout::overflows             0      0.00%    100.00% # Request fanout histogram
-drivesys.membus.snoop_fanout::min_value             0                       # Request fanout histogram
-drivesys.membus.snoop_fanout::max_value             1                       # Request fanout histogram
-drivesys.membus.snoop_fanout::total             51723                       # Request fanout histogram
-drivesys.disk0.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
-drivesys.disk0.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
-drivesys.disk0.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
-drivesys.disk0.dma_write_full_pages                 0                       # Number of full page size DMA writes.
-drivesys.disk0.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
-drivesys.disk0.dma_write_txs                        0                       # Number of DMA write transactions.
-drivesys.disk2.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
-drivesys.disk2.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
-drivesys.disk2.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
-drivesys.disk2.dma_write_full_pages                 0                       # Number of full page size DMA writes.
-drivesys.disk2.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
-drivesys.disk2.dma_write_txs                        0                       # Number of DMA write transactions.
 drivesys.cpu.clk_domain.clock                     250                       # Clock period in ticks
 drivesys.cpu.dtb.fetch_hits                         0                       # ITB hits
 drivesys.cpu.dtb.fetch_misses                       0                       # ITB misses
@@ -1086,6 +786,68 @@
 drivesys.cpu.kern.mode_ticks::user                  0                       # number of ticks spent at the given mode
 drivesys.cpu.kern.mode_ticks::idle                  0                       # number of ticks spent at the given mode
 drivesys.cpu.kern.swap_context                      0                       # number of times the context was actually changed
+drivesys.disk0.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
+drivesys.disk0.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
+drivesys.disk0.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
+drivesys.disk0.dma_write_full_pages                 0                       # Number of full page size DMA writes.
+drivesys.disk0.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
+drivesys.disk0.dma_write_txs                        0                       # Number of DMA write transactions.
+drivesys.disk2.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
+drivesys.disk2.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
+drivesys.disk2.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
+drivesys.disk2.dma_write_full_pages                 0                       # Number of full page size DMA writes.
+drivesys.disk2.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
+drivesys.disk2.dma_write_txs                        0                       # Number of DMA write transactions.
+drivesys.iobus.trans_dist::ReadReq               5050                       # Transaction distribution
+drivesys.iobus.trans_dist::ReadResp              5050                       # Transaction distribution
+drivesys.iobus.trans_dist::WriteReq                81                       # Transaction distribution
+drivesys.iobus.trans_dist::WriteResp               81                       # Transaction distribution
+drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.cchip.pio          402                       # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.ethernet.pio          160                       # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.bridge.master::total          562                       # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave         9700                       # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::total         9700                       # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_count::total                 10262                       # Packet count per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.cchip.pio         1608                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.ethernet.pio          320                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.bridge.master::total         1928                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave       116400                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total       116400                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.iobus.pkt_size::total                 118328                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.trans_dist::ReadReq             47907                       # Transaction distribution
+drivesys.membus.trans_dist::ReadResp            48111                       # Transaction distribution
+drivesys.membus.trans_dist::WriteReq             3689                       # Transaction distribution
+drivesys.membus.trans_dist::WriteResp            3689                       # Transaction distribution
+drivesys.membus.trans_dist::LoadLockedReq          204                       # Transaction distribution
+drivesys.membus.trans_dist::StoreCondReq          204                       # Transaction distribution
+drivesys.membus.trans_dist::StoreCondResp          204                       # Transaction distribution
+drivesys.membus.pkt_count_drivesys.cpu.icache_port::drivesys.physmem.port        72304                       # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.icache_port::total        72304                       # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.bridge.slave          562                       # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.physmem.port        21442                       # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.cpu.dcache_port::total        22004                       # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.iobridge.master::drivesys.physmem.port         9700                       # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count_drivesys.iobridge.master::total         9700                       # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_count::total               104008                       # Packet count per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.icache_port::drivesys.physmem.port       144608                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.icache_port::total       144608                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.bridge.slave         1928                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.physmem.port        77640                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.cpu.dcache_port::total        79568                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port       116400                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size_drivesys.iobridge.master::total       116400                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pkt_size::total                340576                       # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.snoops                              0                       # Total snoops (count)
+drivesys.membus.snoop_fanout::samples           51723                       # Request fanout histogram
+drivesys.membus.snoop_fanout::mean           0.792723                       # Request fanout histogram
+drivesys.membus.snoop_fanout::stdev          0.405360                       # Request fanout histogram
+drivesys.membus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+drivesys.membus.snoop_fanout::0                 10721     20.73%     20.73% # Request fanout histogram
+drivesys.membus.snoop_fanout::1                 41002     79.27%    100.00% # Request fanout histogram
+drivesys.membus.snoop_fanout::overflows             0      0.00%    100.00% # Request fanout histogram
+drivesys.membus.snoop_fanout::min_value             0                       # Request fanout histogram
+drivesys.membus.snoop_fanout::max_value             1                       # Request fanout histogram
+drivesys.membus.snoop_fanout::total             51723                       # Request fanout histogram
 drivesys.tsunami.ethernet.clk_domain.clock         2000                       # Clock period in ticks
 drivesys.tsunami.ethernet.descDMAReads           4850                       # Number of descriptors the device read w/ DMA
 drivesys.tsunami.ethernet.descDMAWrites             0                       # Number of descriptors the device wrote w/ DMA
@@ -1118,21 +880,259 @@
 drivesys.tsunami.ethernet.coalescedTotal            1                       # average number of interrupts coalesced into each post
 drivesys.tsunami.ethernet.postedInterrupts         4850                       # number of posts to CPU
 drivesys.tsunami.ethernet.droppedPackets            0                       # number of packets dropped
-drivesys.iobus.trans_dist::ReadReq               5050                       # Transaction distribution
-drivesys.iobus.trans_dist::ReadResp              5050                       # Transaction distribution
-drivesys.iobus.trans_dist::WriteReq                81                       # Transaction distribution
-drivesys.iobus.trans_dist::WriteResp               81                       # Transaction distribution
-drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.cchip.pio          402                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.ethernet.pio          160                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.bridge.master::total          562                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave         9700                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::total         9700                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_count::total                 10262                       # Packet count per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.cchip.pio         1608                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.ethernet.pio          320                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.bridge.master::total         1928                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave       116400                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total       116400                       # Cumulative packet size per connected master and slave (bytes)
-drivesys.iobus.pkt_size::total                 118328                       # Cumulative packet size per connected master and slave (bytes)
+testsys.voltage_domain.voltage                      1                       # Voltage in Volts
+testsys.clk_domain.clock                         1000                       # Clock period in ticks
+testsys.physmem.bytes_read::cpu.inst           144504                       # Number of bytes read from this memory
+testsys.physmem.bytes_read::cpu.data            49936                       # Number of bytes read from this memory
+testsys.physmem.bytes_read::tsunami.ethernet       116376                       # Number of bytes read from this memory
+testsys.physmem.bytes_read::total              310816                       # Number of bytes read from this memory
+testsys.physmem.bytes_inst_read::cpu.inst       144504                       # Number of instructions bytes read from this memory
+testsys.physmem.bytes_inst_read::total         144504                       # Number of instructions bytes read from this memory
+testsys.physmem.bytes_written::cpu.data         27704                       # Number of bytes written to this memory
+testsys.physmem.bytes_written::total            27704                       # Number of bytes written to this memory
+testsys.physmem.num_reads::cpu.inst             36126                       # Number of read requests responded to by this memory
+testsys.physmem.num_reads::cpu.data              6905                       # Number of read requests responded to by this memory
+testsys.physmem.num_reads::tsunami.ethernet         4849                       # Number of read requests responded to by this memory
+testsys.physmem.num_reads::total                47880                       # Number of read requests responded to by this memory
+testsys.physmem.num_writes::cpu.data             3814                       # Number of write requests responded to by this memory
+testsys.physmem.num_writes::total                3814                       # Number of write requests responded to by this memory
+testsys.physmem.bw_read::cpu.inst           354749025                       # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::cpu.data           122590014                       # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::tsunami.ethernet    285696400                       # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::total              763035438                       # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_inst_read::cpu.inst      354749025                       # Instruction read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_inst_read::total         354749025                       # Instruction read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_write::cpu.data           68011730                       # Write bandwidth from this memory (bytes/s)
+testsys.physmem.bw_write::total              68011730                       # Write bandwidth from this memory (bytes/s)
+testsys.physmem.bw_total::cpu.inst          354749025                       # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::cpu.data          190601743                       # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::tsunami.ethernet    285696400                       # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::total             831047168                       # Total bandwidth to/from this memory (bytes/s)
+testsys.cpu.clk_domain.clock                      500                       # Clock period in ticks
+testsys.cpu.dtb.fetch_hits                          0                       # ITB hits
+testsys.cpu.dtb.fetch_misses                        0                       # ITB misses
+testsys.cpu.dtb.fetch_acv                           0                       # ITB acv
+testsys.cpu.dtb.fetch_accesses                      0                       # ITB accesses
+testsys.cpu.dtb.read_hits                        7065                       # DTB read hits
+testsys.cpu.dtb.read_misses                         0                       # DTB read misses
+testsys.cpu.dtb.read_acv                            0                       # DTB read access violations
+testsys.cpu.dtb.read_accesses                       0                       # DTB read accesses
+testsys.cpu.dtb.write_hits                       3935                       # DTB write hits
+testsys.cpu.dtb.write_misses                        0                       # DTB write misses
+testsys.cpu.dtb.write_acv                           0                       # DTB write access violations
+testsys.cpu.dtb.write_accesses                      0                       # DTB write accesses
+testsys.cpu.dtb.data_hits                       11000                       # DTB hits
+testsys.cpu.dtb.data_misses                         0                       # DTB misses
+testsys.cpu.dtb.data_acv                            0                       # DTB access violations
+testsys.cpu.dtb.data_accesses                       0                       # DTB accesses
+testsys.cpu.itb.fetch_hits                       5992                       # ITB hits
+testsys.cpu.itb.fetch_misses                        0                       # ITB misses
+testsys.cpu.itb.fetch_acv                           0                       # ITB acv
+testsys.cpu.itb.fetch_accesses                   5992                       # ITB accesses
+testsys.cpu.itb.read_hits                           0                       # DTB read hits
+testsys.cpu.itb.read_misses                         0                       # DTB read misses
+testsys.cpu.itb.read_acv                            0                       # DTB read access violations
+testsys.cpu.itb.read_accesses                       0                       # DTB read accesses
+testsys.cpu.itb.write_hits                          0                       # DTB write hits
+testsys.cpu.itb.write_misses                        0                       # DTB write misses
+testsys.cpu.itb.write_acv                           0                       # DTB write access violations
+testsys.cpu.itb.write_accesses                      0                       # DTB write accesses
+testsys.cpu.itb.data_hits                           0                       # DTB hits
+testsys.cpu.itb.data_misses                         0                       # DTB misses
+testsys.cpu.itb.data_acv                            0                       # DTB access violations
+testsys.cpu.itb.data_accesses                       0                       # DTB accesses
+testsys.cpu.numCycles                          821056                       # number of cpu cycles simulated
+testsys.cpu.numWorkItemsStarted                     0                       # number of work items this cpu started
+testsys.cpu.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+testsys.cpu.committedInsts                      36126                       # Number of instructions committed
+testsys.cpu.committedOps                        36126                       # Number of ops (including micro ops) committed
+testsys.cpu.num_int_alu_accesses                33492                       # Number of integer alu accesses
+testsys.cpu.num_fp_alu_accesses                     0                       # Number of float alu accesses
+testsys.cpu.num_func_calls                       2384                       # number of times a function call or return occured
+testsys.cpu.num_conditional_control_insts         2346                       # number of instructions that are conditional controls
+testsys.cpu.num_int_insts                       33492                       # number of integer instructions
+testsys.cpu.num_fp_insts                            0                       # number of float instructions
+testsys.cpu.num_int_register_reads              43747                       # number of times the integer registers were read
+testsys.cpu.num_int_register_writes             26476                       # number of times the integer registers were written
+testsys.cpu.num_fp_register_reads                   0                       # number of times the floating registers were read
+testsys.cpu.num_fp_register_writes                  0                       # number of times the floating registers were written
+testsys.cpu.num_mem_refs                        11041                       # number of memory refs
+testsys.cpu.num_load_insts                       7105                       # Number of load instructions
+testsys.cpu.num_store_insts                      3936                       # Number of store instructions
+testsys.cpu.num_idle_cycles              784687.711054                       # Number of idle cycles
+testsys.cpu.num_busy_cycles              36368.288946                       # Number of busy cycles
+testsys.cpu.not_idle_fraction                0.044295                       # Percentage of non-idle cycles
+testsys.cpu.idle_fraction                    0.955705                       # Percentage of idle cycles
+testsys.cpu.Branches                             5238                       # Number of branches fetched
+testsys.cpu.op_class::No_OpClass                 1261      3.49%      3.49% # Class of executed instruction
+testsys.cpu.op_class::IntAlu                    21664     59.97%     63.46% # Class of executed instruction
+testsys.cpu.op_class::IntMult                      44      0.12%     63.58% # Class of executed instruction
+testsys.cpu.op_class::IntDiv                        0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::FloatAdd                      0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::FloatCmp                      0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::FloatCvt                      0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::FloatMult                     0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::FloatDiv                      0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::FloatSqrt                     0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdAdd                       0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdAddAcc                    0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdAlu                       0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdCmp                       0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdCvt                       0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdMisc                      0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdMult                      0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdMultAcc                   0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdShift                     0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdShiftAcc                  0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdSqrt                      0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatAdd                  0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatAlu                  0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatCmp                  0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatCvt                  0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatDiv                  0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatMisc                 0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatMult                 0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatMultAcc              0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatSqrt                 0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::MemRead                    7674     21.24%     84.82% # Class of executed instruction
+testsys.cpu.op_class::MemWrite                   3938     10.90%     95.72% # Class of executed instruction
+testsys.cpu.op_class::IprAccess                  1545      4.28%    100.00% # Class of executed instruction
+testsys.cpu.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+testsys.cpu.op_class::total                     36126                       # Class of executed instruction
+testsys.cpu.kern.inst.arm                           0                       # number of arm instructions executed
+testsys.cpu.kern.inst.quiesce                      40                       # number of quiesce instructions executed
+testsys.cpu.kern.inst.hwrei                       295                       # number of hwrei instructions executed
+testsys.cpu.kern.ipl_count::0                     123     41.84%     41.84% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::21                     40     13.61%     55.44% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::22                      1      0.34%     55.78% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::31                    130     44.22%    100.00% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::total                 294                       # number of times we switched to this ipl
+testsys.cpu.kern.ipl_good::0                      123     42.86%     42.86% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::21                      40     13.94%     56.79% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::22                       1      0.35%     57.14% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::31                     123     42.86%    100.00% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::total                  287                       # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_ticks::0               397967000     96.95%     96.95% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::21                3240000      0.79%     97.73% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::22                  43000      0.01%     97.74% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::31                9258000      2.26%    100.00% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::total           410508000                       # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_used::0                        1                       # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::31                0.946154                       # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::total             0.976190                       # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.callpal::swpipl                  212     83.46%     83.46% # number of callpals executed
+testsys.cpu.kern.callpal::rdps                      1      0.39%     83.86% # number of callpals executed
+testsys.cpu.kern.callpal::rti                      41     16.14%    100.00% # number of callpals executed
+testsys.cpu.kern.callpal::total                   254                       # number of callpals executed
+testsys.cpu.kern.mode_switch::kernel                0                       # number of protection mode switches
+testsys.cpu.kern.mode_switch::user                  0                       # number of protection mode switches
+testsys.cpu.kern.mode_switch::idle                 41                       # number of protection mode switches
+testsys.cpu.kern.mode_good::kernel                  0                      
+testsys.cpu.kern.mode_good::user                    0                      
+testsys.cpu.kern.mode_good::idle                    0                      
+testsys.cpu.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::user           nan                       # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::idle             0                       # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::total            0                       # fraction of useful protection mode switches
+testsys.cpu.kern.mode_ticks::kernel                 0                       # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
+testsys.cpu.kern.swap_context                       0                       # number of times the context was actually changed
+testsys.disk0.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
+testsys.disk0.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
+testsys.disk0.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
+testsys.disk0.dma_write_full_pages                  0                       # Number of full page size DMA writes.
+testsys.disk0.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
+testsys.disk0.dma_write_txs                         0                       # Number of DMA write transactions.
+testsys.disk2.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
+testsys.disk2.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
+testsys.disk2.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
+testsys.disk2.dma_write_full_pages                  0                       # Number of full page size DMA writes.
+testsys.disk2.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
+testsys.disk2.dma_write_txs                         0                       # Number of DMA write transactions.
+testsys.iobus.trans_dist::ReadReq                5049                       # Transaction distribution
+testsys.iobus.trans_dist::ReadResp               5049                       # Transaction distribution
+testsys.iobus.trans_dist::WriteReq                 81                       # Transaction distribution
+testsys.iobus.trans_dist::WriteResp                81                       # Transaction distribution
+testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.cchip.pio          402                       # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.ethernet.pio          160                       # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.bridge.master::total          562                       # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::testsys.iobridge.slave         9698                       # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::total         9698                       # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_count::total                  10260                       # Packet count per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.cchip.pio         1608                       # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.ethernet.pio          320                       # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.bridge.master::total         1928                       # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave       116376                       # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total       116376                       # Cumulative packet size per connected master and slave (bytes)
+testsys.iobus.pkt_size::total                  118304                       # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.trans_dist::ReadReq              47876                       # Transaction distribution
+testsys.membus.trans_dist::ReadResp             48080                       # Transaction distribution
+testsys.membus.trans_dist::WriteReq              3691                       # Transaction distribution
+testsys.membus.trans_dist::WriteResp             3691                       # Transaction distribution
+testsys.membus.trans_dist::LoadLockedReq          204                       # Transaction distribution
+testsys.membus.trans_dist::StoreCondReq           204                       # Transaction distribution
+testsys.membus.trans_dist::StoreCondResp          204                       # Transaction distribution
+testsys.membus.pkt_count_testsys.cpu.icache_port::testsys.physmem.port        72252                       # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.icache_port::total        72252                       # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.bridge.slave          562                       # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.physmem.port        21438                       # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.cpu.dcache_port::total        22000                       # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.iobridge.master::testsys.physmem.port         9698                       # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count_testsys.iobridge.master::total         9698                       # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_count::total                103950                       # Packet count per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.icache_port::testsys.physmem.port       144504                       # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.icache_port::total       144504                       # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.bridge.slave         1928                       # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.physmem.port        77640                       # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.cpu.dcache_port::total        79568                       # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port       116376                       # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size_testsys.iobridge.master::total       116376                       # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pkt_size::total                 340448                       # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.snoops                               0                       # Total snoops (count)
+testsys.membus.snoop_fanout::samples            51694                       # Request fanout histogram
+testsys.membus.snoop_fanout::mean            0.792645                       # Request fanout histogram
+testsys.membus.snoop_fanout::stdev           0.405416                       # Request fanout histogram
+testsys.membus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
+testsys.membus.snoop_fanout::0                  10719     20.74%     20.74% # Request fanout histogram
+testsys.membus.snoop_fanout::1                  40975     79.26%    100.00% # Request fanout histogram
+testsys.membus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
+testsys.membus.snoop_fanout::min_value              0                       # Request fanout histogram
+testsys.membus.snoop_fanout::max_value              1                       # Request fanout histogram
+testsys.membus.snoop_fanout::total              51694                       # Request fanout histogram
+testsys.tsunami.ethernet.clk_domain.clock         2000                       # Clock period in ticks
+testsys.tsunami.ethernet.descDMAReads            4849                       # Number of descriptors the device read w/ DMA
+testsys.tsunami.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
+testsys.tsunami.ethernet.descDmaReadBytes       116376                       # number of descriptor bytes read w/ DMA
+testsys.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+testsys.tsunami.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
+testsys.tsunami.ethernet.totalSwi                   0                       # total number of Swi written to ISR
+testsys.tsunami.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
+testsys.tsunami.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
+testsys.tsunami.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
+testsys.tsunami.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
+testsys.tsunami.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
+testsys.tsunami.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
+testsys.tsunami.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
+testsys.tsunami.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
+testsys.tsunami.ethernet.postedTxIdle              40                       # number of TxIdle interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedTxIdle            1                       # average number of TxIdle's coalesced into each post
+testsys.tsunami.ethernet.totalTxIdle             4849                       # total number of TxIdle written to ISR
+testsys.tsunami.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
+testsys.tsunami.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
+testsys.tsunami.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
+testsys.tsunami.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
+testsys.tsunami.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
+testsys.tsunami.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
+testsys.tsunami.ethernet.coalescedTotal             1                       # average number of interrupts coalesced into each post
+testsys.tsunami.ethernet.postedInterrupts         4849                       # number of posts to CPU
+testsys.tsunami.ethernet.droppedPackets             0                       # number of packets dropped
 
 ---------- End Simulation Statistics   ----------