learning_gem5: Fix vector port panic in SimpleCache
Change-Id: I0f3b71fdbed77690c533d9d14e774ab2cc08c053
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17870
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
diff --git a/src/learning_gem5/part2/simple_cache.cc b/src/learning_gem5/part2/simple_cache.cc
index 880dc39..6deefde 100644
--- a/src/learning_gem5/part2/simple_cache.cc
+++ b/src/learning_gem5/part2/simple_cache.cc
@@ -54,10 +54,10 @@
Port &
SimpleCache::getPort(const std::string &if_name, PortID idx)
{
- panic_if(idx != InvalidPortID, "This object doesn't support vector ports");
-
// This is the name from the Python SimObject declaration in SimpleCache.py
if (if_name == "mem_side") {
+ panic_if(idx != InvalidPortID,
+ "Mem side of simple cache not a vector port");
return memPort;
} else if (if_name == "cpu_side" && idx < cpuPorts.size()) {
// We should have already created all of the ports in the constructor
