diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
index ec3592c..63a2010 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
@@ -1,168 +1,168 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.397611                       # Number of seconds simulated
-sim_ticks                                47397610926500                       # Number of ticks simulated
-final_tick                               47397610926500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.443139                       # Number of seconds simulated
+sim_ticks                                47443139283500                       # Number of ticks simulated
+final_tick                               47443139283500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 110253                       # Simulator instruction rate (inst/s)
-host_op_rate                                   129665                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5829907242                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 703216                       # Number of bytes of host memory used
-host_seconds                                  8130.08                       # Real time elapsed on the host
-sim_insts                                   896366789                       # Number of instructions simulated
-sim_ops                                    1054186264                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 174986                       # Simulator instruction rate (inst/s)
+host_op_rate                                   205797                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9320406551                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 765676                       # Number of bytes of host memory used
+host_seconds                                  5090.24                       # Real time elapsed on the host
+sim_insts                                   890723033                       # Number of instructions simulated
+sim_ops                                    1047557701                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       107072                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker        78336                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          7782464                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         12802520                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     15762560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       159744                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       154688                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3994240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         12481056                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     14503040                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        448448                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             68274168                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      7782464                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      3994240                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total        11776704                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     79542656                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       111744                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        91648                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          7668224                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         13156952                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     13340800                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       149248                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       146240                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3865344                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         11856672                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     13765376                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        430976                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             64583224                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      7668224                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3865344                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total        11533568                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     75782720                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20812                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          79563472                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1673                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1224                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst            121601                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            200061                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       246290                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2496                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2417                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             62410                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            195031                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       226610                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           7007                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1066820                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1242854                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          75803536                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1746                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1432                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst            119816                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            205599                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       208450                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         2332                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         2285                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             60396                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            185275                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       215084                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6734                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1009149                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1184105                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2602                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1245457                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2259                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          1653                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              164195                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              270109                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       332560                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          3370                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          3264                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               84271                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              263327                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       305987                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             9461                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1440456                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         164195                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          84271                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             248466                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1678200                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1186708                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2355                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          1932                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              161630                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              277320                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       281196                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          3146                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          3082                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               81473                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              249913                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       290145                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9084                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1361276                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         161630                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          81473                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             243103                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1597338                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                439                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1678639                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1678200                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2259                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         1653                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             164195                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             270548                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       332560                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         3370                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         3264                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              84271                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             263327                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       305987                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            9461                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3119095                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1066820                       # Number of read requests accepted
-system.physmem.writeReqs                      1912174                       # Number of write requests accepted
-system.physmem.readBursts                     1066820                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1912174                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 68253568                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     22912                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 119234048                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  68274168                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              122233360                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      358                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                   49121                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         113360                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               61922                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               70972                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               57667                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               64982                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               65050                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               70572                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               72322                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               67337                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               57787                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              110760                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              57283                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              63297                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              60054                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              63124                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              62259                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              61074                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              110998                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              120192                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              114368                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              118573                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              116138                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              119482                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              124701                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              122822                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              112747                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              113706                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             111725                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             114999                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             115986                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             114347                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             116931                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             115317                       # Per bank write bursts
+system.physmem.bw_write::total                1597777                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1597338                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2355                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         1932                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             161630                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             277759                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       281196                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         3146                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         3082                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              81473                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             249913                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       290145                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9084                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2959053                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1009149                       # Number of read requests accepted
+system.physmem.writeReqs                      1850399                       # Number of write requests accepted
+system.physmem.readBursts                     1009149                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1850399                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 64564224                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     21312                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 115242304                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  64583224                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              118279760                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      333                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                   49721                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         115106                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               57845                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               61929                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               56818                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               63723                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               61880                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               68171                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               59739                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               60869                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               54876                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              108415                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              50407                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              61358                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              58228                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              64090                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              57873                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              62595                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              107469                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              113594                       # Per bank write bursts
+system.physmem.perBankWrBursts::2              115011                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              118413                       # Per bank write bursts
+system.physmem.perBankWrBursts::4              118243                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              118449                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              111339                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              115322                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              110047                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              111027                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             102767                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             112058                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             108184                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             112341                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             110504                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             115893                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                         309                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47397609004000                       # Total gap between requests
+system.physmem.numWrRetry                         251                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47443137361000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      37                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1066778                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1009107                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2601                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1909571                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    706521                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    126151                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     49462                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     37446                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     32271                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     29670                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     27253                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     24519                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     21077                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      5735                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1704                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     1231                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      954                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      743                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      468                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      414                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      346                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      284                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      124                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       82                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
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 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -188,169 +188,169 @@
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.bytesPerActivate::stdev     246.499626                       # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::128-255       204682     19.30%     83.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        51639      4.87%     87.95% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::896-1023         7827      0.74%     94.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        56177      5.30%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1060336                       # Bytes accessed per row activation
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-system.physmem.rdPerTurnAround::mean        12.888404                       # Reads before turning the bus around for writes
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-system.physmem.rdPerTurnAround::0-1023          82742    100.00%    100.00% # Reads before turning the bus around for writes
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 system.physmem.rdPerTurnAround::25600-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::samples         82745                       # Writes before turning the bus around for reads
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 system.physmem.wrPerTurnAround::704-719             1      0.00%    100.00% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::total           82745                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    40375015102                       # Total ticks spent queuing
-system.physmem.totMemAccLat               60371177602                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   5332310000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       37858.84                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::736-751             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::848-863             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           78960                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    36416381887                       # Total ticks spent queuing
+system.physmem.totMemAccLat               55331681887                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   5044080000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       36098.14                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  56608.84                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.44                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.52                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.44                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.58                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  54848.14                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.36                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.43                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.36                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.49                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.08                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.99                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     803348                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1065807                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.33                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  57.21                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15910609.09                       # Average gap between requests
-system.physmem.pageHitRate                      63.80                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 4142388600                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 2260231875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4140419400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               6138335520                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3095781190320                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1201204741230                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27384875125500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31698542432445                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.779401                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45556660870724                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1582710220000                       # Time in different power states
+system.physmem.avgWrQLen                        25.03                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     756126                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1035585                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   74.95                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  57.51                       # Row buffer hit rate for writes
+system.physmem.avgGap                     16591131.66                       # Average gap between requests
+system.physmem.pageHitRate                      63.77                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 3944550960                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 2152284750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                3829511400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               5947512480                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3098754740640                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1192681206900                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           27419667632250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             31726977439380                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.736993                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   45614623336779                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1584230440000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    258234748026                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    244280410221                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 3873751560                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 2113654125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                4177906200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               5934111840                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3095781190320                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1188231262785                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27396255369750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31696367246580                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.733509                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45575630122499                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1582710220000                       # Time in different power states
+system.physmem_1.actEnergy                 3749639040                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 2045934000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                4039144200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               5720654160                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3098754740640                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1188668792790                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           27423187293750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             31726166198580                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.719894                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   45620445429017                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1584230440000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    239268979001                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    238458431983                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -381,18 +381,18 @@
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              133516333                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         94941201                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          6028887                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups           100948341                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               73074204                       # Number of BTB hits
+system.cf0.dma_write_full_pages                  1671                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                    6846976                       # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs                         1674                       # Number of DMA write transactions.
+system.cpu0.branchPred.lookups              130059643                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         92054393                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          5970282                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            98035548                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               70777475                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            72.387722                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               15498997                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect           1074405                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            72.195725                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               15296635                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect           1065115                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -423,61 +423,61 @@
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   274493                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               274493                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         8574                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        74935                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples       274493                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0         274493    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       274493                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        83509                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 18665.041972                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 16952.057368                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 12810.377808                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535        82824     99.18%     99.18% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071          578      0.69%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607           32      0.04%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143           36      0.04%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679           27      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks                   268213                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               268213                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         8180                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        73055                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples       268213                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0         268213    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       268213                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        81235                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 18802.895870                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 17058.372218                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 13418.609606                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535        80487     99.08%     99.08% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071          639      0.79%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607           31      0.04%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143           33      0.04%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679           28      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215           11      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        83509                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        81235                       # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walksPending::samples    788586204                       # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::0      788586204    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::total    788586204                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        74935     89.73%     89.73% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M         8574     10.27%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total        83509                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       274493                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K        73055     89.93%     89.93% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M         8180     10.07%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        81235                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       268213                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       274493                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        83509                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       268213                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        81235                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        83509                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       358002                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        81235                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       349448                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    84777209                       # DTB read hits
-system.cpu0.dtb.read_misses                    227212                       # DTB read misses
-system.cpu0.dtb.write_hits                   75760151                       # DTB write hits
-system.cpu0.dtb.write_misses                    47281                       # DTB write misses
+system.cpu0.dtb.read_hits                    82876233                       # DTB read hits
+system.cpu0.dtb.read_misses                    221834                       # DTB read misses
+system.cpu0.dtb.write_hits                   73950839                       # DTB write hits
+system.cpu0.dtb.write_misses                    46379                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              42378                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1052                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   33980                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     2153                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  9225                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              41692                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1050                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   33850                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     2174                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  9634                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    11068                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                85004421                       # DTB read accesses
-system.cpu0.dtb.write_accesses               75807432                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    10897                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                83098067                       # DTB read accesses
+system.cpu0.dtb.write_accesses               73997218                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        160537360                       # DTB hits
-system.cpu0.dtb.misses                         274493                       # DTB misses
-system.cpu0.dtb.accesses                    160811853                       # DTB accesses
+system.cpu0.dtb.hits                        156827072                       # DTB hits
+system.cpu0.dtb.misses                         268213                       # DTB misses
+system.cpu0.dtb.accesses                    157095285                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -507,192 +507,191 @@
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    61212                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                61212                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2          587                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        52411                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples        61212                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          61212    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        61212                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        52998                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 21062.649289                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 19099.820516                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 14417.313367                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-32767        48615     91.73%     91.73% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-65535         3682      6.95%     98.68% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-98303          228      0.43%     99.11% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::98304-131071          379      0.72%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-163839           21      0.04%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::163840-196607           17      0.03%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-229375           22      0.04%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::229376-262143           13      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-294911            7      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::294912-327679            9      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-360447            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::360448-393215            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                    59559                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                59559                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2          562                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        52025                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples        59559                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          59559    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        59559                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        52587                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 21528.762508                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 19318.036298                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 15879.557576                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767        47969     91.22%     91.22% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535         3703      7.04%     98.26% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-98303          280      0.53%     98.79% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-131071          523      0.99%     99.79% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-163839           24      0.05%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::163840-196607           24      0.05%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-229375           27      0.05%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::229376-262143           16      0.03%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-294911            3      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::294912-327679            6      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-360447            8      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::360448-393215            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        52998                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        52587                       # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walksPending::samples    787865704                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::0      787865704    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::total    787865704                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        52411     98.89%     98.89% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M          587      1.11%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        52998                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K        52025     98.93%     98.93% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M          562      1.07%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        52587                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        61212                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        61212                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        59559                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        59559                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        52998                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        52998                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       114210                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   238748421                       # ITB inst hits
-system.cpu0.itb.inst_misses                     61212                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        52587                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        52587                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       112146                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   232580630                       # ITB inst hits
+system.cpu0.itb.inst_misses                     59559                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              42378                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1052                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   24001                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              41692                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1050                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   23871                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   196095                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   192056                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               238809633                       # ITB inst accesses
-system.cpu0.itb.hits                        238748421                       # DTB hits
-system.cpu0.itb.misses                          61212                       # DTB misses
-system.cpu0.itb.accesses                    238809633                       # DTB accesses
-system.cpu0.numCycles                       949769690                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               232640189                       # ITB inst accesses
+system.cpu0.itb.hits                        232580630                       # DTB hits
+system.cpu0.itb.misses                          59559                       # DTB misses
+system.cpu0.itb.accesses                    232640189                       # DTB accesses
+system.cpu0.numCycles                       928928804                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  439719858                       # Number of instructions committed
-system.cpu0.committedOps                    516807751                       # Number of ops (including micro ops) committed
-system.cpu0.discardedOps                     45409758                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends                     3855                       # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles                 93846100118                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi                              2.159943                       # CPI: cycles per instruction
-system.cpu0.ipc                              0.462975                       # IPC: instructions per cycle
+system.cpu0.committedInsts                  429144762                       # Number of instructions committed
+system.cpu0.committedOps                    504441860                       # Number of ops (including micro ops) committed
+system.cpu0.discardedOps                     43734034                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends                     3788                       # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles                 93957994041                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi                              2.164605                       # CPI: cycles per instruction
+system.cpu0.ipc                              0.461978                       # IPC: instructions per cycle
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   12790                       # number of quiesce instructions executed
-system.cpu0.tickCycles                      712933683                       # Number of cycles that the object actually ticked
-system.cpu0.idleCycles                      236836007                       # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements          5519291                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          480.702778                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          152151321                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          5519802                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            27.564634                       # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce                   12678                       # number of quiesce instructions executed
+system.cpu0.tickCycles                      694752800                       # Number of cycles that the object actually ticked
+system.cpu0.idleCycles                      234176004                       # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements          5394073                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          480.331401                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          148625740                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          5394584                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            27.550918                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       5096417500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   480.702778                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.938873                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.938873                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   480.331401                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.938147                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.938147                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          194                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          207                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          354                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           50                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        323933952                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       323933952                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     77613049                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       77613049                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     70091195                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      70091195                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       268191                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       268191                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       249696                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total       249696                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1731388                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1731388                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1698549                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1698549                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    147704244                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       147704244                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    147972435                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      147972435                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      3327173                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      3327173                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      2386267                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      2386267                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       673594                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       673594                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       788040                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::total       788040                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       148951                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       148951                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       180566                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       180566                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      5713440                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       5713440                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      6387034                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      6387034                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  50124059800                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  50124059800                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  46218650240                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  46218650240                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  32570768827                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  32570768827                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2177391616                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   2177391616                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   3839424984                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   3839424984                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      3590500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      3590500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  96342710040                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  96342710040                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  96342710040                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  96342710040                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     80940222                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     80940222                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     72477462                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     72477462                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       941785                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       941785                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data      1037736                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total      1037736                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1880339                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      1880339                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1879115                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      1879115                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    153417684                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    153417684                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    154359469                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    154359469                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.041107                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.041107                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.032924                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.032924                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.715231                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.715231                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.759384                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.759384                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.079215                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.079215                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.096091                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.096091                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.037241                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.037241                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.041378                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.041378                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15065.059677                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15065.059677                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19368.599675                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 19368.599675                       # average WriteReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41331.364940                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41331.364940                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14618.173869                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14618.173869                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21263.277605                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21263.277605                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses        316412315                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       316412315                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     75879605                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       75879605                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     68405292                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      68405292                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       266627                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       266627                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       249000                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::total       249000                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1685353                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1685353                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1648257                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1648257                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    144284897                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       144284897                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    144551524                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      144551524                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      3254530                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      3254530                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      2315784                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      2315784                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       640707                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       640707                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       788472                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::total       788472                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       144645                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       144645                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       180684                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       180684                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      5570314                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       5570314                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      6211021                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      6211021                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  49481056746                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  49481056746                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  45032988844                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  45032988844                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  32697185728                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  32697185728                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2134918217                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   2134918217                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   3848217698                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   3848217698                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      3587000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      3587000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  94514045590                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  94514045590                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  94514045590                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  94514045590                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     79134135                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     79134135                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     70721076                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     70721076                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       907334                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       907334                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data      1037472                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::total      1037472                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1829998                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      1829998                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1828941                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      1828941                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    149855211                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    149855211                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    150762545                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    150762545                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.041127                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.041127                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.032745                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.032745                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.706142                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.706142                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.759994                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.759994                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.079041                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.079041                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.098792                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.098792                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.037171                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.037171                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.041197                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.041197                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15203.748850                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15203.748850                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19446.109328                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 19446.109328                       # average WriteReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41469.051188                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41469.051188                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14759.709751                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14759.709751                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21298.054604                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21298.054604                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16862.469903                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 16862.469903                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15084.107904                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 15084.107904                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16967.453826                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 16967.453826                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15217.151188                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 15217.151188                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -701,96 +700,96 @@
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      3800112                       # number of writebacks
-system.cpu0.dcache.writebacks::total          3800112                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       429398                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       429398                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1005493                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1005493                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data           83                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total           83                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        41403                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        41403                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           51                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::total           51                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1434891                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1434891                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1434891                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1434891                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2897775                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      2897775                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1380774                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1380774                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       667964                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       667964                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       787957                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total       787957                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       107548                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       107548                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       180515                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       180515                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      4278549                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4278549                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      4946513                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      4946513                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  37570974686                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  37570974686                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  24854865946                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  24854865946                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  14971801156                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  14971801156                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  31379224673                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  31379224673                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1379388880                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1379388880                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3557992992                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3557992992                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2840500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2840500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  62425840632                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  62425840632                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  77397641788                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  77397641788                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5923264746                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5923264746                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5701581250                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5701581250                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11624845996                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11624845996                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.035801                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.035801                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019051                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019051                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.709253                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.709253                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.759304                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.759304                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.057196                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.057196                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.096064                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.096064                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027888                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.027888                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032045                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.032045                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12965.456147                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12965.456147                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18000.676393                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18000.676393                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22414.083927                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22414.083927                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39823.524219                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39823.524219                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12825.797597                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12825.797597                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19710.234562                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19710.234562                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      3714069                       # number of writebacks
+system.cpu0.dcache.writebacks::total          3714069                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       414551                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       414551                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       973091                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       973091                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data           89                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total           89                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        40213                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        40213                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           42                       # number of StoreCondReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::total           42                       # number of StoreCondReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1387642                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1387642                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1387642                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1387642                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2839979                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      2839979                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1342693                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1342693                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       635024                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       635024                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       788383                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total       788383                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       104432                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       104432                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       180642                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       180642                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      4182672                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4182672                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      4817696                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      4817696                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  37224821633                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  37224821633                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  24320285408                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  24320285408                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  14430000107                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  14430000107                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  31505168022                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  31505168022                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1352929391                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1352929391                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3566593771                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3566593771                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      3248500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      3248500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  61545107041                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  61545107041                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  75975107148                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  75975107148                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5918601247                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5918601247                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5692373000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5692373000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11610974247                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11610974247                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.035888                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.035888                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018986                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018986                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.699879                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.699879                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.759908                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.759908                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.057067                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.057067                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.098769                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.098769                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027911                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.027911                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031956                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.031956                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13107.428482                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13107.428482                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18113.064869                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18113.064869                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22723.550774                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22723.550774                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39961.754657                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39961.754657                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12955.122865                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12955.122865                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19743.989609                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19743.989609                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14590.423209                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14590.423209                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15646.909608                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15646.909608                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14714.303928                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14714.303928                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15770.008558                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15770.008558                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -798,58 +797,58 @@
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          9444901                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.930140                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          229100961                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          9445413                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            24.255261                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements          9298569                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.930207                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          223083541                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          9299081                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            23.989848                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      24039613250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.930140                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.930207                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999864                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999864                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          249                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          197                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           66                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          423                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           35                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        486538188                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       486538188                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    229100961                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      229100961                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    229100961                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       229100961                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    229100961                       # number of overall hits
-system.cpu0.icache.overall_hits::total      229100961                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      9445422                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      9445422                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      9445422                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       9445422                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      9445422                       # number of overall misses
-system.cpu0.icache.overall_misses::total      9445422                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  93680049293                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  93680049293                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  93680049293                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  93680049293                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  93680049293                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  93680049293                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    238546383                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    238546383                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    238546383                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    238546383                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    238546383                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    238546383                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.039596                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.039596                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.039596                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.039596                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.039596                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.039596                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9918.037468                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  9918.037468                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9918.037468                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  9918.037468                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9918.037468                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  9918.037468                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        474064354                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       474064354                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    223083541                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      223083541                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    223083541                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       223083541                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    223083541                       # number of overall hits
+system.cpu0.icache.overall_hits::total      223083541                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      9299091                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      9299091                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      9299091                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       9299091                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      9299091                       # number of overall misses
+system.cpu0.icache.overall_misses::total      9299091                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  92099739258                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  92099739258                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  92099739258                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  92099739258                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  92099739258                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  92099739258                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    232382632                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    232382632                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    232382632                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    232382632                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    232382632                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    232382632                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.040016                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.040016                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.040016                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.040016                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.040016                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.040016                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9904.165822                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  9904.165822                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9904.165822                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9904.165822                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9904.165822                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  9904.165822                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -858,241 +857,242 @@
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      9445422                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      9445422                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      9445422                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      9445422                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      9445422                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      9445422                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  84206359153                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  84206359153                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  84206359153                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  84206359153                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  84206359153                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  84206359153                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      9299091                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      9299091                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      9299091                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      9299091                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      9299091                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      9299091                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  82773169690                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  82773169690                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  82773169690                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  82773169690                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  82773169690                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  82773169690                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4833897250                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   4833897250                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   4833897250                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   4833897250                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.039596                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.039596                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.039596                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.039596                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.039596                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.039596                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8915.044680                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8915.044680                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8915.044680                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  8915.044680                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8915.044680                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  8915.044680                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.040016                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.040016                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.040016                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.040016                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.040016                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.040016                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8901.210848                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8901.210848                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8901.210848                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  8901.210848                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8901.210848                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  8901.210848                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      7452732                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      7456615                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit         3365                       # number of redundant prefetches already in prefetch queue
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 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       953257                       # number of prefetches not generated due to page crossing
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-system.cpu0.l2cache.tags.tagsinuse       16004.441587                       # Cycle average of tags in use
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-system.cpu0.l2cache.tags.sampled_refs         2732791                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            5.523223                       # Average number of references to valid blocks.
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 system.cpu0.l2cache.tags.warmup_cycle      5822698500                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  4841.451480                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    32.729529                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    10.200147                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  6443.890934                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3592.570226                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1083.599270                       # Average occupied blocks per requestor
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-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          336                       # Occupied blocks per task id
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 system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           73                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           13                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           10                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          221                       # Occupied blocks per task id
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-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5745                       # Occupied blocks per task id
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-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.864624                       # Percentage of cache occupancy per task id
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-system.cpu0.l2cache.ReadReq_hits::total      11999589                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks      3800109                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total      3800109                       # number of Writeback hits
-system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data       203236                       # number of WriteInvalidateReq hits
-system.cpu0.l2cache.WriteInvalidateReq_hits::total       203236                       # number of WriteInvalidateReq hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       106799                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total       106799                       # number of UpgradeReq hits
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-system.cpu0.l2cache.overall_hits::total      12890161                       # number of overall hits
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+system.cpu0.l2cache.Writeback_hits::total      3714063                       # number of Writeback hits
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+system.cpu0.l2cache.UpgradeReq_hits::total       102333                       # number of UpgradeReq hits
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 system.cpu0.l2cache.Writeback_misses::writebacks            1                       # number of Writeback misses
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-system.cpu0.l2cache.UpgradeReq_misses::total       124820                       # number of UpgradeReq misses
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-system.cpu0.l2cache.UpgradeReq_miss_latency::total   2735720409                       # number of UpgradeReq miss cycles
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-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.052115                       # miss rate for ReadReq accesses
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-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.266476                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.127600                       # miss rate for ReadReq accesses
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+system.cpu0.l2cache.WriteInvalidateReq_misses::total       583142                       # number of WriteInvalidateReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       124112                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total       124112                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       148691                       # number of SCUpgradeReq misses
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+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            3                       # number of SCUpgradeFailReq misses
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+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        10993                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8048                       # number of demand (read+write) misses
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+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        10993                       # number of overall misses
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+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    390640720                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    300789761                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst  22448225702                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data  32185912694                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total  55325568877                       # number of ReadReq miss cycles
+system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data    214128828                       # number of WriteInvalidateReq miss cycles
+system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total    214128828                       # number of WriteInvalidateReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2731788344                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total   2731788344                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3090531448                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3090531448                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      3176498                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      3176498                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  13196588662                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total  13196588662                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    390640720                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    300789761                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst  22448225702                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data  45382501356                       # number of demand (read+write) miss cycles
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+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    390640720                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    300789761                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst  22448225702                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data  45382501356                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  68522157539                       # number of overall miss cycles
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+system.cpu0.l2cache.Writeback_accesses::writebacks      3714064                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total      3714064                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data       786829                       # number of WriteInvalidateReq accesses(hits+misses)
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+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       226445                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total       226445                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       180639                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total       180639                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1128333                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total      1128333                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       473956                       # number of demand (read+write) accesses
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+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       473956                       # number of overall (read+write) accesses
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+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.023194                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.054096                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.079622                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.264431                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.126353                       # miss rate for ReadReq accesses
 system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000000                       # miss rate for Writeback accesses
 system.cpu0.l2cache.Writeback_miss_rate::total     0.000000                       # miss rate for Writeback accesses
-system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data     0.741504                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total     0.741504                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.538902                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.538902                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.817105                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.817105                       # miss rate for SCUpgradeReq accesses
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+system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total     0.741129                       # miss rate for WriteInvalidateReq accesses
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+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.548089                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.823139                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.823139                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.233128                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.233128                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.023766                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.052115                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.080131                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.258465                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.135816                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.023766                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.052115                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.080131                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.258465                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.135816                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34417.897702                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 35301.560657                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30340.478875                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 33312.435280                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32047.072663                       # average ReadReq miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data   388.860951                       # average WriteInvalidateReq miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total   388.860951                       # average WriteInvalidateReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21917.324219                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21917.324219                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20824.191440                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20824.191440                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data      1386000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1386000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49694.682196                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49694.682196                       # average ReadExReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34417.897702                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 35301.560657                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30340.478875                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36862.015637                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 34405.505106                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34417.897702                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 35301.560657                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30340.478875                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36862.015637                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 34405.505106                       # average overall miss latency
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.238646                       # miss rate for ReadExReq accesses
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+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 34007.346154                       # average ReadReq miss latency
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+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 22010.670556                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 22010.670556                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20784.926109                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20784.926109                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 1058832.666667                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1058832.666667                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49008.395459                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49008.395459                       # average ReadExReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35535.406168                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 37374.473285                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30318.560075                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37329.977294                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 34691.865003                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35535.406168                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 37374.473285                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30318.560075                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37329.977294                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 34691.865003                       # average overall miss latency
 system.cpu0.l2cache.blocked_cycles::no_mshrs           99                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
@@ -1101,148 +1101,151 @@
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1419293                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1419293                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            3                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst            9                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data          864                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total          876                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data           21                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total           21                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         9600                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         9600                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            3                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            9                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data        10464                       # number of demand (read+write) MSHR hits
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-system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            3                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            9                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data        10464                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total        10476                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        11483                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         7971                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst       756863                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data       977907                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total      1754224                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.writebacks::writebacks      1355884                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1355884                       # number of writebacks
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+system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data           23                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total           23                       # number of WriteInvalidateReq MSHR hits
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+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            6                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data         8727                       # number of demand (read+write) MSHR hits
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+system.cpu0.l2cache.overall_mshr_hits::cpu0.data         8727                       # number of overall MSHR hits
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 system.cpu0.l2cache.Writeback_mshr_misses::writebacks            1                       # number of Writeback MSHR misses
 system.cpu0.l2cache.Writeback_mshr_misses::total            1                       # number of Writeback MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       730042                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       730042                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data       582967                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total       582967                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       124820                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       124820                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       147498                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       147498                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       261133                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total       261133                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        11483                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         7971                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       756863                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1239040                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total      2015357                       # number of demand (read+write) MSHR misses
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-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         7971                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       756863                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1239040                       # number of overall MSHR misses
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-system.cpu0.l2cache.overall_mshr_misses::total      2745399                       # number of overall MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    320171021                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    229236274                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst  18018194823                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data  26119410327                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total  44687012445                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  38329201084                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  38329201084                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  25353006103                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total  25353006103                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2529620082                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2529620082                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2203543880                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2203543880                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2330000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2330000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  10429150296                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  10429150296                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    320171021                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    229236274                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  18018194823                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  36548560623                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total  55116162741                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    320171021                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    229236274                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  18018194823                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  36548560623                       # number of overall MSHR miss cycles
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-system.cpu0.l2cache.overall_mshr_miss_latency::total  93445363825                       # number of overall MSHR miss cycles
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+system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data       583119                       # number of WriteInvalidateReq MSHR misses
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+system.cpu0.l2cache.UpgradeReq_mshr_misses::total       124112                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       148691                       # number of SCUpgradeReq MSHR misses
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+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
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+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total  25478427229                       # number of WriteInvalidateReq MSHR miss cycles
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+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2526518712                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2211223584                       # number of SCUpgradeReq MSHR miss cycles
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+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2721498                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2721498                       # number of SCUpgradeFailReq MSHR miss cycles
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+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    248030007                       # number of demand (read+write) MSHR miss cycles
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+system.cpu0.l2cache.overall_mshr_miss_latency::total  87123176075                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4391070750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5656823753                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total  10047894503                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5452375000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5452375000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5652021253                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total  10043092003                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5443565000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5443565000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   4391070750                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11109198753                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  15500269503                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.023759                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.052115                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.080130                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.266241                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.127536                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11095586253                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  15486657003                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.023192                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.054089                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.079621                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.264207                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.126293                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for Writeback accesses
 system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000000                       # mshr miss rate for Writeback accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.741477                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.741477                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.538902                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.538902                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.817105                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.817105                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.741100                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.741100                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.548089                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.548089                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.823139                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.823139                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.224862                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.224862                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.023759                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.052115                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.080130                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.256301                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.135114                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.023759                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.052115                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.080130                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.256301                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.231620                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.231620                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.023192                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.054089                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.079621                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.256397                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.134417                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.023192                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.054089                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.079621                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.256397                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.184057                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27882.175477                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28758.784845                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23806.415194                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 26709.503385                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25473.948849                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 52502.734204                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 52502.734204                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43489.607650                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43489.607650                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20266.143903                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20266.143903                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14939.483112                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14939.483112                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data      1165000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      1165000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39938.078665                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39938.078665                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27882.175477                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28758.784845                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23806.415194                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29497.482424                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27348.089069                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27882.175477                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28758.784845                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23806.415194                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29497.482424                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 52502.734204                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34037.079428                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.181983                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28990.653748                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 30822.667702                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23784.778281                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27403.946250                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25858.743437                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46843.898684                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46843.898684                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43693.358009                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43693.358009                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20356.764149                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20356.764149                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14871.267151                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14871.267151                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       907166                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       907166                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39927.981557                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39927.981557                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28990.653748                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 30822.667702                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23784.778281                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30115.739692                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27728.591352                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28990.653748                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 30822.667702                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23784.778281                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30115.739692                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46843.898684                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 32724.888480                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1252,67 +1255,66 @@
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq      16517621                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     14068332                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        33225                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        33225                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback      3800110                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq      1086057                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq      1148168                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       786224                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       477409                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       332434                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       482483                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           61                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          127                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1303516                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1171227                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     18995457                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     16182353                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       335795                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1061304                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         36574909                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    607854592                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    610383865                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1223600                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      3866424                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1223328481                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    4849156                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     24579773                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       3.184734                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.388082                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq      16236238                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     13810704                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        33172                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        33172                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback      3714064                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq      1025800                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq      1145042                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       786829                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       475552                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       336189                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       478151                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           52                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          119                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1267323                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1138296                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     18702794                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     15835764                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       326673                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1038123                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         35903354                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    598489344                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    596885449                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1190176                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      3791640                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1200356609                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    4763261                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     24114639                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       3.184867                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.388190                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::3          20039056     81.53%     81.53% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::4           4540717     18.47%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::3          19656632     81.51%     81.51% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::4           4458007     18.49%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      24579773                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   14682015163                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      24114639                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   14405309409                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    205334987                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    207723992                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy  14272912820                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy  14053020534                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   7968080178                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   7776245419                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    183071466                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    178137962                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    578323929                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    564500428                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups              139172899                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         99233401                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          6252869                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups           105205307                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               76618629                       # Number of BTB hits
+system.cpu1.branchPred.lookups              140284857                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         99939687                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          6358953                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups           105820632                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               77032296                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            72.827722                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               16237430                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect           1026400                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            72.795158                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               16359380                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect           1035022                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1342,62 +1344,61 @@
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   295412                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               295412                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        11437                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        91734                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples       295412                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0         295412    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       295412                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       103171                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 19450.829041                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 17494.566732                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 15964.350233                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535       101752     98.62%     98.62% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1198      1.16%     99.79% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607           37      0.04%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143           80      0.08%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679           73      0.07%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215           18      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751            5      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287            6      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       103171                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks                   298079                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               298079                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        11270                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        91179                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples       298079                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0         298079    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       298079                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       102449                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 19055.295776                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 17104.036055                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 15328.339502                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535       101103     98.69%     98.69% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1144      1.12%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607           36      0.04%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143           71      0.07%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679           73      0.07%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215           15      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       102449                       # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walksPending::samples   1267166444                       # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::0     1267166444    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::total   1267166444                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        91734     88.91%     88.91% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        11437     11.09%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total       103171                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       295412                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkPageSizes::4K        91179     89.00%     89.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        11270     11.00%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       102449                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       298079                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       295412                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       103171                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       298079                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       102449                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       103171                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       398583                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       102449                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       400528                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    90130445                       # DTB read hits
-system.cpu1.dtb.read_misses                    246227                       # DTB read misses
-system.cpu1.dtb.write_hits                   78064785                       # DTB write hits
-system.cpu1.dtb.write_misses                    49185                       # DTB write misses
+system.cpu1.dtb.read_hits                    91176680                       # DTB read hits
+system.cpu1.dtb.read_misses                    248433                       # DTB read misses
+system.cpu1.dtb.write_hits                   79002879                       # DTB write hits
+system.cpu1.dtb.write_misses                    49646                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              42378                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1052                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   41873                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      864                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  7939                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              41692                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1050                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   41482                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      884                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  7879                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    11435                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                90376672                       # DTB read accesses
-system.cpu1.dtb.write_accesses               78113970                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    11586                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                91425113                       # DTB read accesses
+system.cpu1.dtb.write_accesses               79052525                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        168195230                       # DTB hits
-system.cpu1.dtb.misses                         295412                       # DTB misses
-system.cpu1.dtb.accesses                    168490642                       # DTB accesses
+system.cpu1.dtb.hits                        170179559                       # DTB hits
+system.cpu1.dtb.misses                         298079                       # DTB misses
+system.cpu1.dtb.accesses                    170477638                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1427,187 +1428,194 @@
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    68039                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                68039                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          556                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        57997                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        68039                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          68039    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        68039                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        58553                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 22020.763957                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 19263.180418                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 18942.782929                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        56928     97.22%     97.22% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071         1459      2.49%     99.72% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607           45      0.08%     99.79% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143           89      0.15%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679           17      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215           13      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        58553                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks                    68407                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                68407                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          609                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        58709                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        68407                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          68407    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        68407                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        59318                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 21639.401767                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 18915.934077                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 18524.659910                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767        54668     92.16%     92.16% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535         3100      5.23%     97.39% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-98303          594      1.00%     98.39% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071          801      1.35%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839           32      0.05%     99.79% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607           14      0.02%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-229375           58      0.10%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::229376-262143           21      0.04%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911            5      0.01%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679            4      0.01%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447           10      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::360448-393215            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-425983            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::425984-458751            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        59318                       # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walksPending::samples   1266435944                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::0     1266435944    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::total   1266435944                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        57997     99.05%     99.05% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          556      0.95%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        58553                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K        58709     98.97%     98.97% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          609      1.03%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        59318                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        68039                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        68039                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        68407                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        68407                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        58553                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        58553                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       126592                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   249268487                       # ITB inst hits
-system.cpu1.itb.inst_misses                     68039                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        59318                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        59318                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       127725                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   251160195                       # ITB inst hits
+system.cpu1.itb.inst_misses                     68407                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              42378                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1052                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   30522                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              41692                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1050                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   30244                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   226060                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   224879                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               249336526                       # ITB inst accesses
-system.cpu1.itb.hits                        249268487                       # DTB hits
-system.cpu1.itb.misses                          68039                       # DTB misses
-system.cpu1.itb.accesses                    249336526                       # DTB accesses
-system.cpu1.numCycles                       932637373                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               251228602                       # ITB inst accesses
+system.cpu1.itb.hits                        251160195                       # DTB hits
+system.cpu1.itb.misses                          68407                       # DTB misses
+system.cpu1.itb.accesses                    251228602                       # DTB accesses
+system.cpu1.numCycles                       937856787                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                  456646931                       # Number of instructions committed
-system.cpu1.committedOps                    537378513                       # Number of ops (including micro ops) committed
-system.cpu1.discardedOps                     48077866                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends                     5781                       # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles                 93863478723                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi                              2.042360                       # CPI: cycles per instruction
-system.cpu1.ipc                              0.489630                       # IPC: instructions per cycle
+system.cpu1.committedInsts                  461578271                       # Number of instructions committed
+system.cpu1.committedOps                    543115841                       # Number of ops (including micro ops) committed
+system.cpu1.discardedOps                     48137471                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends                     5811                       # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles                 93949323576                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi                              2.031848                       # CPI: cycles per instruction
+system.cpu1.ipc                              0.492163                       # IPC: instructions per cycle
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    5811                       # number of quiesce instructions executed
-system.cpu1.tickCycles                      738281563                       # Number of cycles that the object actually ticked
-system.cpu1.idleCycles                      194355810                       # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements          5504177                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          462.121005                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          159889231                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5504689                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            29.046006                       # Average number of references to valid blocks.
+system.cpu1.kern.inst.quiesce                    5892                       # number of quiesce instructions executed
+system.cpu1.tickCycles                      744774671                       # Number of cycles that the object actually ticked
+system.cpu1.idleCycles                      193082116                       # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.replacements          5501509                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          462.401458                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          161882040                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          5502021                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            29.422287                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle     8380046591500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   462.121005                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.902580                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.902580                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   462.401458                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.903128                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.903128                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          385                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           47                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0           77                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          337                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           98                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        339217340                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       339217340                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     82545716                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       82545716                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     72881068                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      72881068                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       234096                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       234096                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data        75438                       # number of WriteInvalidateReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::total        75438                       # number of WriteInvalidateReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1844359                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1844359                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1835233                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1835233                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    155426784                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       155426784                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    155660880                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      155660880                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      3601145                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      3601145                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      2300638                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      2300638                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       662253                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       662253                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data       453115                       # number of WriteInvalidateReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::total       453115                       # number of WriteInvalidateReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       186074                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       186074                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       193760                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       193760                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      5901783                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       5901783                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      6564036                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      6564036                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  55051091271                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  55051091271                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  39953352540                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  39953352540                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data  12827340347                       # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.WriteInvalidateReq_miss_latency::total  12827340347                       # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2834422928                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   2834422928                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4003287927                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   4003287927                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3321500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3321500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  95004443811                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  95004443811                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  95004443811                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  95004443811                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     86146861                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     86146861                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     75181706                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     75181706                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       896349                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       896349                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       528553                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::total       528553                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2030433                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      2030433                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2028993                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      2028993                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    161328567                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    161328567                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    162224916                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    162224916                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.041802                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.041802                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030601                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.030601                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.738834                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.738834                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.857274                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::total     0.857274                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.091643                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.091643                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.095496                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.095496                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.036582                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.036582                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.040463                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.040463                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15287.107648                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15287.107648                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17366.205609                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 17366.205609                       # average WriteReq miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 28309.237935                       # average WriteInvalidateReq miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 28309.237935                       # average WriteInvalidateReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15232.772596                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15232.772596                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20661.064859                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20661.064859                       # average StoreCondReq miss latency
+system.cpu1.dcache.tags.tag_accesses        343173973                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       343173973                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     83605080                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       83605080                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     73820570                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      73820570                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       234480                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       234480                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data        75463                       # number of WriteInvalidateReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::total        75463                       # number of WriteInvalidateReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1844270                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1844270                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1832447                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1832447                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    157425650                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       157425650                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    157660130                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      157660130                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      3592418                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      3592418                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      2291328                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      2291328                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       658469                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       658469                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data       456956                       # number of WriteInvalidateReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::total       456956                       # number of WriteInvalidateReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       185722                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       185722                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       196000                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       196000                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      5883746                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       5883746                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      6542215                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      6542215                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  54049590884                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  54049590884                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  39638005604                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  39638005604                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data  12577649145                       # number of WriteInvalidateReq miss cycles
+system.cpu1.dcache.WriteInvalidateReq_miss_latency::total  12577649145                       # number of WriteInvalidateReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2799761413                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   2799761413                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4076020251                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   4076020251                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2567000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2567000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  93687596488                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  93687596488                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  93687596488                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  93687596488                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     87197498                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     87197498                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     76111898                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     76111898                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       892949                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       892949                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       532419                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::total       532419                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2029992                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      2029992                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2028447                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      2028447                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    163309396                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    163309396                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    164202345                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    164202345                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.041199                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.041199                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030105                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.030105                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.737409                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.737409                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.858264                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::total     0.858264                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.091489                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.091489                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.096626                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.096626                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.036028                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.036028                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.039842                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.039842                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15045.462662                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15045.462662                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17299.140762                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 17299.140762                       # average WriteReq miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27524.858291                       # average WriteInvalidateReq miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27524.858291                       # average WriteInvalidateReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15075.012185                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15075.012185                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20796.021689                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20796.021689                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16097.583359                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 16097.583359                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14473.480007                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 14473.480007                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15923.120490                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 15923.120490                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14320.470435                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 14320.470435                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1616,96 +1624,96 @@
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      3506045                       # number of writebacks
-system.cpu1.dcache.writebacks::total          3506045                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       409825                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       409825                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       940543                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       940543                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data           72                       # number of WriteInvalidateReq MSHR hits
-system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total           72                       # number of WriteInvalidateReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        45181                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        45181                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           47                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::total           47                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      1350368                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      1350368                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      1350368                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      1350368                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3191320                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      3191320                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1360095                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1360095                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       661949                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       661949                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       453043                       # number of WriteInvalidateReq MSHR misses
-system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total       453043                       # number of WriteInvalidateReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       140893                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       140893                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       193713                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       193713                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4551415                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4551415                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      5213364                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      5213364                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  42631813644                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  42631813644                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  22019784779                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  22019784779                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  13605448576                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  13605448576                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  12141090903                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total  12141090903                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1806083972                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1806083972                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3702335044                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3702335044                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2795500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2795500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  64651598423                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  64651598423                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  78257046999                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  78257046999                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    498907500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    498907500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    556628501                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    556628501                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1055536001                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1055536001                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.037045                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.037045                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018091                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018091                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.738495                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.738495                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.857138                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.857138                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.069391                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.069391                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.095472                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.095472                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028212                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.028212                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.032137                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.032137                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13358.677176                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13358.677176                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16189.887309                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16189.887309                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20553.620560                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20553.620560                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26798.981340                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26798.981340                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12818.833952                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12818.833952                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19112.475900                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19112.475900                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      3514313                       # number of writebacks
+system.cpu1.dcache.writebacks::total          3514313                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       402319                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       402319                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       938195                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       938195                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data           62                       # number of WriteInvalidateReq MSHR hits
+system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total           62                       # number of WriteInvalidateReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        44601                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        44601                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           41                       # number of StoreCondReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::total           41                       # number of StoreCondReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      1340514                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      1340514                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      1340514                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      1340514                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3190099                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      3190099                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1353133                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1353133                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       658162                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       658162                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       456894                       # number of WriteInvalidateReq MSHR misses
+system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total       456894                       # number of WriteInvalidateReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       141121                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       141121                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       195959                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       195959                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4543232                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4543232                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      5201394                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      5201394                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  41952700254                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  41952700254                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  21819340170                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  21819340170                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  13178817169                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  13178817169                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  11885329605                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total  11885329605                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1778237950                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1778237950                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3771476218                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3771476218                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2255500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2255500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  63772040424                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  63772040424                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  76950857593                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  76950857593                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    517375000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    517375000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    587265498                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    587265498                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1104640498                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1104640498                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036585                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036585                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017778                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017778                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.737066                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.737066                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.858147                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.858147                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.069518                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.069518                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.096605                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.096605                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027820                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.027820                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031677                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.031677                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13150.908562                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13150.908562                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16125.052135                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16125.052135                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20023.667682                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20023.667682                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26013.319512                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26013.319512                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12600.803211                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12600.803211                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19246.251604                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19246.251604                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14204.724997                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14204.724997                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15010.854220                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15010.854220                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14036.712284                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14036.712284                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14794.275841                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14794.275841                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1713,58 +1721,58 @@
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          9392574                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          507.206734                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          239643264                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          9393086                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            25.512730                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.replacements          9531492                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          507.211334                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          241397065                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          9532004                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            25.324902                       # Average number of references to valid blocks.
 system.cpu1.icache.tags.warmup_cycle     8370013399000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   507.206734                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.990638                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.990638                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   507.211334                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.990647                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.990647                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          363                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2           40                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0          131                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          337                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           44                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        507465788                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       507465788                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    239643264                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      239643264                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    239643264                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       239643264                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    239643264                       # number of overall hits
-system.cpu1.icache.overall_hits::total      239643264                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      9393087                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      9393087                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      9393087                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       9393087                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      9393087                       # number of overall misses
-system.cpu1.icache.overall_misses::total      9393087                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  93629377858                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  93629377858                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  93629377858                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  93629377858                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  93629377858                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  93629377858                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    249036351                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    249036351                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    249036351                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    249036351                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    249036351                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    249036351                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.037718                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.037718                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.037718                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.037718                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.037718                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.037718                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9967.902763                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  9967.902763                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9967.902763                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  9967.902763                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9967.902763                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  9967.902763                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses        511390144                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       511390144                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    241397065                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      241397065                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    241397065                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       241397065                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    241397065                       # number of overall hits
+system.cpu1.icache.overall_hits::total      241397065                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      9532005                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      9532005                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      9532005                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       9532005                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      9532005                       # number of overall misses
+system.cpu1.icache.overall_misses::total      9532005                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  94727843232                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  94727843232                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  94727843232                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  94727843232                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  94727843232                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  94727843232                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    250929070                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    250929070                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    250929070                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    250929070                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    250929070                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    250929070                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.037987                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.037987                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.037987                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.037987                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.037987                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.037987                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9937.871752                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  9937.871752                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9937.871752                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  9937.871752                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9937.871752                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  9937.871752                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1773,236 +1781,236 @@
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      9393087                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      9393087                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      9393087                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      9393087                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      9393087                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      9393087                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  84210400586                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  84210400586                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  84210400586                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  84210400586                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  84210400586                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  84210400586                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      9532005                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      9532005                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      9532005                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      9532005                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      9532005                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      9532005                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  85170319722                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  85170319722                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  85170319722                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  85170319722                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  85170319722                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  85170319722                       # number of overall MSHR miss cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8117000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8117000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8117000                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::total      8117000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.037718                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.037718                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.037718                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.037718                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.037718                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.037718                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8965.146451                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8965.146451                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8965.146451                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  8965.146451                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8965.146451                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  8965.146451                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.037987                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.037987                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.037987                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.037987                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.037987                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.037987                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8935.194612                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8935.194612                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8935.194612                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  8935.194612                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8935.194612                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  8935.194612                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      7598599                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      7600232                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit         1400                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      7632700                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      7634373                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit         1426                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       976472                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements         2525133                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13593.944555                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          15352366                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         2541314                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            6.041113                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    9806300117000                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  4972.841269                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    81.331762                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    87.569688                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  4463.050805                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3225.843213                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   763.307818                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.303518                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004964                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.005345                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.272403                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.196890                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.046589                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.829709                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1470                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           73                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14638                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           15                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          202                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          684                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          569                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           22                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           26                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           25                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1158                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         2664                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5264                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         5426                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.089722                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004456                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.893433                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       318573099                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      318573099                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       537712                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       159577                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst      8583648                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.data      2948596                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total      12229533                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks      3506045                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total      3506045                       # number of Writeback hits
-system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data       188584                       # number of WriteInvalidateReq hits
-system.cpu1.l2cache.WriteInvalidateReq_hits::total       188584                       # number of WriteInvalidateReq hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        74085                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total        74085                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        41733                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total        41733                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       900308                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       900308                       # number of ReadExReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       537712                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       159577                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      8583648                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3848904                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total       13129841                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       537712                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       159577                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      8583648                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3848904                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total      13129841                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        13252                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9078                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.inst       809439                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.data      1045283                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total      1877052                       # number of ReadReq misses
-system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data       263334                       # number of WriteInvalidateReq misses
-system.cpu1.l2cache.WriteInvalidateReq_misses::total       263334                       # number of WriteInvalidateReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       141894                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       141894                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       151971                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       151971                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            9                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total            9                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       245370                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       245370                       # number of ReadExReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        13252                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9078                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       809439                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1290653                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      2122422                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        13252                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9078                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       809439                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1290653                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      2122422                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    492724981                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    392484013                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst  23676424280                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data  34749867857                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total  59311501131                       # number of ReadReq miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data    207047946                       # number of WriteInvalidateReq miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total    207047946                       # number of WriteInvalidateReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   3083845016                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total   3083845016                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3158531415                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3158531415                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2735500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2735500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  10633257356                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total  10633257356                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    492724981                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    392484013                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst  23676424280                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data  45383125213                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  69944758487                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    492724981                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    392484013                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  23676424280                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data  45383125213                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  69944758487                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       550964                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       168655                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.inst      9393087                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.data      3993879                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total     14106585                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks      3506045                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total      3506045                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data       451918                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.WriteInvalidateReq_accesses::total       451918                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       215979                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       215979                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       193704                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       193704                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            9                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            9                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1145678                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total      1145678                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       550964                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       168655                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      9393087                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data      5139557                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total     15252263                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       550964                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       168655                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      9393087                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data      5139557                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total     15252263                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.024052                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.053826                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.086174                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.261721                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.133062                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data     0.582703                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total     0.582703                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.656981                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.656981                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.784553                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.784553                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.prefetcher.pfSpanPage       974619                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements         2493350                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13598.009718                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          15504995                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         2509448                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            6.178648                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    9806309185500                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks  5002.427380                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    85.119837                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    87.520686                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  4382.194744                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3239.455000                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   801.292071                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.305324                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.005195                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.005342                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.267468                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.197721                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.048907                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.829957                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1340                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           68                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14690                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           24                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          317                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          958                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4           41                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           38                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           27                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          120                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1230                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4980                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         7916                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          444                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.081787                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004150                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.896606                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       320697996                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      320697996                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       533308                       # number of ReadReq hits
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+system.cpu1.l2cache.Writeback_hits::writebacks      3514312                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total      3514312                       # number of Writeback hits
+system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data       195589                       # number of WriteInvalidateReq hits
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+system.cpu1.l2cache.UpgradeReq_hits::total        70594                       # number of UpgradeReq hits
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+system.cpu1.l2cache.UpgradeReq_misses::total       141488                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       155591                       # number of SCUpgradeReq misses
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+system.cpu1.l2cache.UpgradeReq_miss_latency::total   3089566814                       # number of UpgradeReq miss cycles
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+system.cpu1.l2cache.Writeback_accesses::writebacks      3514312                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total      3514312                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data       455738                       # number of WriteInvalidateReq accesses(hits+misses)
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+system.cpu1.l2cache.UpgradeReq_accesses::total       212082                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       195951                       # number of SCUpgradeReq accesses(hits+misses)
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+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       166533                       # number of overall (read+write) accesses
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+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.085928                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.256991                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.131082                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data     0.570830                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total     0.570830                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.667138                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.667138                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.794030                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.794030                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.214170                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.214170                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.024052                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.053826                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.086174                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.251121                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.139155                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.024052                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.053826                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.086174                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.251121                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.139155                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37181.178765                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 43234.634611                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29250.412051                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 33244.459019                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31598.219512                       # average ReadReq miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data   786.256032                       # average WriteInvalidateReq miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total   786.256032                       # average WriteInvalidateReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21733.441978                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21733.441978                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20783.777267                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20783.777267                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 303944.444444                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 303944.444444                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43335.604825                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43335.604825                       # average ReadExReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37181.178765                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 43234.634611                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29250.412051                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35162.917696                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 32955.160890                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37181.178765                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 43234.634611                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29250.412051                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35162.917696                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 32955.160890                       # average overall miss latency
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+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.247470                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.137261                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 36802.274318                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 42089.419654                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 28966.959234                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32698.921307                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31133.300331                       # average ReadReq miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data   871.804574                       # average WriteInvalidateReq miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total   871.804574                       # average WriteInvalidateReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21836.246282                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21836.246282                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20806.229840                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20806.229840                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 275687.250000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 275687.250000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42812.514389                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42812.514389                       # average ReadExReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 36802.274318                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 42089.419654                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28966.959234                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34648.512245                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 32488.004053                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 36802.274318                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 42089.419654                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28966.959234                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34648.512245                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 32488.004053                       # average overall miss latency
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -2011,144 +2019,147 @@
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks      1067908                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1067908                       # number of writebacks
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-system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data            3                       # number of WriteInvalidateReq MSHR hits
-system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total            3                       # number of WriteInvalidateReq MSHR hits
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-system.cpu1.l2cache.ReadExReq_mshr_hits::total         7579                       # number of ReadExReq MSHR hits
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-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       141894                       # number of UpgradeReq MSHR misses
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-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       151971                       # number of SCUpgradeReq MSHR misses
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-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            9                       # number of SCUpgradeFailReq MSHR misses
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-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    332680003                       # number of ReadReq MSHR miss cycles
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 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7360000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    459163000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    466523000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    519410999                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    519410999                       # number of WriteReq MSHR uncacheable cycles
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 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7360000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    978573999                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    985933999                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.024052                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.053808                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.086174                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.261514                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.133003                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1025382002                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1032742002                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.023031                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.053767                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.085928                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.256780                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.131022                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.582696                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.582696                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.656981                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.656981                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.784553                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.784553                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.570813                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.570813                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.667138                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.667138                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.794030                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.794030                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.207555                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.207555                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.024052                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.053808                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.086174                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.249486                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.138603                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.024052                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.053808                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.086174                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.249486                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.207860                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.207860                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.023031                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.053767                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.085928                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.245886                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.136733                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.023031                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.053767                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.085928                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.245886                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.186252                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30625.415711                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 36658.953499                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22722.421260                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26660.088082                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25037.672304                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46384.470766                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46384.470766                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32812.266011                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32812.266011                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19486.318153                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19486.318153                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14796.710109                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14796.710109                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 261333.333333                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 261333.333333                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33792.425824                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33792.425824                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30625.415711                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 36658.953499                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22722.421260                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27982.771658                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26022.436146                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30625.415711                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 36658.953499                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22722.421260                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27982.771658                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46384.470766                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31231.631271                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.183418                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30250.557350                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35517.674447                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22440.200456                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26115.946165                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24574.564200                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45129.323351                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45129.323351                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32101.818529                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32101.818529                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19546.883813                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19546.883813                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14787.980462                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14787.980462                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 235874.750000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 235874.750000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33359.452778                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33359.452778                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30250.557350                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35517.674447                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22440.200456                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27479.472783                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25567.068002                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30250.557350                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35517.674447                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22440.200456                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27479.472783                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45129.323351                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30546.227697                       # average overall mshr miss latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -2158,63 +2169,63 @@
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq      16687989                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp     14334572                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq         4962                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         4962                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback      3506045                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq      1053826                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq      1133141                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       451918                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       452249                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       341136                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       469204                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           77                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          127                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1304040                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1151075                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     18786353                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15676887                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       371904                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1206650                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         36041794                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    601163264                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    587975003                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1349240                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4407712                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total        1194895219                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    5002181                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     24473447                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       3.192626                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.394362                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq      16743915                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp     14472665                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         5158                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         5158                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback      3514312                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq      1035959                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq      1137929                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       455738                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       448749                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       344575                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       466415                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           78                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          119                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1299611                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1147815                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     19064189                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15671741                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       370835                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1205745                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         36312510                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    610054016                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    588145619                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1332264                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4367048                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total        1203898947                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    4911557                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     24519969                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       3.188170                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.390848                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::3          19759234     80.74%     80.74% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::4           4714213     19.26%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::3          19906035     81.18%     81.18% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::4           4613934     18.82%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      24473447                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   13845201909                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      24519969                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   13930930666                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    163397980                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    160378480                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy  14102728136                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy  14310919255                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   8209870082                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   8198844119                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    203661942                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    204674963                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    656138927                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    660298903                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40316                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40316                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136601                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              29873                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp       106728                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47648                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                40379                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40379                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136954                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              29970                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp       106984                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47756                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2224,18 +2235,18 @@
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29756                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122530                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231224                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231224                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122846                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231740                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231740                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353834                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47668                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354666                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47776                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2245,18 +2256,18 @@
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17674                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155660                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338912                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7338912                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155884                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7355312                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7355312                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7496658                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36180000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7513282                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36279000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -2276,7 +2287,7 @@
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            22103000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
@@ -2284,71 +2295,71 @@
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           607453407                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           609062244                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92660000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92879000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           148582123                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           148791282                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy              170500                       # Layer occupancy (ticks)
+system.iobus.respLayer4.occupancy              171000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115592                       # number of replacements
-system.iocache.tags.tagsinuse               11.295153                       # Cycle average of tags in use
+system.iocache.tags.replacements               115866                       # number of replacements
+system.iocache.tags.tagsinuse               11.306200                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115608                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115882                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9129697263000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     7.412327                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     3.882827                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.463270                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.242677                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.705947                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         9129676346000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     7.405197                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     3.901004                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.462825                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.243813                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.706638                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1040865                       # Number of tag accesses
-system.iocache.tags.data_accesses             1040865                       # Number of data accesses
+system.iocache.tags.tag_accesses              1043187                       # Number of tag accesses
+system.iocache.tags.data_accesses             1043187                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8884                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8921                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8886                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8923                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide       106728                       # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total       106728                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide       106984                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total       106984                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8884                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8924                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8886                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8926                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8884                       # number of overall misses
-system.iocache.overall_misses::total             8924                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5195500                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1659251745                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1664447245                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8886                       # number of overall misses
+system.iocache.overall_misses::total             8926                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5190000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1626687073                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1631877073                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide  19947928539                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total  19947928539                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5564500                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1659251745                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1664816245                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5564500                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1659251745                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1664816245                       # number of overall miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide  19941362889                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  19941362889                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5559000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1626687073                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1632246073                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5559000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1626687073                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1632246073                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8884                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8921                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8886                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8923                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide       106728                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total       106728                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide       106984                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total       106984                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8884                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8924                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8886                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8926                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8884                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8924                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8886                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8926                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -2362,55 +2373,55 @@
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 186768.544012                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 186576.308149                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140270.270270                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 183061.790795                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 182884.352012                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186904.360046                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 186904.360046                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 186768.544012                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 186554.935567                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 186768.544012                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 186554.935567                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        112960                       # number of cycles access was blocked
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186395.749729                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 186395.749729                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       138975                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 183061.790795                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 182864.225073                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       138975                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 183061.790795                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 182864.225073                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        111964                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                16486                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                16416                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     6.851874                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     6.820419                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks          106678                       # number of writebacks
-system.iocache.writebacks::total               106678                       # number of writebacks
+system.iocache.writebacks::writebacks          106950                       # number of writebacks
+system.iocache.writebacks::total               106950                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8884                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8921                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8886                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8923                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106728                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total       106728                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106984                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total       106984                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8884                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8924                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8886                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8926                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8884                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8924                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3270500                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1196099891                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1199370391                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8886                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8926                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3264000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1163415573                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1166679573                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       213000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       213000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  14397972639                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total  14397972639                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3483500                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1196099891                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1199583391                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3483500                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1196099891                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1199583391                       # number of overall MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  14378130953                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  14378130953                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3477000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1163415573                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1166892573                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3477000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1163415573                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1166892573                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -2424,561 +2435,562 @@
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134635.287145                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 134443.491873                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88216.216216                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130926.803174                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 130749.699989                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        71000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        71000                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134903.424022                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134903.424022                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 134635.287145                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 134422.163940                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 134635.287145                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 134422.163940                       # average overall mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134395.152107                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134395.152107                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        86925                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 130926.803174                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 130729.618306                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        86925                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 130926.803174                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 130729.618306                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1488066                       # number of replacements
-system.l2c.tags.tagsinuse                64457.051863                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    5017316                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1548603                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     3.239898                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1418934                       # number of replacements
+system.l2c.tags.tagsinuse                64475.403646                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4887849                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1480275                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     3.301987                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle               8811587000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   16300.231028                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    18.590542                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     5.410855                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3923.984358                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     5628.040249                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  3900.550479                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   368.152358                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   516.465158                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     4442.350927                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data    11307.713496                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 18045.562414                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.248722                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000284                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000083                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.059875                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.085877                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.059518                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.005618                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.007881                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.067785                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.172542                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.275353                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.983537                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        10439                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          248                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        49850                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2           83                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3          337                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        10018                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          248                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          132                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1727                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         4981                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        42979                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.159286                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.003784                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.760651                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 65141561                       # Number of tag accesses
-system.l2c.tags.data_accesses                65141561                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         6849                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         4798                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             687325                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             588389                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher       296114                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         6913                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         4145                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             746877                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             598329                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher       312912                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                3252651                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         2487202                       # number of Writeback hits
-system.l2c.Writeback_hits::total              2487202                       # number of Writeback hits
-system.l2c.WriteInvalidateReq_hits::cpu0.data       134878                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::cpu1.data       131392                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::total       266270                       # number of WriteInvalidateReq hits
-system.l2c.UpgradeReq_hits::cpu0.data           30237                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data           30181                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               60418                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          6187                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          6142                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             12329                       # number of SCUpgradeReq hits
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-system.l2c.ReadExReq_hits::cpu1.data            53204                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               109753                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          6849                       # number of demand (read+write) hits
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-system.l2c.demand_hits::cpu0.inst              687325                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              644938                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       296114                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          6913                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          4145                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              746877                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              651533                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher       312912                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 3362404                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         6849                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         4798                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             687325                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             644938                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       296114                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         6913                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         4145                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             746877                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             651533                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher       312912                       # number of overall hits
-system.l2c.overall_hits::total                3362404                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         1673                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         1224                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst            69538                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           125760                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       246479                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker         2496                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         2417                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst            62560                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data           141194                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher       226658                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               879999                       # number of ReadReq misses
-system.l2c.WriteInvalidateReq_misses::cpu0.data       439420                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::cpu1.data       123627                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::total       563047                       # number of WriteInvalidateReq misses
-system.l2c.UpgradeReq_misses::cpu0.data         45454                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         42845                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             88299                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data         9151                       # number of SCUpgradeReq misses
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-system.l2c.SCUpgradeReq_misses::total           17870                       # number of SCUpgradeReq misses
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-system.l2c.demand_misses::cpu1.data            197211                       # number of demand (read+write) misses
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-system.l2c.overall_misses::cpu0.data           202536                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       246479                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         2496                       # number of overall misses
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-system.l2c.overall_misses::cpu1.data           197211                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       226658                       # number of overall misses
-system.l2c.overall_misses::total              1012792                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    154004272                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker    114242270                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst   5875477080                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data  11741177980                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  33542362820                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    221714757                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker    213708998                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst   5282320946                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data  12643416993                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher  28768061033                       # number of ReadReq miss cycles
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-system.l2c.UpgradeReq_miss_latency::cpu1.data    266190062                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    539452996                       # number of UpgradeReq miss cycles
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-system.l2c.ReadExReq_miss_latency::total  11657651789                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    154004272                       # number of demand (read+write) miss cycles
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-system.l2c.demand_miss_latency::cpu0.inst   5875477080                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  18649195976                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  33542362820                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    221714757                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    213708998                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   5282320946                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  17393050786                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  28768061033                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    110214138938                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    154004272                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    114242270                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   5875477080                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  18649195976                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  33542362820                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    221714757                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    213708998                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   5282320946                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  17393050786                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  28768061033                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   110214138938                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker         8522                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         6022                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         756863                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         714149                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       542593                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker         9409                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         6562                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         809437                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         739523                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher       539570                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            4132650                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      2487202                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          2487202                       # number of Writeback accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu0.data       574298                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu1.data       255019                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::total       829317                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        75691                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        73026                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          148717                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        15338                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        14861                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         30199                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       133325                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       109221                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           242546                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         8522                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         6022                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          756863                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          847474                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       542593                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         9409                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         6562                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          809437                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          848744                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       539570                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             4375196                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         8522                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         6022                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         756863                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         847474                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       542593                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         9409                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         6562                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         809437                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         848744                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       539570                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            4375196                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.196315                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.203255                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.091877                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.176098                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.454261                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.265278                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.368333                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.077288                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.190926                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.420072                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.212938                       # miss rate for ReadReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.765143                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.484776                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::total     0.678929                       # miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.600521                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.586709                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.593738                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.596623                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.586703                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.591741                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.575856                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.512878                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.547496                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.196315                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.203255                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.091877                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.238988                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.454261                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.265278                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.368333                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.077288                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.232356                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.420072                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.231485                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.196315                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.203255                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.091877                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.238988                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.454261                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.265278                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.368333                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.077288                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.232356                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.420072                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.231485                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 92052.762702                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 93335.187908                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84493.040927                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 93361.784192                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 136086.087740                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88828.027644                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 88419.113777                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84436.076503                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 89546.418353                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 126922.769251                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 111996.135392                       # average ReadReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data   124.077866                       # average WriteInvalidateReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data   332.513925                       # average WriteInvalidateReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::total   169.843716                       # average WriteInvalidateReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6011.856690                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6212.861757                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  6109.389642                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5255.926565                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  6445.488244                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  5836.328819                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89976.268574                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84789.149597                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 87788.149895                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 92052.762702                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 93335.187908                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 84493.040927                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 92078.425445                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 136086.087740                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88828.027644                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88419.113777                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 84436.076503                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 88195.135089                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 126922.769251                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 108822.086804                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 92052.762702                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 93335.187908                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 84493.040927                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 92078.425445                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 136086.087740                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88828.027644                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88419.113777                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 84436.076503                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 88195.135089                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 126922.769251                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 108822.086804                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs              2541                       # number of cycles access was blocked
+system.l2c.tags.occ_blocks::writebacks   16720.464314                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     9.676845                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     2.082484                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3893.344537                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     5310.090712                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  3772.998059                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   379.879752                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   518.261056                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     4648.220337                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data    11740.962883                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17479.422666                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.255134                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000148                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.000032                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.059408                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.081026                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.057571                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.005797                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.007908                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.070926                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.179153                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.266715                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.983817                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022         9966                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          213                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        51162                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::0            2                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::1           69                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          272                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3         1682                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4         7941                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          195                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          240                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         1978                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3        11118                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        37794                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.152069                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003250                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.780670                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 63367915                       # Number of tag accesses
+system.l2c.tags.data_accesses                63367915                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker         6326                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         4773                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             672724                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             551559                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher       298336                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker         6350                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         4103                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             758519                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             584378                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher       311165                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                3198233                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks         2396374                       # number of Writeback hits
+system.l2c.Writeback_hits::total              2396374                       # number of Writeback hits
+system.l2c.WriteInvalidateReq_hits::cpu0.data       132089                       # number of WriteInvalidateReq hits
+system.l2c.WriteInvalidateReq_hits::cpu1.data       134441                       # number of WriteInvalidateReq hits
+system.l2c.WriteInvalidateReq_hits::total       266530                       # number of WriteInvalidateReq hits
+system.l2c.UpgradeReq_hits::cpu0.data           29493                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data           27736                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               57229                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data          5838                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data          6131                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total             11969                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            53859                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            51185                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               105044                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          6326                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          4773                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              672724                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              605418                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher       298336                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          6350                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          4103                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              758519                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              635563                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher       311165                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 3303277                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         6326                       # number of overall hits
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+system.l2c.UpgradeReq_miss_latency::cpu1.data    288996819                       # number of UpgradeReq miss cycles
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+system.l2c.Writeback_accesses::writebacks      2396374                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          2396374                       # number of Writeback accesses(hits+misses)
+system.l2c.WriteInvalidateReq_accesses::cpu0.data       575043                       # number of WriteInvalidateReq accesses(hits+misses)
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+system.l2c.UpgradeReq_accesses::cpu1.data        72394                       # number of UpgradeReq accesses(hits+misses)
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+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.216303                       # miss rate for ReadReq accesses
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+system.l2c.ReadReq_miss_rate::cpu0.inst      0.091412                       # miss rate for ReadReq accesses
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+system.l2c.ReadReq_miss_rate::total          0.204599                       # miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.770297                       # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.464517                       # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::total     0.677367                       # miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.607754                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.616874                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.612228                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.604953                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.591376                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.598113                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.590095                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.517982                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.557864                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.216303                       # miss rate for demand accesses
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+system.l2c.demand_miss_rate::total           0.224308                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.216303                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::total          0.224308                       # miss rate for overall accesses
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+system.l2c.ReadReq_avg_miss_latency::total 110274.031012                       # average ReadReq miss latency
+system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data   109.211099                       # average WriteInvalidateReq miss latency
+system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data   355.087263                       # average WriteInvalidateReq miss latency
+system.l2c.WriteInvalidateReq_avg_miss_latency::total   160.455182                       # average WriteInvalidateReq miss latency
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+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6471.333669                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  6073.871474                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5484.222483                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  6691.211090                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  6085.446865                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89373.736390                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83951.505181                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 87123.497552                       # average ReadExReq miss latency
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+system.l2c.demand_avg_miss_latency::cpu1.data 87621.307073                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::total 107061.810305                       # average overall miss latency
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 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
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 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    139394486                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    115450499                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   4870282387                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  16465928626                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  25233483205                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    176791243                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    171176743                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst   4312003588                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data  14077766313                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  24818336697                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  90380613787                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    139394486                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    115450499                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   4870282387                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  16465928626                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  25233483205                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    176791243                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    171176743                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst   4312003588                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data  14077766313                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  24818336697                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  90380613787                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   3188012750                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5006572250                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5001418750                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5293500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    361466500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   8561345000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4837026001                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    427260001                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5264286002                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    377070000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   8571795000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4829205000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    452800000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   5282005000                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   3188012750                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9843598251                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9830623750                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      5293500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    788726501                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  13825631002                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.196315                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.203255                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.091569                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.176050                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.454261                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.265278                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.368333                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.077021                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.190900                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.420072                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.212817                       # mshr miss rate for ReadReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.765143                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.484776                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.678929                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.600521                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.586709                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.593738                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.596623                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.586703                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.591741                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.575848                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.512878                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.547492                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.196315                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.203255                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.091569                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.238947                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.454261                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.265278                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.368333                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.077021                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.232334                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.420072                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.231370                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.196315                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.203255                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.091569                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.238947                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.265278                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.368333                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.077021                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.232334                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::total     0.231370                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79438.272564                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 80712.196078                       # average ReadReq mshr miss latency
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80848.279354                       # average ReadReq mshr miss latency
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76234.872997                       # average ReadReq mshr miss latency
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77016.382199                       # average ReadReq mshr miss latency
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-system.l2c.ReadReq_avg_mshr_miss_latency::total 99617.771443                       # average ReadReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33583.928144                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32063.710201                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33250.137211                       # average WriteInvalidateReq mshr miss latency
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-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17796.886334                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17819.536552                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17860.137471                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17820.412203                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17840.755008                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77480.654562                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72287.514629                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 75289.979524                       # average ReadExReq mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71996.654931                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79571.498531                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123809.973523                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76234.872997                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 75817.128672                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71919.235275                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75673.036756                       # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::total 96426.453406                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79438.272564                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80712.196078                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71996.654931                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79571.498531                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123809.973523                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76234.872997                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 75817.128672                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71919.235275                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75673.036756                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114625.422288                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 96426.453406                       # average overall mshr miss latency
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    829870000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  13853800000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.216303                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.230782                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.091193                       # mshr miss rate for ReadReq accesses
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+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.268602                       # mshr miss rate for ReadReq accesses
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+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.073657                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.184765                       # mshr miss rate for ReadReq accesses
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+system.l2c.ReadReq_mshr_miss_rate::total     0.204495                       # mshr miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.770297                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.464517                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.677367                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.607754                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.616874                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.612228                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.604953                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.591376                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.598113                       # mshr miss rate for SCUpgradeReq accesses
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+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.517982                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.557864                       # mshr miss rate for ReadExReq accesses
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+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.230782                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.091193                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.255653                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.411518                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.268602                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.357702                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.073657                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.227758                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.408764                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.224210                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.216303                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.230782                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.091193                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.255653                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.411518                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.268602                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.357702                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.073657                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.227758                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.408764                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.224210                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79836.475372                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 80621.856844                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72130.959523                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80558.829037                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120952.546963                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75810.996141                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 74913.235449                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71473.621548                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76617.147137                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115363.832721                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 97889.611530                       # average ReadReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33579.020650                       # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32048.054457                       # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33259.945559                       # average WriteInvalidateReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17817.885507                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17791.659815                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17804.923446                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17847.137919                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17802.416206                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17824.861169                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76873.835674                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71448.956603                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 74622.497967                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79836.475372                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80621.856844                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72130.959523                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79184.818080                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120952.546963                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75810.996141                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 74913.235449                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71473.621548                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75100.646101                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115363.832721                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 94659.804929                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79836.475372                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80621.856844                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72130.959523                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79184.818080                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120952.546963                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75810.996141                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 74913.235449                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71473.621548                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75100.646101                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115363.832721                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 94659.804929                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -2993,58 +3005,58 @@
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              979077                       # Transaction distribution
-system.membus.trans_dist::ReadResp             979077                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38187                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38187                       # Transaction distribution
-system.membus.trans_dist::Writeback           1242854                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       666717                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       666717                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           428866                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         287024                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          113399                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq           43                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            145453                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           128623                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122530                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq              921958                       # Transaction distribution
+system.membus.trans_dist::ReadResp             921958                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38330                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38330                       # Transaction distribution
+system.membus.trans_dist::Writeback           1184105                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq       663691                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp       663691                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           435500                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         292205                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          115129                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq           30                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            144960                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           128452                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122846                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           52                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25066                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5227832                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      5375480                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       336065                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       336065                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5711545                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155660                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25278                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5060662                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      5208838                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       336578                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       336578                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5545416                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155884                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1324                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        50132                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    176401096                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    176608212                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14106432                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     14106432                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               190714644                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           622043                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3659684                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        50556                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    168740232                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    168947996                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14122752                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total     14122752                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               183070748                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           632037                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3551920                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3659684    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3551920    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3659684                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           109555497                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3551920                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           109974000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               33484                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            20982498                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            21181500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         11300972211                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy         10917620106                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         6484776493                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         6186347625                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          151978377                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          152234718                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -3088,45 +3100,45 @@
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq            5072106                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           5064869                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38187                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38187                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          2487202                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq       936242                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp       829317                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          482057                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        299353                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         781410                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq          127                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp          127                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           300573                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          300573                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8029813                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6984147                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              15013960                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    269549433                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    226408539                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              495957972                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1618057                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          9487188                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.012211                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.109827                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq            4966231                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           4959010                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38330                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38330                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          2396374                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq       933256                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp       826108                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          485771                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        304174                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         789945                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          119                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          119                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           295867                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          295867                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      7796872                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6899953                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              14696825                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    260005833                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    222466259                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              482472092                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         1634381                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          9291173                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.012493                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.111071                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                9371339     98.78%     98.78% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 115849      1.22%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                9175099     98.75%     98.75% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 116074      1.25%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            9487188                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         8381122122                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            9291173                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         8184497542                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2527500                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2554500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        4575963989                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        4445775595                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4435446795                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4394903352                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index 4c75131..18eb625 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -4,11 +4,11 @@
 sim_ticks                                1962612686500                       # Number of ticks simulated
 final_tick                               1962612686500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1121045                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1121044                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            36128483856                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 373592                       # Number of bytes of host memory used
-host_seconds                                    54.32                       # Real time elapsed on the host
+host_inst_rate                                1051716                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1051715                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            33894179183                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 374244                       # Number of bytes of host memory used
+host_seconds                                    57.90                       # Real time elapsed on the host
 sim_insts                                    60898638                       # Number of instructions simulated
 sim_ops                                      60898638                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -271,12 +271,12 @@
 system.physmem.wrPerTurnAround::816-831             1      0.02%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::928-943             1      0.02%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total            4988                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2137453500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9763978500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                     2137457500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9763982500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                   2033740000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5254.98                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        5254.99                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24004.98                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  24004.99                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          13.26                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           4.44                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       13.27                       # Average system read bandwidth in MiByte/s
@@ -298,28 +298,28 @@
 system.physmem_0.readEnergy                1581504600                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                432429840                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy           128188142160                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            66287825100                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1119418909500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1316300550825                       # Total energy per rank (pJ)
+system.physmem_0.actBackEnergy            66287824245                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1119418910250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1316300550720                       # Total energy per rank (pJ)
 system.physmem_0.averagePower              670.688732                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1862013795212                       # Time in different power states
+system.physmem_0.memoryStateTime::IDLE   1862013796212                       # Time in different power states
 system.physmem_0.memoryStateTime::REF     65535860000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     35060566038                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     35060565038                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.physmem_1.actEnergy                  257856480                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                  140695500                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                1591129800                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                450625680                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy           128188142160                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            66523569975                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1119212115750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1316364135345                       # Total energy per rank (pJ)
+system.physmem_1.actBackEnergy            66523575105                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1119212111250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1316364135975                       # Total energy per rank (pJ)
 system.physmem_1.averagePower              670.721130                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1861673243216                       # Time in different power states
+system.physmem_1.memoryStateTime::IDLE   1861673236216                       # Time in different power states
 system.physmem_1.memoryStateTime::REF     65535860000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     35401118034                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     35401125034                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
@@ -542,16 +542,16 @@
 system.cpu0.dcache.overall_misses::total      1190299                       # number of overall misses
 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  29060390999                       # number of ReadReq miss cycles
 system.cpu0.dcache.ReadReq_miss_latency::total  29060390999                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  10906399185                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  10906399185                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  10906402435                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  10906402435                       # number of WriteReq miss cycles
 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    150333500                       # number of LoadLockedReq miss cycles
 system.cpu0.dcache.LoadLockedReq_miss_latency::total    150333500                       # number of LoadLockedReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     48525392                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::total     48525392                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  39966790184                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  39966790184                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  39966790184                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  39966790184                       # number of overall miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  39966793434                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  39966793434                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  39966793434                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  39966793434                       # number of overall miss cycles
 system.cpu0.dcache.ReadReq_accesses::cpu0.data      7350545                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::total      7350545                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::cpu0.data      4910752                       # number of WriteReq accesses(hits+misses)
@@ -578,16 +578,16 @@
 system.cpu0.dcache.overall_miss_rate::total     0.097078                       # miss rate for overall accesses
 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30960.168882                       # average ReadReq miss latency
 system.cpu0.dcache.ReadReq_avg_miss_latency::total 30960.168882                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43337.661318                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 43337.661318                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43337.674232                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 43337.674232                       # average WriteReq miss latency
 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11003.769580                       # average LoadLockedReq miss latency
 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11003.769580                       # average LoadLockedReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  8936.536280                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  8936.536280                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33577.101370                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 33577.101370                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33577.101370                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 33577.101370                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33577.104101                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 33577.104101                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33577.104101                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 33577.104101                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -612,22 +612,22 @@
 system.cpu0.dcache.overall_mshr_misses::total      1190299                       # number of overall MSHR misses
 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  27526583001                       # number of ReadReq MSHR miss cycles
 system.cpu0.dcache.ReadReq_mshr_miss_latency::total  27526583001                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  10476948315                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  10476948315                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  10476952065                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  10476952065                       # number of WriteReq MSHR miss cycles
 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    129828500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    129828500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     40378608                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     40378608                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  38003531316                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  38003531316                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  38003531316                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  38003531316                       # number of overall MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  38003535066                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  38003535066                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  38003535066                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  38003535066                       # number of overall MSHR miss cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1474416000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1474416000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2293895500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2293895500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3768311500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3768311500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2293892500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2293892500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3768308500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3768308500                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.127696                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.127696                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.051247                       # mshr miss rate for WriteReq accesses
@@ -642,16 +642,16 @@
 system.cpu0.dcache.overall_mshr_miss_rate::total     0.097078                       # mshr miss rate for overall accesses
 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29326.090571                       # average ReadReq mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29326.090571                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41631.195596                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41631.195596                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41631.210497                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41631.210497                       # average WriteReq mshr miss latency
 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  9502.891231                       # average LoadLockedReq mshr miss latency
 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  9502.891231                       # average LoadLockedReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  7436.207735                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  7436.207735                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31927.718427                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31927.718427                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31927.718427                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31927.718427                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31927.721578                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31927.721578                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31927.721578                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31927.721578                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -793,8 +793,8 @@
 system.cpu1.num_mem_refs                      4200357                       # number of memory refs
 system.cpu1.num_load_insts                    2433886                       # Number of load instructions
 system.cpu1.num_store_insts                   1766471                       # Number of store instructions
-system.cpu1.num_idle_cycles              3876126897.998025                       # Number of idle cycles
-system.cpu1.num_busy_cycles              49098475.001975                       # Number of busy cycles
+system.cpu1.num_idle_cycles              3876126901.998025                       # Number of idle cycles
+system.cpu1.num_busy_cycles              49098471.001975                       # Number of busy cycles
 system.cpu1.not_idle_fraction                0.012508                       # Percentage of non-idle cycles
 system.cpu1.idle_fraction                    0.987492                       # Percentage of idle cycles
 system.cpu1.Branches                          1871330                       # Number of branches fetched
@@ -945,8 +945,8 @@
 system.cpu1.dcache.ReadReq_miss_latency::total   1427964750                       # number of ReadReq miss cycles
 system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   1264688999                       # number of WriteReq miss cycles
 system.cpu1.dcache.WriteReq_miss_latency::total   1264688999                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     81194500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     81194500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     81193500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     81193500                       # number of LoadLockedReq miss cycles
 system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     50099897                       # number of StoreCondReq miss cycles
 system.cpu1.dcache.StoreCondReq_miss_latency::total     50099897                       # number of StoreCondReq miss cycles
 system.cpu1.dcache.demand_miss_latency::cpu1.data   2692653749                       # number of demand (read+write) miss cycles
@@ -981,8 +981,8 @@
 system.cpu1.dcache.ReadReq_avg_miss_latency::total 12084.600640                       # average ReadReq miss latency
 system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20224.022116                       # average WriteReq miss latency
 system.cpu1.dcache.WriteReq_avg_miss_latency::total 20224.022116                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9108.649316                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9108.649316                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9108.537133                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9108.537133                       # average LoadLockedReq miss latency
 system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8564.084957                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  8564.084957                       # average StoreCondReq miss latency
 system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14901.403164                       # average overall miss latency
@@ -1015,20 +1015,20 @@
 system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1250643250                       # number of ReadReq MSHR miss cycles
 system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1167915001                       # number of WriteReq MSHR miss cycles
 system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1167915001                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     67823500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     67823500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     67822500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     67822500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     41323103                       # number of StoreCondReq MSHR miss cycles
 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     41323103                       # number of StoreCondReq MSHR miss cycles
 system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2418558251                       # number of demand (read+write) MSHR miss cycles
 system.cpu1.dcache.demand_mshr_miss_latency::total   2418558251                       # number of demand (read+write) MSHR miss cycles
 system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2418558251                       # number of overall MSHR miss cycles
 system.cpu1.dcache.overall_mshr_miss_latency::total   2418558251                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     18864000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     18864000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    716373000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    716373000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    735237000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    735237000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     18866000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     18866000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    716370000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    716370000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    735236000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    735236000                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.049791                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.049791                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036730                       # mshr miss rate for WriteReq accesses
@@ -1045,8 +1045,8 @@
 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10583.961697                       # average ReadReq mshr miss latency
 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18676.480011                       # average WriteReq mshr miss latency
 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18676.480011                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7608.649316                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7608.649316                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7608.537133                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7608.537133                       # average LoadLockedReq mshr miss latency
 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  7063.778291                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  7063.778291                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13384.532485                       # average overall mshr miss latency
@@ -1323,7 +1323,7 @@
 system.iocache.overall_avg_mshr_miss_latency::total 72505.074713                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.l2c.tags.replacements                   341367                       # number of replacements
-system.l2c.tags.tagsinuse                65207.739778                       # Cycle average of tags in use
+system.l2c.tags.tagsinuse                65207.739779                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    2440642                       # Total number of references to valid blocks.
 system.l2c.tags.sampled_refs                   406370                       # Sample count of references to valid blocks.
 system.l2c.tags.avg_refs                     6.005960                       # Average number of references to valid blocks.
@@ -1409,19 +1409,19 @@
 system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1334957                       # number of SCUpgradeReq miss cycles
 system.l2c.SCUpgradeReq_miss_latency::cpu1.data       185994                       # number of SCUpgradeReq miss cycles
 system.l2c.SCUpgradeReq_miss_latency::total      1520951                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   8793297261                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   8793301011                       # number of ReadExReq miss cycles
 system.l2c.ReadExReq_miss_latency::cpu1.data    540094736                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   9333391997                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   9333395747                       # number of ReadExReq miss cycles
 system.l2c.demand_miss_latency::cpu0.inst   1052716500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  28494183761                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  28494187511                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu1.inst     37366250                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu1.data    558586986                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     30142853497                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     30142857247                       # number of demand (read+write) miss cycles
 system.l2c.overall_miss_latency::cpu0.inst   1052716500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  28494183761                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  28494187511                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu1.inst     37366250                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu1.data    558586986                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    30142853497                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    30142857247                       # number of overall miss cycles
 system.l2c.ReadReq_accesses::cpu0.inst         699367                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu0.data         936074                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.inst         316201                       # number of ReadReq accesses(hits+misses)
@@ -1483,19 +1483,19 @@
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1496.588565                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   207.351171                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::total   850.168250                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76048.823034                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76048.855466                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81969.151009                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 76368.004165                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 76368.034848                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu0.inst 80544.491201                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 73578.378934                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 73578.388617                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.inst 81764.223195                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.data 81868.237725                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 73949.686337                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 73949.695537                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.inst 80544.491201                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 73578.378934                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 73578.388617                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.inst 81764.223195                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.data 81868.237725                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 73949.686337                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 73949.695537                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1550,28 +1550,28 @@
 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     15769892                       # number of SCUpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     15706897                       # number of SCUpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::total     31476789                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   7347142739                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   7347146989                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    457723764                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   7804866503                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   7804870753                       # number of ReadExReq MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.inst    888765750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  23652210239                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  23652214489                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.inst     31138500                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.data    473285514                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  25045400003                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  25045404253                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.inst    888765750                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  23652210239                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  23652214489                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.inst     31138500                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.data    473285514                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  25045400003                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  25045404253                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1374876000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     17618000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   1392494000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2153053500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    674538500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   2827592000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3527929500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    692156500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   4220086000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     17620000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   1392496000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2153050500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    674536000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2827586500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3527926500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    692156000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   4220082500                       # number of overall MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.018684                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.290186                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.001420                       # mshr miss rate for ReadReq accesses
@@ -1607,19 +1607,19 @@
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17679.251121                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17510.476031                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17594.627725                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 63541.757020                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 63541.793777                       # average ReadExReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69467.865230                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 63861.249779                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 63861.284554                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68016.051886                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61075.316359                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61075.327333                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69350.779510                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69366.189946                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 61445.724022                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 61445.734449                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68016.051886                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61075.316359                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61075.327333                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69350.779510                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69366.189946                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 61445.724022                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 61445.734449                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1666,11 +1666,11 @@
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::total              597341                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            40208500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy            40208000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy          1232118814                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2189522527                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2189522277                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.membus.respLayer2.occupancy           42501500                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
@@ -1715,7 +1715,7 @@
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
 system.toL2Bus.respLayer0.occupancy        1051604997                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1901998576                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1901998326                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
 system.toL2Bus.respLayer2.occupancy         474390739                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
index 4a7304d..1b65661 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
@@ -1,195 +1,195 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000729                       # Number of seconds simulated
-sim_ticks                                   728722500                       # Number of ticks simulated
-final_tick                                  728722500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000730                       # Number of seconds simulated
+sim_ticks                                   729906500                       # Number of ticks simulated
+final_tick                                  729906500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                              162031375                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 277108                       # Number of bytes of host memory used
-host_seconds                                     4.50                       # Real time elapsed on the host
+host_tick_rate                              158517498                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 277860                       # Number of bytes of host memory used
+host_seconds                                     4.60                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0                 79470                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1                 78418                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2                 80729                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3                 80022                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4                 80096                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5                 78976                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6                 78470                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7                 78262                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               634443                       # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks       400000                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0               5381                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1               5444                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2               5473                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3               5390                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4               5369                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5               5494                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6               5433                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7               5395                       # Number of bytes written to this memory
-system.physmem.bytes_written::total            443379                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0                  11115                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1                  10882                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2                  10862                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3                  11100                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4                  10733                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5                  10873                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6                  10934                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7                  11041                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 87540                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks            6250                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0                  5381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1                  5444                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2                  5473                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3                  5390                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4                  5369                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5                  5494                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6                  5433                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7                  5395                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                49629                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0                109053858                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1                107610236                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2                110781539                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3                109811348                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4                109912896                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5                108375959                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6                107681593                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7                107396162                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               870623591                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         548905791                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0                 7384155                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1                 7470608                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2                 7510403                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3                 7396506                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4                 7367688                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5                 7539221                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6                 7455513                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7                 7403367                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              608433251                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         548905791                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0               116438013                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1               115080844                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2               118291942                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3               117207853                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4               117280583                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5               115915180                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6               115137106                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7               114799529                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1479056843                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0                 76606                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1                 79713                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2                 76745                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3                 78087                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4                 75189                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5                 77277                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6                 77630                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7                 79795                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               621042                       # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks       386688                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0               5350                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1               5335                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2               5338                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3               5543                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4               5464                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5               5476                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6               5444                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7               5451                       # Number of bytes written to this memory
+system.physmem.bytes_written::total            430089                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0                  10897                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1                  11106                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2                  10910                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3                  10803                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4                  10929                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5                  10812                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6                  10850                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7                  10810                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 87117                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks            6042                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0                  5350                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1                  5335                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2                  5338                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3                  5543                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4                  5464                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5                  5476                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6                  5444                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7                  5451                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                49443                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0                104953169                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1                109209878                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2                105143604                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3                106982196                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4                103011824                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5                105872464                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6                106356088                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7                109322221                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               850851445                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         529777444                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0                 7329706                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1                 7309155                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2                 7313265                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3                 7594123                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4                 7485890                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5                 7502331                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6                 7458490                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7                 7468080                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              589238485                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         529777444                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0               112282875                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1               116519034                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2               112456869                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3               114576319                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4               110497714                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5               113374795                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6               113814578                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7               116790301                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1440089929                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.num_reads                          100000                       # number of read accesses completed
-system.cpu0.num_writes                          54791                       # number of write accesses completed
-system.cpu0.l1c.tags.replacements               22240                       # number of replacements
-system.cpu0.l1c.tags.tagsinuse             394.087405                       # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs                 13441                       # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs               22636                       # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs                0.593789                       # Average number of references to valid blocks.
+system.cpu0.num_reads                           99153                       # number of read accesses completed
+system.cpu0.num_writes                          54942                       # number of write accesses completed
+system.cpu0.l1c.tags.replacements               22508                       # number of replacements
+system.cpu0.l1c.tags.tagsinuse             393.884164                       # Cycle average of tags in use
+system.cpu0.l1c.tags.total_refs                 13343                       # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs               22908                       # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs                0.582460                       # Average number of references to valid blocks.
 system.cpu0.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0      394.087405                       # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0       0.769702                       # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total      0.769702                       # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_task_id_blocks::1024          396                       # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::0          367                       # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::1           29                       # Occupied blocks per task id
-system.cpu0.l1c.tags.occ_task_id_percent::1024     0.773438                       # Percentage of cache occupancy per task id
-system.cpu0.l1c.tags.tag_accesses              337290                       # Number of tag accesses
-system.cpu0.l1c.tags.data_accesses             337290                       # Number of data accesses
-system.cpu0.l1c.ReadReq_hits::cpu0               8682                       # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total              8682                       # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0              1111                       # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total             1111                       # number of WriteReq hits
-system.cpu0.l1c.demand_hits::cpu0                9793                       # number of demand (read+write) hits
-system.cpu0.l1c.demand_hits::total               9793                       # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0               9793                       # number of overall hits
-system.cpu0.l1c.overall_hits::total              9793                       # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0            36727                       # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total           36727                       # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0           23639                       # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total          23639                       # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0             60366                       # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total            60366                       # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0            60366                       # number of overall misses
-system.cpu0.l1c.overall_misses::total           60366                       # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0   1016702315                       # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total   1016702315                       # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0    918792240                       # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total    918792240                       # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency::cpu0   1935494555                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_latency::total   1935494555                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency::cpu0   1935494555                       # number of overall miss cycles
-system.cpu0.l1c.overall_miss_latency::total   1935494555                       # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0          45409                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total         45409                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0         24750                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total        24750                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses::cpu0           70159                       # number of demand (read+write) accesses
-system.cpu0.l1c.demand_accesses::total          70159                       # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses::cpu0          70159                       # number of overall (read+write) accesses
-system.cpu0.l1c.overall_accesses::total         70159                       # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.808804                       # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total     0.808804                       # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.955111                       # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total     0.955111                       # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0       0.860417                       # miss rate for demand accesses
-system.cpu0.l1c.demand_miss_rate::total      0.860417                       # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate::cpu0      0.860417                       # miss rate for overall accesses
-system.cpu0.l1c.overall_miss_rate::total     0.860417                       # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 27682.694339                       # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 27682.694339                       # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 38867.644147                       # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 38867.644147                       # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 32062.660355                       # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 32062.660355                       # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 32062.660355                       # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 32062.660355                       # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs      1074391                       # number of cycles access was blocked
+system.cpu0.l1c.tags.occ_blocks::cpu0      393.884164                       # Average occupied blocks per requestor
+system.cpu0.l1c.tags.occ_percent::cpu0       0.769305                       # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_percent::total      0.769305                       # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_task_id_blocks::1024          400                       # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::0          366                       # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::1           34                       # Occupied blocks per task id
+system.cpu0.l1c.tags.occ_task_id_percent::1024     0.781250                       # Percentage of cache occupancy per task id
+system.cpu0.l1c.tags.tag_accesses              337372                       # Number of tag accesses
+system.cpu0.l1c.tags.data_accesses             337372                       # Number of data accesses
+system.cpu0.l1c.ReadReq_hits::cpu0               8651                       # number of ReadReq hits
+system.cpu0.l1c.ReadReq_hits::total              8651                       # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits::cpu0              1083                       # number of WriteReq hits
+system.cpu0.l1c.WriteReq_hits::total             1083                       # number of WriteReq hits
+system.cpu0.l1c.demand_hits::cpu0                9734                       # number of demand (read+write) hits
+system.cpu0.l1c.demand_hits::total               9734                       # number of demand (read+write) hits
+system.cpu0.l1c.overall_hits::cpu0               9734                       # number of overall hits
+system.cpu0.l1c.overall_hits::total              9734                       # number of overall hits
+system.cpu0.l1c.ReadReq_misses::cpu0            36335                       # number of ReadReq misses
+system.cpu0.l1c.ReadReq_misses::total           36335                       # number of ReadReq misses
+system.cpu0.l1c.WriteReq_misses::cpu0           24086                       # number of WriteReq misses
+system.cpu0.l1c.WriteReq_misses::total          24086                       # number of WriteReq misses
+system.cpu0.l1c.demand_misses::cpu0             60421                       # number of demand (read+write) misses
+system.cpu0.l1c.demand_misses::total            60421                       # number of demand (read+write) misses
+system.cpu0.l1c.overall_misses::cpu0            60421                       # number of overall misses
+system.cpu0.l1c.overall_misses::total           60421                       # number of overall misses
+system.cpu0.l1c.ReadReq_miss_latency::cpu0   1008804376                       # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_latency::total   1008804376                       # number of ReadReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::cpu0    935467464                       # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::total    935467464                       # number of WriteReq miss cycles
+system.cpu0.l1c.demand_miss_latency::cpu0   1944271840                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_latency::total   1944271840                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.overall_miss_latency::cpu0   1944271840                       # number of overall miss cycles
+system.cpu0.l1c.overall_miss_latency::total   1944271840                       # number of overall miss cycles
+system.cpu0.l1c.ReadReq_accesses::cpu0          44986                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_accesses::total         44986                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::cpu0         25169                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::total        25169                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.demand_accesses::cpu0           70155                       # number of demand (read+write) accesses
+system.cpu0.l1c.demand_accesses::total          70155                       # number of demand (read+write) accesses
+system.cpu0.l1c.overall_accesses::cpu0          70155                       # number of overall (read+write) accesses
+system.cpu0.l1c.overall_accesses::total         70155                       # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.807696                       # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_miss_rate::total     0.807696                       # miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.956971                       # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::total     0.956971                       # miss rate for WriteReq accesses
+system.cpu0.l1c.demand_miss_rate::cpu0       0.861250                       # miss rate for demand accesses
+system.cpu0.l1c.demand_miss_rate::total      0.861250                       # miss rate for demand accesses
+system.cpu0.l1c.overall_miss_rate::cpu0      0.861250                       # miss rate for overall accesses
+system.cpu0.l1c.overall_miss_rate::total     0.861250                       # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 27763.984478                       # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_miss_latency::total 27763.984478                       # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 38838.639209                       # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::total 38838.639209                       # average WriteReq miss latency
+system.cpu0.l1c.demand_avg_miss_latency::cpu0 32178.743152                       # average overall miss latency
+system.cpu0.l1c.demand_avg_miss_latency::total 32178.743152                       # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 32178.743152                       # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::total 32178.743152                       # average overall miss latency
+system.cpu0.l1c.blocked_cycles::no_mshrs      1068204                       # number of cycles access was blocked
 system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs               61970                       # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs               61717                       # number of cycles access was blocked
 system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs    17.337276                       # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs    17.308100                       # average number of cycles each access was blocked
 system.cpu0.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks           9656                       # number of writebacks
-system.cpu0.l1c.writebacks::total                9656                       # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36727                       # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total        36727                       # number of ReadReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23639                       # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::total        23639                       # number of WriteReq MSHR misses
-system.cpu0.l1c.demand_mshr_misses::cpu0        60366                       # number of demand (read+write) MSHR misses
-system.cpu0.l1c.demand_mshr_misses::total        60366                       # number of demand (read+write) MSHR misses
-system.cpu0.l1c.overall_mshr_misses::cpu0        60366                       # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_misses::total        60366                       # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    960514497                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total    960514497                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    882874166                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total    882874166                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1843388663                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::total   1843388663                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1843388663                       # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total   1843388663                       # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    755586835                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    755586835                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0   1939842714                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total   1939842714                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   2695429549                       # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total   2695429549                       # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.808804                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.808804                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.955111                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.955111                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.860417                       # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_miss_rate::total     0.860417                       # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.860417                       # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total     0.860417                       # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 26152.816647                       # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 26152.816647                       # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 37348.202800                       # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 37348.202800                       # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 30536.869480                       # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 30536.869480                       # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 30536.869480                       # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 30536.869480                       # average overall mshr miss latency
+system.cpu0.l1c.writebacks::writebacks           9915                       # number of writebacks
+system.cpu0.l1c.writebacks::total                9915                       # number of writebacks
+system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36335                       # number of ReadReq MSHR misses
+system.cpu0.l1c.ReadReq_mshr_misses::total        36335                       # number of ReadReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::cpu0        24086                       # number of WriteReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::total        24086                       # number of WriteReq MSHR misses
+system.cpu0.l1c.demand_mshr_misses::cpu0        60421                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.demand_mshr_misses::total        60421                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.overall_mshr_misses::cpu0        60421                       # number of overall MSHR misses
+system.cpu0.l1c.overall_mshr_misses::total        60421                       # number of overall MSHR misses
+system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    953224016                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_miss_latency::total    953224016                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    898871386                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::total    898871386                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1852095402                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::total   1852095402                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1852095402                       # number of overall MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::total   1852095402                       # number of overall MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    743740324                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    743740324                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0   1921383275                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total   1921383275                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   2665123599                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::total   2665123599                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.807696                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.807696                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.956971                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.956971                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.861250                       # mshr miss rate for demand accesses
+system.cpu0.l1c.demand_mshr_miss_rate::total     0.861250                       # mshr miss rate for demand accesses
+system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.861250                       # mshr miss rate for overall accesses
+system.cpu0.l1c.overall_mshr_miss_rate::total     0.861250                       # mshr miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 26234.319967                       # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 26234.319967                       # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 37319.247115                       # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 37319.247115                       # average WriteReq mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 30653.173599                       # average overall mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::total 30653.173599                       # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 30653.173599                       # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::total 30653.173599                       # average overall mshr miss latency
 system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average WriteReq mshr uncacheable latency
@@ -197,119 +197,119 @@
 system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0          inf                       # average overall mshr uncacheable latency
 system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu1.num_reads                           99410                       # number of read accesses completed
-system.cpu1.num_writes                          55132                       # number of write accesses completed
-system.cpu1.l1c.tags.replacements               22295                       # number of replacements
-system.cpu1.l1c.tags.tagsinuse             393.820804                       # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs                 13496                       # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs               22679                       # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs                0.595088                       # Average number of references to valid blocks.
+system.cpu1.num_reads                          100000                       # number of read accesses completed
+system.cpu1.num_writes                          54938                       # number of write accesses completed
+system.cpu1.l1c.tags.replacements               22377                       # number of replacements
+system.cpu1.l1c.tags.tagsinuse             394.468790                       # Cycle average of tags in use
+system.cpu1.l1c.tags.total_refs                 13456                       # Total number of references to valid blocks.
+system.cpu1.l1c.tags.sampled_refs               22785                       # Sample count of references to valid blocks.
+system.cpu1.l1c.tags.avg_refs                0.590564                       # Average number of references to valid blocks.
 system.cpu1.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1      393.820804                       # Average occupied blocks per requestor
-system.cpu1.l1c.tags.occ_percent::cpu1       0.769181                       # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_percent::total      0.769181                       # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_task_id_blocks::1024          384                       # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::0          343                       # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::1           41                       # Occupied blocks per task id
-system.cpu1.l1c.tags.occ_task_id_percent::1024     0.750000                       # Percentage of cache occupancy per task id
-system.cpu1.l1c.tags.tag_accesses              338268                       # Number of tag accesses
-system.cpu1.l1c.tags.data_accesses             338268                       # Number of data accesses
-system.cpu1.l1c.ReadReq_hits::cpu1               8726                       # number of ReadReq hits
-system.cpu1.l1c.ReadReq_hits::total              8726                       # number of ReadReq hits
-system.cpu1.l1c.WriteReq_hits::cpu1              1171                       # number of WriteReq hits
-system.cpu1.l1c.WriteReq_hits::total             1171                       # number of WriteReq hits
-system.cpu1.l1c.demand_hits::cpu1                9897                       # number of demand (read+write) hits
-system.cpu1.l1c.demand_hits::total               9897                       # number of demand (read+write) hits
-system.cpu1.l1c.overall_hits::cpu1               9897                       # number of overall hits
-system.cpu1.l1c.overall_hits::total              9897                       # number of overall hits
-system.cpu1.l1c.ReadReq_misses::cpu1            36573                       # number of ReadReq misses
-system.cpu1.l1c.ReadReq_misses::total           36573                       # number of ReadReq misses
-system.cpu1.l1c.WriteReq_misses::cpu1           23897                       # number of WriteReq misses
-system.cpu1.l1c.WriteReq_misses::total          23897                       # number of WriteReq misses
-system.cpu1.l1c.demand_misses::cpu1             60470                       # number of demand (read+write) misses
-system.cpu1.l1c.demand_misses::total            60470                       # number of demand (read+write) misses
-system.cpu1.l1c.overall_misses::cpu1            60470                       # number of overall misses
-system.cpu1.l1c.overall_misses::total           60470                       # number of overall misses
-system.cpu1.l1c.ReadReq_miss_latency::cpu1   1020722242                       # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_latency::total   1020722242                       # number of ReadReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::cpu1    921634198                       # number of WriteReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::total    921634198                       # number of WriteReq miss cycles
-system.cpu1.l1c.demand_miss_latency::cpu1   1942356440                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.demand_miss_latency::total   1942356440                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.overall_miss_latency::cpu1   1942356440                       # number of overall miss cycles
-system.cpu1.l1c.overall_miss_latency::total   1942356440                       # number of overall miss cycles
-system.cpu1.l1c.ReadReq_accesses::cpu1          45299                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_accesses::total         45299                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::cpu1         25068                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::total        25068                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.demand_accesses::cpu1           70367                       # number of demand (read+write) accesses
-system.cpu1.l1c.demand_accesses::total          70367                       # number of demand (read+write) accesses
-system.cpu1.l1c.overall_accesses::cpu1          70367                       # number of overall (read+write) accesses
-system.cpu1.l1c.overall_accesses::total         70367                       # number of overall (read+write) accesses
-system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.807369                       # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_miss_rate::total     0.807369                       # miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.953287                       # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::total     0.953287                       # miss rate for WriteReq accesses
-system.cpu1.l1c.demand_miss_rate::cpu1       0.859352                       # miss rate for demand accesses
-system.cpu1.l1c.demand_miss_rate::total      0.859352                       # miss rate for demand accesses
-system.cpu1.l1c.overall_miss_rate::cpu1      0.859352                       # miss rate for overall accesses
-system.cpu1.l1c.overall_miss_rate::total     0.859352                       # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 27909.174582                       # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 27909.174582                       # average ReadReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 38566.941373                       # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::total 38566.941373                       # average WriteReq miss latency
-system.cpu1.l1c.demand_avg_miss_latency::cpu1 32120.992889                       # average overall miss latency
-system.cpu1.l1c.demand_avg_miss_latency::total 32120.992889                       # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 32120.992889                       # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 32120.992889                       # average overall miss latency
-system.cpu1.l1c.blocked_cycles::no_mshrs      1066797                       # number of cycles access was blocked
+system.cpu1.l1c.tags.occ_blocks::cpu1      394.468790                       # Average occupied blocks per requestor
+system.cpu1.l1c.tags.occ_percent::cpu1       0.770447                       # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_percent::total      0.770447                       # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_task_id_blocks::1024          408                       # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::0          378                       # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::1           30                       # Occupied blocks per task id
+system.cpu1.l1c.tags.occ_task_id_percent::1024     0.796875                       # Percentage of cache occupancy per task id
+system.cpu1.l1c.tags.tag_accesses              338150                       # Number of tag accesses
+system.cpu1.l1c.tags.data_accesses             338150                       # Number of data accesses
+system.cpu1.l1c.ReadReq_hits::cpu1               8709                       # number of ReadReq hits
+system.cpu1.l1c.ReadReq_hits::total              8709                       # number of ReadReq hits
+system.cpu1.l1c.WriteReq_hits::cpu1              1179                       # number of WriteReq hits
+system.cpu1.l1c.WriteReq_hits::total             1179                       # number of WriteReq hits
+system.cpu1.l1c.demand_hits::cpu1                9888                       # number of demand (read+write) hits
+system.cpu1.l1c.demand_hits::total               9888                       # number of demand (read+write) hits
+system.cpu1.l1c.overall_hits::cpu1               9888                       # number of overall hits
+system.cpu1.l1c.overall_hits::total              9888                       # number of overall hits
+system.cpu1.l1c.ReadReq_misses::cpu1            36587                       # number of ReadReq misses
+system.cpu1.l1c.ReadReq_misses::total           36587                       # number of ReadReq misses
+system.cpu1.l1c.WriteReq_misses::cpu1           23856                       # number of WriteReq misses
+system.cpu1.l1c.WriteReq_misses::total          23856                       # number of WriteReq misses
+system.cpu1.l1c.demand_misses::cpu1             60443                       # number of demand (read+write) misses
+system.cpu1.l1c.demand_misses::total            60443                       # number of demand (read+write) misses
+system.cpu1.l1c.overall_misses::cpu1            60443                       # number of overall misses
+system.cpu1.l1c.overall_misses::total           60443                       # number of overall misses
+system.cpu1.l1c.ReadReq_miss_latency::cpu1   1017715976                       # number of ReadReq miss cycles
+system.cpu1.l1c.ReadReq_miss_latency::total   1017715976                       # number of ReadReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::cpu1    924313604                       # number of WriteReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::total    924313604                       # number of WriteReq miss cycles
+system.cpu1.l1c.demand_miss_latency::cpu1   1942029580                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.demand_miss_latency::total   1942029580                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.overall_miss_latency::cpu1   1942029580                       # number of overall miss cycles
+system.cpu1.l1c.overall_miss_latency::total   1942029580                       # number of overall miss cycles
+system.cpu1.l1c.ReadReq_accesses::cpu1          45296                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_accesses::total         45296                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::cpu1         25035                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::total        25035                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.demand_accesses::cpu1           70331                       # number of demand (read+write) accesses
+system.cpu1.l1c.demand_accesses::total          70331                       # number of demand (read+write) accesses
+system.cpu1.l1c.overall_accesses::cpu1          70331                       # number of overall (read+write) accesses
+system.cpu1.l1c.overall_accesses::total         70331                       # number of overall (read+write) accesses
+system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.807731                       # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_miss_rate::total     0.807731                       # miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.952906                       # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::total     0.952906                       # miss rate for WriteReq accesses
+system.cpu1.l1c.demand_miss_rate::cpu1       0.859408                       # miss rate for demand accesses
+system.cpu1.l1c.demand_miss_rate::total      0.859408                       # miss rate for demand accesses
+system.cpu1.l1c.overall_miss_rate::cpu1      0.859408                       # miss rate for overall accesses
+system.cpu1.l1c.overall_miss_rate::total     0.859408                       # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 27816.327548                       # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 27816.327548                       # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 38745.540074                       # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::total 38745.540074                       # average WriteReq miss latency
+system.cpu1.l1c.demand_avg_miss_latency::cpu1 32129.933657                       # average overall miss latency
+system.cpu1.l1c.demand_avg_miss_latency::total 32129.933657                       # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 32129.933657                       # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 32129.933657                       # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs      1075887                       # number of cycles access was blocked
 system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs               61607                       # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs               62059                       # number of cycles access was blocked
 system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs    17.316165                       # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs    17.336518                       # average number of cycles each access was blocked
 system.cpu1.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks           9694                       # number of writebacks
-system.cpu1.l1c.writebacks::total                9694                       # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36573                       # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total        36573                       # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23897                       # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total        23897                       # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1        60470                       # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total        60470                       # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1        60470                       # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total        60470                       # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    964784026                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total    964784026                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    885327122                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total    885327122                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1850111148                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total   1850111148                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1850111148                       # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total   1850111148                       # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    740106955                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    740106955                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1   1954561172                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total   1954561172                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   2694668127                       # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total   2694668127                       # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.807369                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.807369                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.953287                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.953287                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.859352                       # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_miss_rate::total     0.859352                       # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.859352                       # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total     0.859352                       # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 26379.679709                       # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 26379.679709                       # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37047.626146                       # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 37047.626146                       # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 30595.520886                       # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 30595.520886                       # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 30595.520886                       # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 30595.520886                       # average overall mshr miss latency
+system.cpu1.l1c.writebacks::writebacks           9753                       # number of writebacks
+system.cpu1.l1c.writebacks::total                9753                       # number of writebacks
+system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36587                       # number of ReadReq MSHR misses
+system.cpu1.l1c.ReadReq_mshr_misses::total        36587                       # number of ReadReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23856                       # number of WriteReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::total        23856                       # number of WriteReq MSHR misses
+system.cpu1.l1c.demand_mshr_misses::cpu1        60443                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.demand_mshr_misses::total        60443                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.overall_mshr_misses::cpu1        60443                       # number of overall MSHR misses
+system.cpu1.l1c.overall_mshr_misses::total        60443                       # number of overall MSHR misses
+system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    961736168                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_miss_latency::total    961736168                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    888050076                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::total    888050076                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1849786244                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::total   1849786244                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1849786244                       # number of overall MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::total   1849786244                       # number of overall MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    753708733                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    753708733                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1   1923800282                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total   1923800282                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   2677509015                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::total   2677509015                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.807731                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.807731                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.952906                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.952906                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.859408                       # mshr miss rate for demand accesses
+system.cpu1.l1c.demand_mshr_miss_rate::total     0.859408                       # mshr miss rate for demand accesses
+system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.859408                       # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_miss_rate::total     0.859408                       # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 26286.281138                       # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 26286.281138                       # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37225.439135                       # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 37225.439135                       # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 30603.812584                       # average overall mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::total 30603.812584                       # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 30603.812584                       # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::total 30603.812584                       # average overall mshr miss latency
 system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average WriteReq mshr uncacheable latency
@@ -317,119 +317,119 @@
 system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1          inf                       # average overall mshr uncacheable latency
 system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu2.num_reads                           99274                       # number of read accesses completed
-system.cpu2.num_writes                          54884                       # number of write accesses completed
-system.cpu2.l1c.tags.replacements               22456                       # number of replacements
-system.cpu2.l1c.tags.tagsinuse             393.843880                       # Cycle average of tags in use
-system.cpu2.l1c.tags.total_refs                 13581                       # Total number of references to valid blocks.
-system.cpu2.l1c.tags.sampled_refs               22857                       # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs                0.594172                       # Average number of references to valid blocks.
+system.cpu2.num_reads                           99515                       # number of read accesses completed
+system.cpu2.num_writes                          55356                       # number of write accesses completed
+system.cpu2.l1c.tags.replacements               22413                       # number of replacements
+system.cpu2.l1c.tags.tagsinuse             394.491739                       # Cycle average of tags in use
+system.cpu2.l1c.tags.total_refs                 13448                       # Total number of references to valid blocks.
+system.cpu2.l1c.tags.sampled_refs               22815                       # Sample count of references to valid blocks.
+system.cpu2.l1c.tags.avg_refs                0.589437                       # Average number of references to valid blocks.
 system.cpu2.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.tags.occ_blocks::cpu2      393.843880                       # Average occupied blocks per requestor
-system.cpu2.l1c.tags.occ_percent::cpu2       0.769226                       # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_percent::total      0.769226                       # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_task_id_blocks::1024          401                       # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::0          373                       # Occupied blocks per task id
+system.cpu2.l1c.tags.occ_blocks::cpu2      394.491739                       # Average occupied blocks per requestor
+system.cpu2.l1c.tags.occ_percent::cpu2       0.770492                       # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_percent::total      0.770492                       # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::0          374                       # Occupied blocks per task id
 system.cpu2.l1c.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
-system.cpu2.l1c.tags.occ_task_id_percent::1024     0.783203                       # Percentage of cache occupancy per task id
-system.cpu2.l1c.tags.tag_accesses              337451                       # Number of tag accesses
-system.cpu2.l1c.tags.data_accesses             337451                       # Number of data accesses
-system.cpu2.l1c.ReadReq_hits::cpu2               8813                       # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total              8813                       # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2              1134                       # number of WriteReq hits
-system.cpu2.l1c.WriteReq_hits::total             1134                       # number of WriteReq hits
-system.cpu2.l1c.demand_hits::cpu2                9947                       # number of demand (read+write) hits
-system.cpu2.l1c.demand_hits::total               9947                       # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits::cpu2               9947                       # number of overall hits
-system.cpu2.l1c.overall_hits::total              9947                       # number of overall hits
-system.cpu2.l1c.ReadReq_misses::cpu2            36457                       # number of ReadReq misses
-system.cpu2.l1c.ReadReq_misses::total           36457                       # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses::cpu2           23816                       # number of WriteReq misses
-system.cpu2.l1c.WriteReq_misses::total          23816                       # number of WriteReq misses
-system.cpu2.l1c.demand_misses::cpu2             60273                       # number of demand (read+write) misses
-system.cpu2.l1c.demand_misses::total            60273                       # number of demand (read+write) misses
-system.cpu2.l1c.overall_misses::cpu2            60273                       # number of overall misses
-system.cpu2.l1c.overall_misses::total           60273                       # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency::cpu2   1014308258                       # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_latency::total   1014308258                       # number of ReadReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::cpu2    924910230                       # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::total    924910230                       # number of WriteReq miss cycles
-system.cpu2.l1c.demand_miss_latency::cpu2   1939218488                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_latency::total   1939218488                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.overall_miss_latency::cpu2   1939218488                       # number of overall miss cycles
-system.cpu2.l1c.overall_miss_latency::total   1939218488                       # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2          45270                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_accesses::total         45270                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::cpu2         24950                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::total        24950                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.demand_accesses::cpu2           70220                       # number of demand (read+write) accesses
-system.cpu2.l1c.demand_accesses::total          70220                       # number of demand (read+write) accesses
-system.cpu2.l1c.overall_accesses::cpu2          70220                       # number of overall (read+write) accesses
-system.cpu2.l1c.overall_accesses::total         70220                       # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.805324                       # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_miss_rate::total     0.805324                       # miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.954549                       # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::total     0.954549                       # miss rate for WriteReq accesses
-system.cpu2.l1c.demand_miss_rate::cpu2       0.858345                       # miss rate for demand accesses
-system.cpu2.l1c.demand_miss_rate::total      0.858345                       # miss rate for demand accesses
-system.cpu2.l1c.overall_miss_rate::cpu2      0.858345                       # miss rate for overall accesses
-system.cpu2.l1c.overall_miss_rate::total     0.858345                       # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 27822.043997                       # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 27822.043997                       # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 38835.666359                       # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 38835.666359                       # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency::cpu2 32173.916812                       # average overall miss latency
-system.cpu2.l1c.demand_avg_miss_latency::total 32173.916812                       # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 32173.916812                       # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 32173.916812                       # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs      1061117                       # number of cycles access was blocked
+system.cpu2.l1c.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
+system.cpu2.l1c.tags.tag_accesses              338294                       # Number of tag accesses
+system.cpu2.l1c.tags.data_accesses             338294                       # Number of data accesses
+system.cpu2.l1c.ReadReq_hits::cpu2               8726                       # number of ReadReq hits
+system.cpu2.l1c.ReadReq_hits::total              8726                       # number of ReadReq hits
+system.cpu2.l1c.WriteReq_hits::cpu2              1175                       # number of WriteReq hits
+system.cpu2.l1c.WriteReq_hits::total             1175                       # number of WriteReq hits
+system.cpu2.l1c.demand_hits::cpu2                9901                       # number of demand (read+write) hits
+system.cpu2.l1c.demand_hits::total               9901                       # number of demand (read+write) hits
+system.cpu2.l1c.overall_hits::cpu2               9901                       # number of overall hits
+system.cpu2.l1c.overall_hits::total              9901                       # number of overall hits
+system.cpu2.l1c.ReadReq_misses::cpu2            36442                       # number of ReadReq misses
+system.cpu2.l1c.ReadReq_misses::total           36442                       # number of ReadReq misses
+system.cpu2.l1c.WriteReq_misses::cpu2           24017                       # number of WriteReq misses
+system.cpu2.l1c.WriteReq_misses::total          24017                       # number of WriteReq misses
+system.cpu2.l1c.demand_misses::cpu2             60459                       # number of demand (read+write) misses
+system.cpu2.l1c.demand_misses::total            60459                       # number of demand (read+write) misses
+system.cpu2.l1c.overall_misses::cpu2            60459                       # number of overall misses
+system.cpu2.l1c.overall_misses::total           60459                       # number of overall misses
+system.cpu2.l1c.ReadReq_miss_latency::cpu2   1013968188                       # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_latency::total   1013968188                       # number of ReadReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::cpu2    926155084                       # number of WriteReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::total    926155084                       # number of WriteReq miss cycles
+system.cpu2.l1c.demand_miss_latency::cpu2   1940123272                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.demand_miss_latency::total   1940123272                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.overall_miss_latency::cpu2   1940123272                       # number of overall miss cycles
+system.cpu2.l1c.overall_miss_latency::total   1940123272                       # number of overall miss cycles
+system.cpu2.l1c.ReadReq_accesses::cpu2          45168                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_accesses::total         45168                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::cpu2         25192                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::total        25192                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.demand_accesses::cpu2           70360                       # number of demand (read+write) accesses
+system.cpu2.l1c.demand_accesses::total          70360                       # number of demand (read+write) accesses
+system.cpu2.l1c.overall_accesses::cpu2          70360                       # number of overall (read+write) accesses
+system.cpu2.l1c.overall_accesses::total         70360                       # number of overall (read+write) accesses
+system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.806810                       # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_miss_rate::total     0.806810                       # miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.953358                       # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::total     0.953358                       # miss rate for WriteReq accesses
+system.cpu2.l1c.demand_miss_rate::cpu2       0.859281                       # miss rate for demand accesses
+system.cpu2.l1c.demand_miss_rate::total      0.859281                       # miss rate for demand accesses
+system.cpu2.l1c.overall_miss_rate::cpu2      0.859281                       # miss rate for overall accesses
+system.cpu2.l1c.overall_miss_rate::total     0.859281                       # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 27824.164096                       # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_miss_latency::total 27824.164096                       # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 38562.480077                       # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::total 38562.480077                       # average WriteReq miss latency
+system.cpu2.l1c.demand_avg_miss_latency::cpu2 32089.900131                       # average overall miss latency
+system.cpu2.l1c.demand_avg_miss_latency::total 32089.900131                       # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::cpu2 32089.900131                       # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::total 32089.900131                       # average overall miss latency
+system.cpu2.l1c.blocked_cycles::no_mshrs      1067763                       # number of cycles access was blocked
 system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs               61178                       # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_mshrs               61601                       # number of cycles access was blocked
 system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs    17.344748                       # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs    17.333534                       # average number of cycles each access was blocked
 system.cpu2.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks           9940                       # number of writebacks
-system.cpu2.l1c.writebacks::total                9940                       # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36457                       # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total        36457                       # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2        23816                       # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total        23816                       # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses::cpu2        60273                       # number of demand (read+write) MSHR misses
-system.cpu2.l1c.demand_mshr_misses::total        60273                       # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2        60273                       # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total        60273                       # number of overall MSHR misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    958559384                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_latency::total    958559384                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    888663772                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total    888663772                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1847223156                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::total   1847223156                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1847223156                       # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total   1847223156                       # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    735013046                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    735013046                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2   1939097223                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total   1939097223                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   2674110269                       # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total   2674110269                       # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.805324                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.805324                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.954549                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.954549                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.858345                       # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_miss_rate::total     0.858345                       # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.858345                       # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total     0.858345                       # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 26292.876101                       # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 26292.876101                       # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 37313.729090                       # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 37313.729090                       # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 30647.605993                       # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 30647.605993                       # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 30647.605993                       # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 30647.605993                       # average overall mshr miss latency
+system.cpu2.l1c.writebacks::writebacks           9861                       # number of writebacks
+system.cpu2.l1c.writebacks::total                9861                       # number of writebacks
+system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36442                       # number of ReadReq MSHR misses
+system.cpu2.l1c.ReadReq_mshr_misses::total        36442                       # number of ReadReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::cpu2        24017                       # number of WriteReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::total        24017                       # number of WriteReq MSHR misses
+system.cpu2.l1c.demand_mshr_misses::cpu2        60459                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.demand_mshr_misses::total        60459                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.overall_mshr_misses::cpu2        60459                       # number of overall MSHR misses
+system.cpu2.l1c.overall_mshr_misses::total        60459                       # number of overall MSHR misses
+system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    958233322                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_miss_latency::total    958233322                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    889641050                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::total    889641050                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1847874372                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::total   1847874372                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1847874372                       # number of overall MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::total   1847874372                       # number of overall MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    744958366                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    744958366                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2   1919549279                       # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total   1919549279                       # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   2664507645                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::total   2664507645                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.806810                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.806810                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.953358                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.953358                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.859281                       # mshr miss rate for demand accesses
+system.cpu2.l1c.demand_mshr_miss_rate::total     0.859281                       # mshr miss rate for demand accesses
+system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.859281                       # mshr miss rate for overall accesses
+system.cpu2.l1c.overall_mshr_miss_rate::total     0.859281                       # mshr miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 26294.751166                       # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 26294.751166                       # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 37042.138902                       # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 37042.138902                       # average WriteReq mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 30564.090905                       # average overall mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::total 30564.090905                       # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 30564.090905                       # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 30564.090905                       # average overall mshr miss latency
 system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
 system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average WriteReq mshr uncacheable latency
@@ -437,119 +437,119 @@
 system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2          inf                       # average overall mshr uncacheable latency
 system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu3.num_reads                           99869                       # number of read accesses completed
-system.cpu3.num_writes                          54874                       # number of write accesses completed
-system.cpu3.l1c.tags.replacements               22370                       # number of replacements
-system.cpu3.l1c.tags.tagsinuse             393.431339                       # Cycle average of tags in use
-system.cpu3.l1c.tags.total_refs                 13240                       # Total number of references to valid blocks.
-system.cpu3.l1c.tags.sampled_refs               22771                       # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs                0.581441                       # Average number of references to valid blocks.
+system.cpu3.num_reads                           99509                       # number of read accesses completed
+system.cpu3.num_writes                          55322                       # number of write accesses completed
+system.cpu3.l1c.tags.replacements               22357                       # number of replacements
+system.cpu3.l1c.tags.tagsinuse             394.352238                       # Cycle average of tags in use
+system.cpu3.l1c.tags.total_refs                 13564                       # Total number of references to valid blocks.
+system.cpu3.l1c.tags.sampled_refs               22743                       # Sample count of references to valid blocks.
+system.cpu3.l1c.tags.avg_refs                0.596403                       # Average number of references to valid blocks.
 system.cpu3.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.tags.occ_blocks::cpu3      393.431339                       # Average occupied blocks per requestor
-system.cpu3.l1c.tags.occ_percent::cpu3       0.768421                       # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_percent::total      0.768421                       # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_task_id_blocks::1024          401                       # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::0          371                       # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::1           30                       # Occupied blocks per task id
-system.cpu3.l1c.tags.occ_task_id_percent::1024     0.783203                       # Percentage of cache occupancy per task id
-system.cpu3.l1c.tags.tag_accesses              336829                       # Number of tag accesses
-system.cpu3.l1c.tags.data_accesses             336829                       # Number of data accesses
-system.cpu3.l1c.ReadReq_hits::cpu3               8648                       # number of ReadReq hits
-system.cpu3.l1c.ReadReq_hits::total              8648                       # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits::cpu3              1128                       # number of WriteReq hits
-system.cpu3.l1c.WriteReq_hits::total             1128                       # number of WriteReq hits
-system.cpu3.l1c.demand_hits::cpu3                9776                       # number of demand (read+write) hits
-system.cpu3.l1c.demand_hits::total               9776                       # number of demand (read+write) hits
-system.cpu3.l1c.overall_hits::cpu3               9776                       # number of overall hits
-system.cpu3.l1c.overall_hits::total              9776                       # number of overall hits
-system.cpu3.l1c.ReadReq_misses::cpu3            36458                       # number of ReadReq misses
-system.cpu3.l1c.ReadReq_misses::total           36458                       # number of ReadReq misses
-system.cpu3.l1c.WriteReq_misses::cpu3           23788                       # number of WriteReq misses
-system.cpu3.l1c.WriteReq_misses::total          23788                       # number of WriteReq misses
-system.cpu3.l1c.demand_misses::cpu3             60246                       # number of demand (read+write) misses
-system.cpu3.l1c.demand_misses::total            60246                       # number of demand (read+write) misses
-system.cpu3.l1c.overall_misses::cpu3            60246                       # number of overall misses
-system.cpu3.l1c.overall_misses::total           60246                       # number of overall misses
-system.cpu3.l1c.ReadReq_miss_latency::cpu3   1012578921                       # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_latency::total   1012578921                       # number of ReadReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::cpu3    920459168                       # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::total    920459168                       # number of WriteReq miss cycles
-system.cpu3.l1c.demand_miss_latency::cpu3   1933038089                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_latency::total   1933038089                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.overall_miss_latency::cpu3   1933038089                       # number of overall miss cycles
-system.cpu3.l1c.overall_miss_latency::total   1933038089                       # number of overall miss cycles
-system.cpu3.l1c.ReadReq_accesses::cpu3          45106                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_accesses::total         45106                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::cpu3         24916                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::total        24916                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.demand_accesses::cpu3           70022                       # number of demand (read+write) accesses
-system.cpu3.l1c.demand_accesses::total          70022                       # number of demand (read+write) accesses
-system.cpu3.l1c.overall_accesses::cpu3          70022                       # number of overall (read+write) accesses
-system.cpu3.l1c.overall_accesses::total         70022                       # number of overall (read+write) accesses
-system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.808274                       # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_miss_rate::total     0.808274                       # miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.954728                       # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::total     0.954728                       # miss rate for WriteReq accesses
-system.cpu3.l1c.demand_miss_rate::cpu3       0.860387                       # miss rate for demand accesses
-system.cpu3.l1c.demand_miss_rate::total      0.860387                       # miss rate for demand accesses
-system.cpu3.l1c.overall_miss_rate::cpu3      0.860387                       # miss rate for overall accesses
-system.cpu3.l1c.overall_miss_rate::total     0.860387                       # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 27773.847194                       # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_miss_latency::total 27773.847194                       # average ReadReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 38694.264671                       # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::total 38694.264671                       # average WriteReq miss latency
-system.cpu3.l1c.demand_avg_miss_latency::cpu3 32085.749909                       # average overall miss latency
-system.cpu3.l1c.demand_avg_miss_latency::total 32085.749909                       # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 32085.749909                       # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 32085.749909                       # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs      1072737                       # number of cycles access was blocked
+system.cpu3.l1c.tags.occ_blocks::cpu3      394.352238                       # Average occupied blocks per requestor
+system.cpu3.l1c.tags.occ_percent::cpu3       0.770219                       # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_percent::total      0.770219                       # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_task_id_blocks::1024          386                       # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::0          354                       # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::1           32                       # Occupied blocks per task id
+system.cpu3.l1c.tags.occ_task_id_percent::1024     0.753906                       # Percentage of cache occupancy per task id
+system.cpu3.l1c.tags.tag_accesses              338647                       # Number of tag accesses
+system.cpu3.l1c.tags.data_accesses             338647                       # Number of data accesses
+system.cpu3.l1c.ReadReq_hits::cpu3               8763                       # number of ReadReq hits
+system.cpu3.l1c.ReadReq_hits::total              8763                       # number of ReadReq hits
+system.cpu3.l1c.WriteReq_hits::cpu3              1221                       # number of WriteReq hits
+system.cpu3.l1c.WriteReq_hits::total             1221                       # number of WriteReq hits
+system.cpu3.l1c.demand_hits::cpu3                9984                       # number of demand (read+write) hits
+system.cpu3.l1c.demand_hits::total               9984                       # number of demand (read+write) hits
+system.cpu3.l1c.overall_hits::cpu3               9984                       # number of overall hits
+system.cpu3.l1c.overall_hits::total              9984                       # number of overall hits
+system.cpu3.l1c.ReadReq_misses::cpu3            36641                       # number of ReadReq misses
+system.cpu3.l1c.ReadReq_misses::total           36641                       # number of ReadReq misses
+system.cpu3.l1c.WriteReq_misses::cpu3           23832                       # number of WriteReq misses
+system.cpu3.l1c.WriteReq_misses::total          23832                       # number of WriteReq misses
+system.cpu3.l1c.demand_misses::cpu3             60473                       # number of demand (read+write) misses
+system.cpu3.l1c.demand_misses::total            60473                       # number of demand (read+write) misses
+system.cpu3.l1c.overall_misses::cpu3            60473                       # number of overall misses
+system.cpu3.l1c.overall_misses::total           60473                       # number of overall misses
+system.cpu3.l1c.ReadReq_miss_latency::cpu3   1024295614                       # number of ReadReq miss cycles
+system.cpu3.l1c.ReadReq_miss_latency::total   1024295614                       # number of ReadReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::cpu3    922064777                       # number of WriteReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::total    922064777                       # number of WriteReq miss cycles
+system.cpu3.l1c.demand_miss_latency::cpu3   1946360391                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.demand_miss_latency::total   1946360391                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.overall_miss_latency::cpu3   1946360391                       # number of overall miss cycles
+system.cpu3.l1c.overall_miss_latency::total   1946360391                       # number of overall miss cycles
+system.cpu3.l1c.ReadReq_accesses::cpu3          45404                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_accesses::total         45404                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::cpu3         25053                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::total        25053                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.demand_accesses::cpu3           70457                       # number of demand (read+write) accesses
+system.cpu3.l1c.demand_accesses::total          70457                       # number of demand (read+write) accesses
+system.cpu3.l1c.overall_accesses::cpu3          70457                       # number of overall (read+write) accesses
+system.cpu3.l1c.overall_accesses::total         70457                       # number of overall (read+write) accesses
+system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.806999                       # miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_miss_rate::total     0.806999                       # miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.951263                       # miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::total     0.951263                       # miss rate for WriteReq accesses
+system.cpu3.l1c.demand_miss_rate::cpu3       0.858297                       # miss rate for demand accesses
+system.cpu3.l1c.demand_miss_rate::total      0.858297                       # miss rate for demand accesses
+system.cpu3.l1c.overall_miss_rate::cpu3      0.858297                       # miss rate for overall accesses
+system.cpu3.l1c.overall_miss_rate::total     0.858297                       # miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 27954.903360                       # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_miss_latency::total 27954.903360                       # average ReadReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 38690.197088                       # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::total 38690.197088                       # average WriteReq miss latency
+system.cpu3.l1c.demand_avg_miss_latency::cpu3 32185.609958                       # average overall miss latency
+system.cpu3.l1c.demand_avg_miss_latency::total 32185.609958                       # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::cpu3 32185.609958                       # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::total 32185.609958                       # average overall miss latency
+system.cpu3.l1c.blocked_cycles::no_mshrs      1061792                       # number of cycles access was blocked
 system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs               61848                       # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_mshrs               61430                       # number of cycles access was blocked
 system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs    17.344732                       # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_mshrs    17.284584                       # average number of cycles each access was blocked
 system.cpu3.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu3.l1c.writebacks::writebacks           9757                       # number of writebacks
-system.cpu3.l1c.writebacks::total                9757                       # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36458                       # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_misses::total        36458                       # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23788                       # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::total        23788                       # number of WriteReq MSHR misses
-system.cpu3.l1c.demand_mshr_misses::cpu3        60246                       # number of demand (read+write) MSHR misses
-system.cpu3.l1c.demand_mshr_misses::total        60246                       # number of demand (read+write) MSHR misses
-system.cpu3.l1c.overall_mshr_misses::cpu3        60246                       # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_misses::total        60246                       # number of overall MSHR misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    956791627                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_latency::total    956791627                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    884289164                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total    884289164                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1841080791                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::total   1841080791                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1841080791                       # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total   1841080791                       # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    756050699                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    756050699                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3   1926314708                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total   1926314708                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   2682365407                       # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::total   2682365407                       # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.808274                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.808274                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.954728                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.954728                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.860387                       # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_miss_rate::total     0.860387                       # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.860387                       # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total     0.860387                       # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 26243.667426                       # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 26243.667426                       # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 37173.749958                       # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 37173.749958                       # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 30559.386366                       # average overall mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 30559.386366                       # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 30559.386366                       # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 30559.386366                       # average overall mshr miss latency
+system.cpu3.l1c.writebacks::writebacks           9814                       # number of writebacks
+system.cpu3.l1c.writebacks::total                9814                       # number of writebacks
+system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36641                       # number of ReadReq MSHR misses
+system.cpu3.l1c.ReadReq_mshr_misses::total        36641                       # number of ReadReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23832                       # number of WriteReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::total        23832                       # number of WriteReq MSHR misses
+system.cpu3.l1c.demand_mshr_misses::cpu3        60473                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.demand_mshr_misses::total        60473                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.overall_mshr_misses::cpu3        60473                       # number of overall MSHR misses
+system.cpu3.l1c.overall_mshr_misses::total        60473                       # number of overall MSHR misses
+system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    968238306                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_miss_latency::total    968238306                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    885855695                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::total    885855695                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1854094001                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::total   1854094001                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1854094001                       # number of overall MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::total   1854094001                       # number of overall MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    733819505                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    733819505                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3   1976786114                       # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total   1976786114                       # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   2710605619                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::total   2710605619                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.806999                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.806999                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.951263                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.951263                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.858297                       # mshr miss rate for demand accesses
+system.cpu3.l1c.demand_mshr_miss_rate::total     0.858297                       # mshr miss rate for demand accesses
+system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.858297                       # mshr miss rate for overall accesses
+system.cpu3.l1c.overall_mshr_miss_rate::total     0.858297                       # mshr miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 26424.996752                       # average ReadReq mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 26424.996752                       # average ReadReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 37170.849908                       # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 37170.849908                       # average WriteReq mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 30659.864750                       # average overall mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::total 30659.864750                       # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 30659.864750                       # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::total 30659.864750                       # average overall mshr miss latency
 system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average ReadReq mshr uncacheable latency
 system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average WriteReq mshr uncacheable latency
@@ -557,119 +557,119 @@
 system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3          inf                       # average overall mshr uncacheable latency
 system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu4.num_reads                           98774                       # number of read accesses completed
-system.cpu4.num_writes                          54829                       # number of write accesses completed
-system.cpu4.l1c.tags.replacements               22505                       # number of replacements
-system.cpu4.l1c.tags.tagsinuse             395.050000                       # Cycle average of tags in use
-system.cpu4.l1c.tags.total_refs                 13373                       # Total number of references to valid blocks.
-system.cpu4.l1c.tags.sampled_refs               22916                       # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs                0.583566                       # Average number of references to valid blocks.
+system.cpu4.num_reads                           99688                       # number of read accesses completed
+system.cpu4.num_writes                          55538                       # number of write accesses completed
+system.cpu4.l1c.tags.replacements               22215                       # number of replacements
+system.cpu4.l1c.tags.tagsinuse             391.788113                       # Cycle average of tags in use
+system.cpu4.l1c.tags.total_refs                 13621                       # Total number of references to valid blocks.
+system.cpu4.l1c.tags.sampled_refs               22618                       # Sample count of references to valid blocks.
+system.cpu4.l1c.tags.avg_refs                0.602219                       # Average number of references to valid blocks.
 system.cpu4.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.tags.occ_blocks::cpu4      395.050000                       # Average occupied blocks per requestor
-system.cpu4.l1c.tags.occ_percent::cpu4       0.771582                       # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_percent::total      0.771582                       # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_task_id_blocks::1024          411                       # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::0          384                       # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::1           27                       # Occupied blocks per task id
-system.cpu4.l1c.tags.occ_task_id_percent::1024     0.802734                       # Percentage of cache occupancy per task id
-system.cpu4.l1c.tags.tag_accesses              337873                       # Number of tag accesses
-system.cpu4.l1c.tags.data_accesses             337873                       # Number of data accesses
-system.cpu4.l1c.ReadReq_hits::cpu4               8531                       # number of ReadReq hits
-system.cpu4.l1c.ReadReq_hits::total              8531                       # number of ReadReq hits
-system.cpu4.l1c.WriteReq_hits::cpu4              1209                       # number of WriteReq hits
-system.cpu4.l1c.WriteReq_hits::total             1209                       # number of WriteReq hits
-system.cpu4.l1c.demand_hits::cpu4                9740                       # number of demand (read+write) hits
-system.cpu4.l1c.demand_hits::total               9740                       # number of demand (read+write) hits
-system.cpu4.l1c.overall_hits::cpu4               9740                       # number of overall hits
-system.cpu4.l1c.overall_hits::total              9740                       # number of overall hits
-system.cpu4.l1c.ReadReq_misses::cpu4            36518                       # number of ReadReq misses
-system.cpu4.l1c.ReadReq_misses::total           36518                       # number of ReadReq misses
-system.cpu4.l1c.WriteReq_misses::cpu4           24001                       # number of WriteReq misses
-system.cpu4.l1c.WriteReq_misses::total          24001                       # number of WriteReq misses
-system.cpu4.l1c.demand_misses::cpu4             60519                       # number of demand (read+write) misses
-system.cpu4.l1c.demand_misses::total            60519                       # number of demand (read+write) misses
-system.cpu4.l1c.overall_misses::cpu4            60519                       # number of overall misses
-system.cpu4.l1c.overall_misses::total           60519                       # number of overall misses
-system.cpu4.l1c.ReadReq_miss_latency::cpu4   1017641988                       # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_latency::total   1017641988                       # number of ReadReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::cpu4    934552595                       # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::total    934552595                       # number of WriteReq miss cycles
-system.cpu4.l1c.demand_miss_latency::cpu4   1952194583                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_latency::total   1952194583                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.overall_miss_latency::cpu4   1952194583                       # number of overall miss cycles
-system.cpu4.l1c.overall_miss_latency::total   1952194583                       # number of overall miss cycles
-system.cpu4.l1c.ReadReq_accesses::cpu4          45049                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_accesses::total         45049                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::cpu4         25210                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::total        25210                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.demand_accesses::cpu4           70259                       # number of demand (read+write) accesses
-system.cpu4.l1c.demand_accesses::total          70259                       # number of demand (read+write) accesses
-system.cpu4.l1c.overall_accesses::cpu4          70259                       # number of overall (read+write) accesses
-system.cpu4.l1c.overall_accesses::total         70259                       # number of overall (read+write) accesses
-system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.810628                       # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_miss_rate::total     0.810628                       # miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.952043                       # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::total     0.952043                       # miss rate for WriteReq accesses
-system.cpu4.l1c.demand_miss_rate::cpu4       0.861370                       # miss rate for demand accesses
-system.cpu4.l1c.demand_miss_rate::total      0.861370                       # miss rate for demand accesses
-system.cpu4.l1c.overall_miss_rate::cpu4      0.861370                       # miss rate for overall accesses
-system.cpu4.l1c.overall_miss_rate::total     0.861370                       # miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 27866.859850                       # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_miss_latency::total 27866.859850                       # average ReadReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 38938.069039                       # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::total 38938.069039                       # average WriteReq miss latency
-system.cpu4.l1c.demand_avg_miss_latency::cpu4 32257.548588                       # average overall miss latency
-system.cpu4.l1c.demand_avg_miss_latency::total 32257.548588                       # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::cpu4 32257.548588                       # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::total 32257.548588                       # average overall miss latency
-system.cpu4.l1c.blocked_cycles::no_mshrs      1063629                       # number of cycles access was blocked
+system.cpu4.l1c.tags.occ_blocks::cpu4      391.788113                       # Average occupied blocks per requestor
+system.cpu4.l1c.tags.occ_percent::cpu4       0.765211                       # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_percent::total      0.765211                       # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_task_id_blocks::1024          403                       # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::0          365                       # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
+system.cpu4.l1c.tags.occ_task_id_percent::1024     0.787109                       # Percentage of cache occupancy per task id
+system.cpu4.l1c.tags.tag_accesses              338206                       # Number of tag accesses
+system.cpu4.l1c.tags.data_accesses             338206                       # Number of data accesses
+system.cpu4.l1c.ReadReq_hits::cpu4               8861                       # number of ReadReq hits
+system.cpu4.l1c.ReadReq_hits::total              8861                       # number of ReadReq hits
+system.cpu4.l1c.WriteReq_hits::cpu4              1198                       # number of WriteReq hits
+system.cpu4.l1c.WriteReq_hits::total             1198                       # number of WriteReq hits
+system.cpu4.l1c.demand_hits::cpu4               10059                       # number of demand (read+write) hits
+system.cpu4.l1c.demand_hits::total              10059                       # number of demand (read+write) hits
+system.cpu4.l1c.overall_hits::cpu4              10059                       # number of overall hits
+system.cpu4.l1c.overall_hits::total             10059                       # number of overall hits
+system.cpu4.l1c.ReadReq_misses::cpu4            36318                       # number of ReadReq misses
+system.cpu4.l1c.ReadReq_misses::total           36318                       # number of ReadReq misses
+system.cpu4.l1c.WriteReq_misses::cpu4           24000                       # number of WriteReq misses
+system.cpu4.l1c.WriteReq_misses::total          24000                       # number of WriteReq misses
+system.cpu4.l1c.demand_misses::cpu4             60318                       # number of demand (read+write) misses
+system.cpu4.l1c.demand_misses::total            60318                       # number of demand (read+write) misses
+system.cpu4.l1c.overall_misses::cpu4            60318                       # number of overall misses
+system.cpu4.l1c.overall_misses::total           60318                       # number of overall misses
+system.cpu4.l1c.ReadReq_miss_latency::cpu4   1007698293                       # number of ReadReq miss cycles
+system.cpu4.l1c.ReadReq_miss_latency::total   1007698293                       # number of ReadReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::cpu4    930213172                       # number of WriteReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::total    930213172                       # number of WriteReq miss cycles
+system.cpu4.l1c.demand_miss_latency::cpu4   1937911465                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.demand_miss_latency::total   1937911465                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.overall_miss_latency::cpu4   1937911465                       # number of overall miss cycles
+system.cpu4.l1c.overall_miss_latency::total   1937911465                       # number of overall miss cycles
+system.cpu4.l1c.ReadReq_accesses::cpu4          45179                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.ReadReq_accesses::total         45179                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::cpu4         25198                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::total        25198                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.demand_accesses::cpu4           70377                       # number of demand (read+write) accesses
+system.cpu4.l1c.demand_accesses::total          70377                       # number of demand (read+write) accesses
+system.cpu4.l1c.overall_accesses::cpu4          70377                       # number of overall (read+write) accesses
+system.cpu4.l1c.overall_accesses::total         70377                       # number of overall (read+write) accesses
+system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.803869                       # miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_miss_rate::total     0.803869                       # miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.952457                       # miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::total     0.952457                       # miss rate for WriteReq accesses
+system.cpu4.l1c.demand_miss_rate::cpu4       0.857070                       # miss rate for demand accesses
+system.cpu4.l1c.demand_miss_rate::total      0.857070                       # miss rate for demand accesses
+system.cpu4.l1c.overall_miss_rate::cpu4      0.857070                       # miss rate for overall accesses
+system.cpu4.l1c.overall_miss_rate::total     0.857070                       # miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 27746.524946                       # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_miss_latency::total 27746.524946                       # average ReadReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 38758.882167                       # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::total 38758.882167                       # average WriteReq miss latency
+system.cpu4.l1c.demand_avg_miss_latency::cpu4 32128.244720                       # average overall miss latency
+system.cpu4.l1c.demand_avg_miss_latency::total 32128.244720                       # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::cpu4 32128.244720                       # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::total 32128.244720                       # average overall miss latency
+system.cpu4.l1c.blocked_cycles::no_mshrs      1066740                       # number of cycles access was blocked
 system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs               61473                       # number of cycles access was blocked
+system.cpu4.l1c.blocked::no_mshrs               61639                       # number of cycles access was blocked
 system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_mshrs    17.302377                       # average number of cycles each access was blocked
+system.cpu4.l1c.avg_blocked_cycles::no_mshrs    17.306251                       # average number of cycles each access was blocked
 system.cpu4.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu4.l1c.writebacks::writebacks           9914                       # number of writebacks
-system.cpu4.l1c.writebacks::total                9914                       # number of writebacks
-system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36518                       # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_misses::total        36518                       # number of ReadReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::cpu4        24001                       # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::total        24001                       # number of WriteReq MSHR misses
-system.cpu4.l1c.demand_mshr_misses::cpu4        60519                       # number of demand (read+write) MSHR misses
-system.cpu4.l1c.demand_mshr_misses::total        60519                       # number of demand (read+write) MSHR misses
-system.cpu4.l1c.overall_mshr_misses::cpu4        60519                       # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_misses::total        60519                       # number of overall MSHR misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    961775196                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_latency::total    961775196                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    898026173                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::total    898026173                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1859801369                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::total   1859801369                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1859801369                       # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total   1859801369                       # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    728267014                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    728267014                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4   1921671690                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total   1921671690                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   2649938704                       # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::total   2649938704                       # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.810628                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.810628                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.952043                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.952043                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.861370                       # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_miss_rate::total     0.861370                       # mshr miss rate for demand accesses
-system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.861370                       # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_miss_rate::total     0.861370                       # mshr miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 26337.017252                       # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 26337.017252                       # average ReadReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 37416.198200                       # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 37416.198200                       # average WriteReq mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 30730.867480                       # average overall mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 30730.867480                       # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 30730.867480                       # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 30730.867480                       # average overall mshr miss latency
+system.cpu4.l1c.writebacks::writebacks           9826                       # number of writebacks
+system.cpu4.l1c.writebacks::total                9826                       # number of writebacks
+system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36318                       # number of ReadReq MSHR misses
+system.cpu4.l1c.ReadReq_mshr_misses::total        36318                       # number of ReadReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses::cpu4        24000                       # number of WriteReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses::total        24000                       # number of WriteReq MSHR misses
+system.cpu4.l1c.demand_mshr_misses::cpu4        60318                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.demand_mshr_misses::total        60318                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.overall_mshr_misses::cpu4        60318                       # number of overall MSHR misses
+system.cpu4.l1c.overall_mshr_misses::total        60318                       # number of overall MSHR misses
+system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    952156937                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_miss_latency::total    952156937                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    893690718                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency::total    893690718                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1845847655                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency::total   1845847655                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1845847655                       # number of overall MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::total   1845847655                       # number of overall MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    748268844                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    748268844                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4   1945456088                       # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total   1945456088                       # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   2693724932                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency::total   2693724932                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.803869                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.803869                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.952457                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.952457                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.857070                       # mshr miss rate for demand accesses
+system.cpu4.l1c.demand_mshr_miss_rate::total     0.857070                       # mshr miss rate for demand accesses
+system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.857070                       # mshr miss rate for overall accesses
+system.cpu4.l1c.overall_mshr_miss_rate::total     0.857070                       # mshr miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 26217.218377                       # average ReadReq mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 26217.218377                       # average ReadReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 37237.113250                       # average WriteReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 37237.113250                       # average WriteReq mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 30601.937316                       # average overall mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::total 30601.937316                       # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 30601.937316                       # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::total 30601.937316                       # average overall mshr miss latency
 system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average ReadReq mshr uncacheable latency
 system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average WriteReq mshr uncacheable latency
@@ -677,119 +677,119 @@
 system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4          inf                       # average overall mshr uncacheable latency
 system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu5.num_reads                           99305                       # number of read accesses completed
-system.cpu5.num_writes                          54996                       # number of write accesses completed
-system.cpu5.l1c.tags.replacements               22529                       # number of replacements
-system.cpu5.l1c.tags.tagsinuse             394.380527                       # Cycle average of tags in use
-system.cpu5.l1c.tags.total_refs                 13364                       # Total number of references to valid blocks.
-system.cpu5.l1c.tags.sampled_refs               22931                       # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs                0.582792                       # Average number of references to valid blocks.
+system.cpu5.num_reads                           98777                       # number of read accesses completed
+system.cpu5.num_writes                          55102                       # number of write accesses completed
+system.cpu5.l1c.tags.replacements               22389                       # number of replacements
+system.cpu5.l1c.tags.tagsinuse             394.368473                       # Cycle average of tags in use
+system.cpu5.l1c.tags.total_refs                 13612                       # Total number of references to valid blocks.
+system.cpu5.l1c.tags.sampled_refs               22785                       # Sample count of references to valid blocks.
+system.cpu5.l1c.tags.avg_refs                0.597411                       # Average number of references to valid blocks.
 system.cpu5.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.tags.occ_blocks::cpu5      394.380527                       # Average occupied blocks per requestor
-system.cpu5.l1c.tags.occ_percent::cpu5       0.770274                       # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_percent::total      0.770274                       # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::0          376                       # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
-system.cpu5.l1c.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
-system.cpu5.l1c.tags.tag_accesses              337468                       # Number of tag accesses
-system.cpu5.l1c.tags.data_accesses             337468                       # Number of data accesses
-system.cpu5.l1c.ReadReq_hits::cpu5               8640                       # number of ReadReq hits
-system.cpu5.l1c.ReadReq_hits::total              8640                       # number of ReadReq hits
-system.cpu5.l1c.WriteReq_hits::cpu5              1161                       # number of WriteReq hits
-system.cpu5.l1c.WriteReq_hits::total             1161                       # number of WriteReq hits
-system.cpu5.l1c.demand_hits::cpu5                9801                       # number of demand (read+write) hits
-system.cpu5.l1c.demand_hits::total               9801                       # number of demand (read+write) hits
-system.cpu5.l1c.overall_hits::cpu5               9801                       # number of overall hits
-system.cpu5.l1c.overall_hits::total              9801                       # number of overall hits
-system.cpu5.l1c.ReadReq_misses::cpu5            36580                       # number of ReadReq misses
-system.cpu5.l1c.ReadReq_misses::total           36580                       # number of ReadReq misses
-system.cpu5.l1c.WriteReq_misses::cpu5           23798                       # number of WriteReq misses
-system.cpu5.l1c.WriteReq_misses::total          23798                       # number of WriteReq misses
-system.cpu5.l1c.demand_misses::cpu5             60378                       # number of demand (read+write) misses
-system.cpu5.l1c.demand_misses::total            60378                       # number of demand (read+write) misses
-system.cpu5.l1c.overall_misses::cpu5            60378                       # number of overall misses
-system.cpu5.l1c.overall_misses::total           60378                       # number of overall misses
-system.cpu5.l1c.ReadReq_miss_latency::cpu5   1015127570                       # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_latency::total   1015127570                       # number of ReadReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::cpu5    927119253                       # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::total    927119253                       # number of WriteReq miss cycles
-system.cpu5.l1c.demand_miss_latency::cpu5   1942246823                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.demand_miss_latency::total   1942246823                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.overall_miss_latency::cpu5   1942246823                       # number of overall miss cycles
-system.cpu5.l1c.overall_miss_latency::total   1942246823                       # number of overall miss cycles
-system.cpu5.l1c.ReadReq_accesses::cpu5          45220                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_accesses::total         45220                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::cpu5         24959                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::total        24959                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.demand_accesses::cpu5           70179                       # number of demand (read+write) accesses
-system.cpu5.l1c.demand_accesses::total          70179                       # number of demand (read+write) accesses
-system.cpu5.l1c.overall_accesses::cpu5          70179                       # number of overall (read+write) accesses
-system.cpu5.l1c.overall_accesses::total         70179                       # number of overall (read+write) accesses
-system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.808934                       # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_miss_rate::total     0.808934                       # miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.953484                       # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::total     0.953484                       # miss rate for WriteReq accesses
-system.cpu5.l1c.demand_miss_rate::cpu5       0.860343                       # miss rate for demand accesses
-system.cpu5.l1c.demand_miss_rate::total      0.860343                       # miss rate for demand accesses
-system.cpu5.l1c.overall_miss_rate::cpu5      0.860343                       # miss rate for overall accesses
-system.cpu5.l1c.overall_miss_rate::total     0.860343                       # miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 27750.890377                       # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_miss_latency::total 27750.890377                       # average ReadReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 38957.864232                       # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::total 38957.864232                       # average WriteReq miss latency
-system.cpu5.l1c.demand_avg_miss_latency::cpu5 32168.121220                       # average overall miss latency
-system.cpu5.l1c.demand_avg_miss_latency::total 32168.121220                       # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 32168.121220                       # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 32168.121220                       # average overall miss latency
-system.cpu5.l1c.blocked_cycles::no_mshrs      1066593                       # number of cycles access was blocked
+system.cpu5.l1c.tags.occ_blocks::cpu5      394.368473                       # Average occupied blocks per requestor
+system.cpu5.l1c.tags.occ_percent::cpu5       0.770251                       # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_percent::total      0.770251                       # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_task_id_blocks::1024          396                       # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::0          367                       # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::1           29                       # Occupied blocks per task id
+system.cpu5.l1c.tags.occ_task_id_percent::1024     0.773438                       # Percentage of cache occupancy per task id
+system.cpu5.l1c.tags.tag_accesses              338353                       # Number of tag accesses
+system.cpu5.l1c.tags.data_accesses             338353                       # Number of data accesses
+system.cpu5.l1c.ReadReq_hits::cpu5               8788                       # number of ReadReq hits
+system.cpu5.l1c.ReadReq_hits::total              8788                       # number of ReadReq hits
+system.cpu5.l1c.WriteReq_hits::cpu5              1200                       # number of WriteReq hits
+system.cpu5.l1c.WriteReq_hits::total             1200                       # number of WriteReq hits
+system.cpu5.l1c.demand_hits::cpu5                9988                       # number of demand (read+write) hits
+system.cpu5.l1c.demand_hits::total               9988                       # number of demand (read+write) hits
+system.cpu5.l1c.overall_hits::cpu5               9988                       # number of overall hits
+system.cpu5.l1c.overall_hits::total              9988                       # number of overall hits
+system.cpu5.l1c.ReadReq_misses::cpu5            36608                       # number of ReadReq misses
+system.cpu5.l1c.ReadReq_misses::total           36608                       # number of ReadReq misses
+system.cpu5.l1c.WriteReq_misses::cpu5           23815                       # number of WriteReq misses
+system.cpu5.l1c.WriteReq_misses::total          23815                       # number of WriteReq misses
+system.cpu5.l1c.demand_misses::cpu5             60423                       # number of demand (read+write) misses
+system.cpu5.l1c.demand_misses::total            60423                       # number of demand (read+write) misses
+system.cpu5.l1c.overall_misses::cpu5            60423                       # number of overall misses
+system.cpu5.l1c.overall_misses::total           60423                       # number of overall misses
+system.cpu5.l1c.ReadReq_miss_latency::cpu5   1017800983                       # number of ReadReq miss cycles
+system.cpu5.l1c.ReadReq_miss_latency::total   1017800983                       # number of ReadReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::cpu5    926597102                       # number of WriteReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::total    926597102                       # number of WriteReq miss cycles
+system.cpu5.l1c.demand_miss_latency::cpu5   1944398085                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.demand_miss_latency::total   1944398085                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.overall_miss_latency::cpu5   1944398085                       # number of overall miss cycles
+system.cpu5.l1c.overall_miss_latency::total   1944398085                       # number of overall miss cycles
+system.cpu5.l1c.ReadReq_accesses::cpu5          45396                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.ReadReq_accesses::total         45396                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::cpu5         25015                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::total        25015                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.demand_accesses::cpu5           70411                       # number of demand (read+write) accesses
+system.cpu5.l1c.demand_accesses::total          70411                       # number of demand (read+write) accesses
+system.cpu5.l1c.overall_accesses::cpu5          70411                       # number of overall (read+write) accesses
+system.cpu5.l1c.overall_accesses::total         70411                       # number of overall (read+write) accesses
+system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.806415                       # miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_miss_rate::total     0.806415                       # miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.952029                       # miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::total     0.952029                       # miss rate for WriteReq accesses
+system.cpu5.l1c.demand_miss_rate::cpu5       0.858147                       # miss rate for demand accesses
+system.cpu5.l1c.demand_miss_rate::total      0.858147                       # miss rate for demand accesses
+system.cpu5.l1c.overall_miss_rate::cpu5      0.858147                       # miss rate for overall accesses
+system.cpu5.l1c.overall_miss_rate::total     0.858147                       # miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 27802.692936                       # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_miss_latency::total 27802.692936                       # average ReadReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 38908.129414                       # average WriteReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::total 38908.129414                       # average WriteReq miss latency
+system.cpu5.l1c.demand_avg_miss_latency::cpu5 32179.767390                       # average overall miss latency
+system.cpu5.l1c.demand_avg_miss_latency::total 32179.767390                       # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::cpu5 32179.767390                       # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::total 32179.767390                       # average overall miss latency
+system.cpu5.l1c.blocked_cycles::no_mshrs      1064852                       # number of cycles access was blocked
 system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs               61522                       # number of cycles access was blocked
+system.cpu5.l1c.blocked::no_mshrs               61539                       # number of cycles access was blocked
 system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs    17.336774                       # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_mshrs    17.303694                       # average number of cycles each access was blocked
 system.cpu5.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu5.l1c.writebacks::writebacks           9775                       # number of writebacks
-system.cpu5.l1c.writebacks::total                9775                       # number of writebacks
-system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36580                       # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_misses::total        36580                       # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23798                       # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::total        23798                       # number of WriteReq MSHR misses
-system.cpu5.l1c.demand_mshr_misses::cpu5        60378                       # number of demand (read+write) MSHR misses
-system.cpu5.l1c.demand_mshr_misses::total        60378                       # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses::cpu5        60378                       # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_misses::total        60378                       # number of overall MSHR misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    959195658                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_latency::total    959195658                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    890981649                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::total    890981649                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1850177307                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::total   1850177307                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1850177307                       # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total   1850177307                       # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    738489342                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    738489342                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5   1963680665                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total   1963680665                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   2702170007                       # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::total   2702170007                       # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.808934                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.808934                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.953484                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.953484                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.860343                       # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_miss_rate::total     0.860343                       # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.860343                       # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_miss_rate::total     0.860343                       # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 26221.860525                       # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 26221.860525                       # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 37439.349903                       # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 37439.349903                       # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 30643.236063                       # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 30643.236063                       # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 30643.236063                       # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::total 30643.236063                       # average overall mshr miss latency
+system.cpu5.l1c.writebacks::writebacks           9851                       # number of writebacks
+system.cpu5.l1c.writebacks::total                9851                       # number of writebacks
+system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36608                       # number of ReadReq MSHR misses
+system.cpu5.l1c.ReadReq_mshr_misses::total        36608                       # number of ReadReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23815                       # number of WriteReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses::total        23815                       # number of WriteReq MSHR misses
+system.cpu5.l1c.demand_mshr_misses::cpu5        60423                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.demand_mshr_misses::total        60423                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.overall_mshr_misses::cpu5        60423                       # number of overall MSHR misses
+system.cpu5.l1c.overall_mshr_misses::total        60423                       # number of overall MSHR misses
+system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    961777191                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_miss_latency::total    961777191                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    890427492                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency::total    890427492                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1852204683                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency::total   1852204683                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1852204683                       # number of overall MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::total   1852204683                       # number of overall MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    736504009                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    736504009                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5   1948720715                       # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total   1948720715                       # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   2685224724                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency::total   2685224724                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.806415                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.806415                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.952029                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.952029                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.858147                       # mshr miss rate for demand accesses
+system.cpu5.l1c.demand_mshr_miss_rate::total     0.858147                       # mshr miss rate for demand accesses
+system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.858147                       # mshr miss rate for overall accesses
+system.cpu5.l1c.overall_mshr_miss_rate::total     0.858147                       # mshr miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 26272.322744                       # average ReadReq mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 26272.322744                       # average ReadReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 37389.355112                       # average WriteReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 37389.355112                       # average WriteReq mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 30653.967579                       # average overall mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::total 30653.967579                       # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 30653.967579                       # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::total 30653.967579                       # average overall mshr miss latency
 system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average ReadReq mshr uncacheable latency
 system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average WriteReq mshr uncacheable latency
@@ -797,119 +797,119 @@
 system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5          inf                       # average overall mshr uncacheable latency
 system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu6.num_reads                           99342                       # number of read accesses completed
-system.cpu6.num_writes                          54737                       # number of write accesses completed
-system.cpu6.l1c.tags.replacements               22276                       # number of replacements
-system.cpu6.l1c.tags.tagsinuse             393.125800                       # Cycle average of tags in use
-system.cpu6.l1c.tags.total_refs                 13636                       # Total number of references to valid blocks.
-system.cpu6.l1c.tags.sampled_refs               22683                       # Sample count of references to valid blocks.
-system.cpu6.l1c.tags.avg_refs                0.601155                       # Average number of references to valid blocks.
+system.cpu6.num_reads                           99339                       # number of read accesses completed
+system.cpu6.num_writes                          55520                       # number of write accesses completed
+system.cpu6.l1c.tags.replacements               22403                       # number of replacements
+system.cpu6.l1c.tags.tagsinuse             393.263413                       # Cycle average of tags in use
+system.cpu6.l1c.tags.total_refs                 13582                       # Total number of references to valid blocks.
+system.cpu6.l1c.tags.sampled_refs               22789                       # Sample count of references to valid blocks.
+system.cpu6.l1c.tags.avg_refs                0.595989                       # Average number of references to valid blocks.
 system.cpu6.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.tags.occ_blocks::cpu6      393.125800                       # Average occupied blocks per requestor
-system.cpu6.l1c.tags.occ_percent::cpu6       0.767824                       # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_percent::total      0.767824                       # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_task_id_blocks::1024          407                       # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::0          376                       # Occupied blocks per task id
+system.cpu6.l1c.tags.occ_blocks::cpu6      393.263413                       # Average occupied blocks per requestor
+system.cpu6.l1c.tags.occ_percent::cpu6       0.768093                       # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_percent::total      0.768093                       # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_task_id_blocks::1024          386                       # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::0          355                       # Occupied blocks per task id
 system.cpu6.l1c.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
-system.cpu6.l1c.tags.occ_task_id_percent::1024     0.794922                       # Percentage of cache occupancy per task id
-system.cpu6.l1c.tags.tag_accesses              337855                       # Number of tag accesses
-system.cpu6.l1c.tags.data_accesses             337855                       # Number of data accesses
-system.cpu6.l1c.ReadReq_hits::cpu6               8799                       # number of ReadReq hits
-system.cpu6.l1c.ReadReq_hits::total              8799                       # number of ReadReq hits
-system.cpu6.l1c.WriteReq_hits::cpu6              1154                       # number of WriteReq hits
-system.cpu6.l1c.WriteReq_hits::total             1154                       # number of WriteReq hits
-system.cpu6.l1c.demand_hits::cpu6                9953                       # number of demand (read+write) hits
-system.cpu6.l1c.demand_hits::total               9953                       # number of demand (read+write) hits
-system.cpu6.l1c.overall_hits::cpu6               9953                       # number of overall hits
-system.cpu6.l1c.overall_hits::total              9953                       # number of overall hits
-system.cpu6.l1c.ReadReq_misses::cpu6            36552                       # number of ReadReq misses
-system.cpu6.l1c.ReadReq_misses::total           36552                       # number of ReadReq misses
-system.cpu6.l1c.WriteReq_misses::cpu6           23805                       # number of WriteReq misses
-system.cpu6.l1c.WriteReq_misses::total          23805                       # number of WriteReq misses
-system.cpu6.l1c.demand_misses::cpu6             60357                       # number of demand (read+write) misses
-system.cpu6.l1c.demand_misses::total            60357                       # number of demand (read+write) misses
-system.cpu6.l1c.overall_misses::cpu6            60357                       # number of overall misses
-system.cpu6.l1c.overall_misses::total           60357                       # number of overall misses
-system.cpu6.l1c.ReadReq_miss_latency::cpu6   1017275565                       # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_latency::total   1017275565                       # number of ReadReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::cpu6    923819144                       # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::total    923819144                       # number of WriteReq miss cycles
-system.cpu6.l1c.demand_miss_latency::cpu6   1941094709                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_latency::total   1941094709                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.overall_miss_latency::cpu6   1941094709                       # number of overall miss cycles
-system.cpu6.l1c.overall_miss_latency::total   1941094709                       # number of overall miss cycles
-system.cpu6.l1c.ReadReq_accesses::cpu6          45351                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_accesses::total         45351                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::cpu6         24959                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::total        24959                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.demand_accesses::cpu6           70310                       # number of demand (read+write) accesses
-system.cpu6.l1c.demand_accesses::total          70310                       # number of demand (read+write) accesses
-system.cpu6.l1c.overall_accesses::cpu6          70310                       # number of overall (read+write) accesses
-system.cpu6.l1c.overall_accesses::total         70310                       # number of overall (read+write) accesses
-system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.805980                       # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_miss_rate::total     0.805980                       # miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.953764                       # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::total     0.953764                       # miss rate for WriteReq accesses
-system.cpu6.l1c.demand_miss_rate::cpu6       0.858441                       # miss rate for demand accesses
-system.cpu6.l1c.demand_miss_rate::total      0.858441                       # miss rate for demand accesses
-system.cpu6.l1c.overall_miss_rate::cpu6      0.858441                       # miss rate for overall accesses
-system.cpu6.l1c.overall_miss_rate::total     0.858441                       # miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 27830.913903                       # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_miss_latency::total 27830.913903                       # average ReadReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 38807.777526                       # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::total 38807.777526                       # average WriteReq miss latency
-system.cpu6.l1c.demand_avg_miss_latency::cpu6 32160.225144                       # average overall miss latency
-system.cpu6.l1c.demand_avg_miss_latency::total 32160.225144                       # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 32160.225144                       # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 32160.225144                       # average overall miss latency
-system.cpu6.l1c.blocked_cycles::no_mshrs      1069531                       # number of cycles access was blocked
+system.cpu6.l1c.tags.occ_task_id_percent::1024     0.753906                       # Percentage of cache occupancy per task id
+system.cpu6.l1c.tags.tag_accesses              338803                       # Number of tag accesses
+system.cpu6.l1c.tags.data_accesses             338803                       # Number of data accesses
+system.cpu6.l1c.ReadReq_hits::cpu6               8815                       # number of ReadReq hits
+system.cpu6.l1c.ReadReq_hits::total              8815                       # number of ReadReq hits
+system.cpu6.l1c.WriteReq_hits::cpu6              1164                       # number of WriteReq hits
+system.cpu6.l1c.WriteReq_hits::total             1164                       # number of WriteReq hits
+system.cpu6.l1c.demand_hits::cpu6                9979                       # number of demand (read+write) hits
+system.cpu6.l1c.demand_hits::total               9979                       # number of demand (read+write) hits
+system.cpu6.l1c.overall_hits::cpu6               9979                       # number of overall hits
+system.cpu6.l1c.overall_hits::total              9979                       # number of overall hits
+system.cpu6.l1c.ReadReq_misses::cpu6            36385                       # number of ReadReq misses
+system.cpu6.l1c.ReadReq_misses::total           36385                       # number of ReadReq misses
+system.cpu6.l1c.WriteReq_misses::cpu6           24126                       # number of WriteReq misses
+system.cpu6.l1c.WriteReq_misses::total          24126                       # number of WriteReq misses
+system.cpu6.l1c.demand_misses::cpu6             60511                       # number of demand (read+write) misses
+system.cpu6.l1c.demand_misses::total            60511                       # number of demand (read+write) misses
+system.cpu6.l1c.overall_misses::cpu6            60511                       # number of overall misses
+system.cpu6.l1c.overall_misses::total           60511                       # number of overall misses
+system.cpu6.l1c.ReadReq_miss_latency::cpu6   1008730718                       # number of ReadReq miss cycles
+system.cpu6.l1c.ReadReq_miss_latency::total   1008730718                       # number of ReadReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::cpu6    936995994                       # number of WriteReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::total    936995994                       # number of WriteReq miss cycles
+system.cpu6.l1c.demand_miss_latency::cpu6   1945726712                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.demand_miss_latency::total   1945726712                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.overall_miss_latency::cpu6   1945726712                       # number of overall miss cycles
+system.cpu6.l1c.overall_miss_latency::total   1945726712                       # number of overall miss cycles
+system.cpu6.l1c.ReadReq_accesses::cpu6          45200                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.ReadReq_accesses::total         45200                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::cpu6         25290                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::total        25290                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.demand_accesses::cpu6           70490                       # number of demand (read+write) accesses
+system.cpu6.l1c.demand_accesses::total          70490                       # number of demand (read+write) accesses
+system.cpu6.l1c.overall_accesses::cpu6          70490                       # number of overall (read+write) accesses
+system.cpu6.l1c.overall_accesses::total         70490                       # number of overall (read+write) accesses
+system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.804978                       # miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_miss_rate::total     0.804978                       # miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.953974                       # miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::total     0.953974                       # miss rate for WriteReq accesses
+system.cpu6.l1c.demand_miss_rate::cpu6       0.858434                       # miss rate for demand accesses
+system.cpu6.l1c.demand_miss_rate::total      0.858434                       # miss rate for demand accesses
+system.cpu6.l1c.overall_miss_rate::cpu6      0.858434                       # miss rate for overall accesses
+system.cpu6.l1c.overall_miss_rate::total     0.858434                       # miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 27723.807008                       # average ReadReq miss latency
+system.cpu6.l1c.ReadReq_avg_miss_latency::total 27723.807008                       # average ReadReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 38837.602338                       # average WriteReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::total 38837.602338                       # average WriteReq miss latency
+system.cpu6.l1c.demand_avg_miss_latency::cpu6 32154.925749                       # average overall miss latency
+system.cpu6.l1c.demand_avg_miss_latency::total 32154.925749                       # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::cpu6 32154.925749                       # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::total 32154.925749                       # average overall miss latency
+system.cpu6.l1c.blocked_cycles::no_mshrs      1063684                       # number of cycles access was blocked
 system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_mshrs               61695                       # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_mshrs               61545                       # number of cycles access was blocked
 system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_mshrs    17.335781                       # average number of cycles each access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_mshrs    17.283029                       # average number of cycles each access was blocked
 system.cpu6.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu6.l1c.writebacks::writebacks           9809                       # number of writebacks
-system.cpu6.l1c.writebacks::total                9809                       # number of writebacks
-system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36552                       # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_misses::total        36552                       # number of ReadReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23805                       # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::total        23805                       # number of WriteReq MSHR misses
-system.cpu6.l1c.demand_mshr_misses::cpu6        60357                       # number of demand (read+write) MSHR misses
-system.cpu6.l1c.demand_mshr_misses::total        60357                       # number of demand (read+write) MSHR misses
-system.cpu6.l1c.overall_mshr_misses::cpu6        60357                       # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_misses::total        60357                       # number of overall MSHR misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    961362717                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_latency::total    961362717                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    887609672                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::total    887609672                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1848972389                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::total   1848972389                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1848972389                       # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::total   1848972389                       # number of overall MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    744037855                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    744037855                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6   1951627727                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total   1951627727                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   2695665582                       # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::total   2695665582                       # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.805980                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.805980                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.953764                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.953764                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.858441                       # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_miss_rate::total     0.858441                       # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.858441                       # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_miss_rate::total     0.858441                       # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 26301.234324                       # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 26301.234324                       # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 37286.690695                       # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 37286.690695                       # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 30633.934573                       # average overall mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 30633.934573                       # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 30633.934573                       # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 30633.934573                       # average overall mshr miss latency
+system.cpu6.l1c.writebacks::writebacks           9842                       # number of writebacks
+system.cpu6.l1c.writebacks::total                9842                       # number of writebacks
+system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36385                       # number of ReadReq MSHR misses
+system.cpu6.l1c.ReadReq_mshr_misses::total        36385                       # number of ReadReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::cpu6        24126                       # number of WriteReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::total        24126                       # number of WriteReq MSHR misses
+system.cpu6.l1c.demand_mshr_misses::cpu6        60511                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.demand_mshr_misses::total        60511                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.overall_mshr_misses::cpu6        60511                       # number of overall MSHR misses
+system.cpu6.l1c.overall_mshr_misses::total        60511                       # number of overall MSHR misses
+system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    953086366                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_miss_latency::total    953086366                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    900293024                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::total    900293024                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1853379390                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::total   1853379390                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1853379390                       # number of overall MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::total   1853379390                       # number of overall MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    738599910                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    738599910                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6   1965255677                       # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total   1965255677                       # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   2703855587                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::total   2703855587                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.804978                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.804978                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.953974                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.953974                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.858434                       # mshr miss rate for demand accesses
+system.cpu6.l1c.demand_mshr_miss_rate::total     0.858434                       # mshr miss rate for demand accesses
+system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.858434                       # mshr miss rate for overall accesses
+system.cpu6.l1c.overall_mshr_miss_rate::total     0.858434                       # mshr miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 26194.485805                       # average ReadReq mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 26194.485805                       # average ReadReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 37316.298765                       # average WriteReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 37316.298765                       # average WriteReq mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 30628.801210                       # average overall mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::total 30628.801210                       # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 30628.801210                       # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::total 30628.801210                       # average overall mshr miss latency
 system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average ReadReq mshr uncacheable latency
 system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average WriteReq mshr uncacheable latency
@@ -917,119 +917,119 @@
 system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6          inf                       # average overall mshr uncacheable latency
 system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu7.num_reads                           99062                       # number of read accesses completed
-system.cpu7.num_writes                          54686                       # number of write accesses completed
-system.cpu7.l1c.tags.replacements               22200                       # number of replacements
-system.cpu7.l1c.tags.tagsinuse             394.753023                       # Cycle average of tags in use
-system.cpu7.l1c.tags.total_refs                 13454                       # Total number of references to valid blocks.
-system.cpu7.l1c.tags.sampled_refs               22591                       # Sample count of references to valid blocks.
-system.cpu7.l1c.tags.avg_refs                0.595547                       # Average number of references to valid blocks.
+system.cpu7.num_reads                           99565                       # number of read accesses completed
+system.cpu7.num_writes                          55051                       # number of write accesses completed
+system.cpu7.l1c.tags.replacements               22600                       # number of replacements
+system.cpu7.l1c.tags.tagsinuse             394.642544                       # Cycle average of tags in use
+system.cpu7.l1c.tags.total_refs                 13380                       # Total number of references to valid blocks.
+system.cpu7.l1c.tags.sampled_refs               22986                       # Sample count of references to valid blocks.
+system.cpu7.l1c.tags.avg_refs                0.582093                       # Average number of references to valid blocks.
 system.cpu7.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.tags.occ_blocks::cpu7      394.753023                       # Average occupied blocks per requestor
-system.cpu7.l1c.tags.occ_percent::cpu7       0.771002                       # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_percent::total      0.771002                       # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_task_id_blocks::1024          391                       # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::0          354                       # Occupied blocks per task id
+system.cpu7.l1c.tags.occ_blocks::cpu7      394.642544                       # Average occupied blocks per requestor
+system.cpu7.l1c.tags.occ_percent::cpu7       0.770786                       # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_percent::total      0.770786                       # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_task_id_blocks::1024          386                       # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::0          349                       # Occupied blocks per task id
 system.cpu7.l1c.tags.age_task_id_blocks_1024::1           37                       # Occupied blocks per task id
-system.cpu7.l1c.tags.occ_task_id_percent::1024     0.763672                       # Percentage of cache occupancy per task id
-system.cpu7.l1c.tags.tag_accesses              337139                       # Number of tag accesses
-system.cpu7.l1c.tags.data_accesses             337139                       # Number of data accesses
-system.cpu7.l1c.ReadReq_hits::cpu7               8690                       # number of ReadReq hits
-system.cpu7.l1c.ReadReq_hits::total              8690                       # number of ReadReq hits
-system.cpu7.l1c.WriteReq_hits::cpu7              1182                       # number of WriteReq hits
-system.cpu7.l1c.WriteReq_hits::total             1182                       # number of WriteReq hits
-system.cpu7.l1c.demand_hits::cpu7                9872                       # number of demand (read+write) hits
-system.cpu7.l1c.demand_hits::total               9872                       # number of demand (read+write) hits
-system.cpu7.l1c.overall_hits::cpu7               9872                       # number of overall hits
-system.cpu7.l1c.overall_hits::total              9872                       # number of overall hits
-system.cpu7.l1c.ReadReq_misses::cpu7            36466                       # number of ReadReq misses
-system.cpu7.l1c.ReadReq_misses::total           36466                       # number of ReadReq misses
-system.cpu7.l1c.WriteReq_misses::cpu7           23790                       # number of WriteReq misses
-system.cpu7.l1c.WriteReq_misses::total          23790                       # number of WriteReq misses
-system.cpu7.l1c.demand_misses::cpu7             60256                       # number of demand (read+write) misses
-system.cpu7.l1c.demand_misses::total            60256                       # number of demand (read+write) misses
-system.cpu7.l1c.overall_misses::cpu7            60256                       # number of overall misses
-system.cpu7.l1c.overall_misses::total           60256                       # number of overall misses
-system.cpu7.l1c.ReadReq_miss_latency::cpu7   1009807130                       # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_latency::total   1009807130                       # number of ReadReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::cpu7    916976125                       # number of WriteReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::total    916976125                       # number of WriteReq miss cycles
-system.cpu7.l1c.demand_miss_latency::cpu7   1926783255                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.demand_miss_latency::total   1926783255                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.overall_miss_latency::cpu7   1926783255                       # number of overall miss cycles
-system.cpu7.l1c.overall_miss_latency::total   1926783255                       # number of overall miss cycles
-system.cpu7.l1c.ReadReq_accesses::cpu7          45156                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_accesses::total         45156                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::cpu7         24972                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::total        24972                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.demand_accesses::cpu7           70128                       # number of demand (read+write) accesses
-system.cpu7.l1c.demand_accesses::total          70128                       # number of demand (read+write) accesses
-system.cpu7.l1c.overall_accesses::cpu7          70128                       # number of overall (read+write) accesses
-system.cpu7.l1c.overall_accesses::total         70128                       # number of overall (read+write) accesses
-system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.807556                       # miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_miss_rate::total     0.807556                       # miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.952667                       # miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::total     0.952667                       # miss rate for WriteReq accesses
-system.cpu7.l1c.demand_miss_rate::cpu7       0.859229                       # miss rate for demand accesses
-system.cpu7.l1c.demand_miss_rate::total      0.859229                       # miss rate for demand accesses
-system.cpu7.l1c.overall_miss_rate::cpu7      0.859229                       # miss rate for overall accesses
-system.cpu7.l1c.overall_miss_rate::total     0.859229                       # miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 27691.743816                       # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_miss_latency::total 27691.743816                       # average ReadReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 38544.603825                       # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::total 38544.603825                       # average WriteReq miss latency
-system.cpu7.l1c.demand_avg_miss_latency::cpu7 31976.620668                       # average overall miss latency
-system.cpu7.l1c.demand_avg_miss_latency::total 31976.620668                       # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::cpu7 31976.620668                       # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::total 31976.620668                       # average overall miss latency
-system.cpu7.l1c.blocked_cycles::no_mshrs      1063264                       # number of cycles access was blocked
+system.cpu7.l1c.tags.occ_task_id_percent::1024     0.753906                       # Percentage of cache occupancy per task id
+system.cpu7.l1c.tags.tag_accesses              338392                       # Number of tag accesses
+system.cpu7.l1c.tags.data_accesses             338392                       # Number of data accesses
+system.cpu7.l1c.ReadReq_hits::cpu7               8664                       # number of ReadReq hits
+system.cpu7.l1c.ReadReq_hits::total              8664                       # number of ReadReq hits
+system.cpu7.l1c.WriteReq_hits::cpu7              1142                       # number of WriteReq hits
+system.cpu7.l1c.WriteReq_hits::total             1142                       # number of WriteReq hits
+system.cpu7.l1c.demand_hits::cpu7                9806                       # number of demand (read+write) hits
+system.cpu7.l1c.demand_hits::total               9806                       # number of demand (read+write) hits
+system.cpu7.l1c.overall_hits::cpu7               9806                       # number of overall hits
+system.cpu7.l1c.overall_hits::total              9806                       # number of overall hits
+system.cpu7.l1c.ReadReq_misses::cpu7            36635                       # number of ReadReq misses
+system.cpu7.l1c.ReadReq_misses::total           36635                       # number of ReadReq misses
+system.cpu7.l1c.WriteReq_misses::cpu7           23923                       # number of WriteReq misses
+system.cpu7.l1c.WriteReq_misses::total          23923                       # number of WriteReq misses
+system.cpu7.l1c.demand_misses::cpu7             60558                       # number of demand (read+write) misses
+system.cpu7.l1c.demand_misses::total            60558                       # number of demand (read+write) misses
+system.cpu7.l1c.overall_misses::cpu7            60558                       # number of overall misses
+system.cpu7.l1c.overall_misses::total           60558                       # number of overall misses
+system.cpu7.l1c.ReadReq_miss_latency::cpu7   1023029462                       # number of ReadReq miss cycles
+system.cpu7.l1c.ReadReq_miss_latency::total   1023029462                       # number of ReadReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::cpu7    929610099                       # number of WriteReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::total    929610099                       # number of WriteReq miss cycles
+system.cpu7.l1c.demand_miss_latency::cpu7   1952639561                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.demand_miss_latency::total   1952639561                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.overall_miss_latency::cpu7   1952639561                       # number of overall miss cycles
+system.cpu7.l1c.overall_miss_latency::total   1952639561                       # number of overall miss cycles
+system.cpu7.l1c.ReadReq_accesses::cpu7          45299                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.ReadReq_accesses::total         45299                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::cpu7         25065                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::total        25065                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.demand_accesses::cpu7           70364                       # number of demand (read+write) accesses
+system.cpu7.l1c.demand_accesses::total          70364                       # number of demand (read+write) accesses
+system.cpu7.l1c.overall_accesses::cpu7          70364                       # number of overall (read+write) accesses
+system.cpu7.l1c.overall_accesses::total         70364                       # number of overall (read+write) accesses
+system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.808737                       # miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_miss_rate::total     0.808737                       # miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.954438                       # miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::total     0.954438                       # miss rate for WriteReq accesses
+system.cpu7.l1c.demand_miss_rate::cpu7       0.860639                       # miss rate for demand accesses
+system.cpu7.l1c.demand_miss_rate::total      0.860639                       # miss rate for demand accesses
+system.cpu7.l1c.overall_miss_rate::cpu7      0.860639                       # miss rate for overall accesses
+system.cpu7.l1c.overall_miss_rate::total     0.860639                       # miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 27924.920486                       # average ReadReq miss latency
+system.cpu7.l1c.ReadReq_avg_miss_latency::total 27924.920486                       # average ReadReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 38858.424905                       # average WriteReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::total 38858.424905                       # average WriteReq miss latency
+system.cpu7.l1c.demand_avg_miss_latency::cpu7 32244.122346                       # average overall miss latency
+system.cpu7.l1c.demand_avg_miss_latency::total 32244.122346                       # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::cpu7 32244.122346                       # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::total 32244.122346                       # average overall miss latency
+system.cpu7.l1c.blocked_cycles::no_mshrs      1066072                       # number of cycles access was blocked
 system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_mshrs               61445                       # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_mshrs               61535                       # number of cycles access was blocked
 system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_mshrs    17.304321                       # average number of cycles each access was blocked
+system.cpu7.l1c.avg_blocked_cycles::no_mshrs    17.324645                       # average number of cycles each access was blocked
 system.cpu7.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu7.l1c.writebacks::writebacks           9819                       # number of writebacks
-system.cpu7.l1c.writebacks::total                9819                       # number of writebacks
-system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36466                       # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_misses::total        36466                       # number of ReadReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23790                       # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::total        23790                       # number of WriteReq MSHR misses
-system.cpu7.l1c.demand_mshr_misses::cpu7        60256                       # number of demand (read+write) MSHR misses
-system.cpu7.l1c.demand_mshr_misses::total        60256                       # number of demand (read+write) MSHR misses
-system.cpu7.l1c.overall_mshr_misses::cpu7        60256                       # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_misses::total        60256                       # number of overall MSHR misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    953998318                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_miss_latency::total    953998318                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    880753723                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::total    880753723                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1834752041                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::total   1834752041                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1834752041                       # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::total   1834752041                       # number of overall MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    752742732                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    752742732                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7   1947143716                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total   1947143716                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   2699886448                       # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::total   2699886448                       # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.807556                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.807556                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.952667                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.952667                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.859229                       # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_miss_rate::total     0.859229                       # mshr miss rate for demand accesses
-system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.859229                       # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_miss_rate::total     0.859229                       # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 26161.309658                       # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 26161.309658                       # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 37022.014418                       # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 37022.014418                       # average WriteReq mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 30449.283739                       # average overall mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 30449.283739                       # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 30449.283739                       # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::total 30449.283739                       # average overall mshr miss latency
+system.cpu7.l1c.writebacks::writebacks           9831                       # number of writebacks
+system.cpu7.l1c.writebacks::total                9831                       # number of writebacks
+system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36635                       # number of ReadReq MSHR misses
+system.cpu7.l1c.ReadReq_mshr_misses::total        36635                       # number of ReadReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23923                       # number of WriteReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::total        23923                       # number of WriteReq MSHR misses
+system.cpu7.l1c.demand_mshr_misses::cpu7        60558                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.demand_mshr_misses::total        60558                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.overall_mshr_misses::cpu7        60558                       # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_misses::total        60558                       # number of overall MSHR misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    966974672                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_latency::total    966974672                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    893289987                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::total    893289987                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1860264659                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::total   1860264659                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1860264659                       # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::total   1860264659                       # number of overall MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    731988929                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    731988929                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7   1960595657                       # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total   1960595657                       # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   2692584586                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::total   2692584586                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.808737                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.808737                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.954438                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.954438                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.860639                       # mshr miss rate for demand accesses
+system.cpu7.l1c.demand_mshr_miss_rate::total     0.860639                       # mshr miss rate for demand accesses
+system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.860639                       # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_miss_rate::total     0.860639                       # mshr miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 26394.832046                       # average ReadReq mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 26394.832046                       # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 37340.215985                       # average WriteReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 37340.215985                       # average WriteReq mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 30718.726824                       # average overall mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::total 30718.726824                       # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 30718.726824                       # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::total 30718.726824                       # average overall mshr miss latency
 system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average ReadReq mshr uncacheable latency
 system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average WriteReq mshr uncacheable latency
@@ -1037,565 +1037,568 @@
 system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7          inf                       # average overall mshr uncacheable latency
 system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                    13121                       # number of replacements
-system.l2c.tags.tagsinuse                  779.163229                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     150276                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                    13897                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    10.813557                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                    12974                       # number of replacements
+system.l2c.tags.tagsinuse                  782.339791                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     149980                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                    13746                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    10.910810                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks     725.457797                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0             6.718013                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1             6.568954                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2             6.219418                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3             6.731947                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4             6.474998                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5             6.998802                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6             6.991847                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7             7.001453                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.708455                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0            0.006561                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1            0.006415                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2            0.006074                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3            0.006574                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu4            0.006323                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu5            0.006835                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu6            0.006828                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu7            0.006837                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.760902                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024          776                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          566                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          210                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.757812                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  1961425                       # Number of tag accesses
-system.l2c.tags.data_accesses                 1961425                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0                   10794                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1                   10766                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2                   10683                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3                   10661                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu4                   10692                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu5                   10671                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu6                   10889                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu7                   10673                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                  85829                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks           75598                       # number of Writeback hits
-system.l2c.Writeback_hits::total                75598                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0                  353                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1                  323                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2                  342                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3                  334                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4                  356                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5                  330                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6                  361                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7                  346                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                2745                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0                  1821                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1                  1892                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2                  1947                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3                  1893                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu4                  1947                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu5                  1922                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu6                  1886                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu7                  1863                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                15171                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0                    12615                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1                    12658                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2                    12630                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3                    12554                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu4                    12639                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu5                    12593                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu6                    12775                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu7                    12536                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  101000                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0                   12615                       # number of overall hits
-system.l2c.overall_hits::cpu1                   12658                       # number of overall hits
-system.l2c.overall_hits::cpu2                   12630                       # number of overall hits
-system.l2c.overall_hits::cpu3                   12554                       # number of overall hits
-system.l2c.overall_hits::cpu4                   12639                       # number of overall hits
-system.l2c.overall_hits::cpu5                   12593                       # number of overall hits
-system.l2c.overall_hits::cpu6                   12775                       # number of overall hits
-system.l2c.overall_hits::cpu7                   12536                       # number of overall hits
-system.l2c.overall_hits::total                 101000                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0                   705                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1                   721                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2                   716                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3                   685                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu4                   694                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu5                   690                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu6                   691                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu7                   715                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                 5617                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0               1952                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1               1935                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2               1970                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3               1832                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu4               1968                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu5               1954                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu6               1963                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu7               1919                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             15493                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0                4418                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1                4338                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2                4348                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3                4457                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu4                4447                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu5                4501                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu6                4407                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu7                4373                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total              35289                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0                   5123                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1                   5059                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2                   5064                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3                   5142                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu4                   5141                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu5                   5191                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu6                   5098                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu7                   5088                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                 40906                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0                  5123                       # number of overall misses
-system.l2c.overall_misses::cpu1                  5059                       # number of overall misses
-system.l2c.overall_misses::cpu2                  5064                       # number of overall misses
-system.l2c.overall_misses::cpu3                  5142                       # number of overall misses
-system.l2c.overall_misses::cpu4                  5141                       # number of overall misses
-system.l2c.overall_misses::cpu5                  5191                       # number of overall misses
-system.l2c.overall_misses::cpu6                  5098                       # number of overall misses
-system.l2c.overall_misses::cpu7                  5088                       # number of overall misses
-system.l2c.overall_misses::total                40906                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0        42571447                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1        44584934                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2        43709432                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3        42098938                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu4        42802932                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu5        42467936                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu6        42434429                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu7        44394419                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total      345064467                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0     57799000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1     58024000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2     57179999                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu3     53990500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu4     56201500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu5     57084499                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu6     56659000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu7     56222499                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    453160997                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0     241579958                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1     237098460                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2     238347956                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3     243950461                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu4     243322462                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu5     246152957                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu6     241076464                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu7     238492966                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   1930021684                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0        284151405                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1        281683394                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2        282057388                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3        286049399                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu4        286125394                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu5        288620893                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu6        283510893                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu7        282887385                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      2275086151                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0       284151405                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1       281683394                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2       282057388                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3       286049399                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu4       286125394                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu5       288620893                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu6       283510893                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu7       282887385                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     2275086151                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0               11499                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1               11487                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2               11399                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3               11346                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu4               11386                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu5               11361                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu6               11580                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu7               11388                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total              91446                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks        75598                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total            75598                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0             2305                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1             2258                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2             2312                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3             2166                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu4             2324                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu5             2284                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu6             2324                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu7             2265                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           18238                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0              6239                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1              6230                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2              6295                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3              6350                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu4              6394                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu5              6423                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu6              6293                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu7              6236                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total            50460                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0                17738                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1                17717                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2                17694                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3                17696                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu4                17780                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu5                17784                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu6                17873                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu7                17624                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              141906                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0               17738                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1               17717                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2               17694                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3               17696                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu4               17780                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu5               17784                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu6               17873                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu7               17624                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             141906                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0           0.061310                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1           0.062767                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2           0.062813                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3           0.060374                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu4           0.060952                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu5           0.060734                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu6           0.059672                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu7           0.062785                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.061424                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0        0.846855                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1        0.856953                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2        0.852076                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3        0.845799                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu4        0.846816                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu5        0.855517                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu6        0.844664                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu7        0.847241                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.849490                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0         0.708126                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1         0.696308                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2         0.690707                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3         0.701890                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu4         0.695496                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu5         0.700763                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu6         0.700302                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu7         0.701251                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.699346                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0            0.288815                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1            0.285545                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2            0.286199                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3            0.290574                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu4            0.289145                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu5            0.291892                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu6            0.285235                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu7            0.288697                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.288261                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0           0.288815                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1           0.285545                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2           0.286199                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3           0.290574                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu4           0.289145                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu5           0.291892                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu6           0.285235                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu7           0.288697                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.288261                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0 60385.031206                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1 61837.633842                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2 61046.692737                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3 61458.303650                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu4 61675.694524                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu5 61547.733333                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu6 61410.172214                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu7 62090.096503                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 61432.164323                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0 29610.143443                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1 29986.563307                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2 29025.380203                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3 29470.796943                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu4 28557.672764                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu5 29214.175537                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu6 28863.474274                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu7 29297.810839                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 29249.402763                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0 54680.841557                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1 54656.168741                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2 54817.837167                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3 54734.229527                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu4 54716.092197                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu5 54688.504110                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu6 54703.077831                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu7 54537.609421                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 54691.878036                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0 55465.821784                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1 55679.658826                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2 55698.536335                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3 55629.988137                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu4 55655.591130                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu5 55600.249085                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu6 55612.179874                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu7 55598.935731                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 55617.419229                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0 55465.821784                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1 55679.658826                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2 55698.536335                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3 55629.988137                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu4 55655.591130                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu5 55600.249085                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu6 55612.179874                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu7 55598.935731                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 55617.419229                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs             10446                       # number of cycles access was blocked
+system.l2c.tags.occ_blocks::writebacks     728.962494                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0             6.892190                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1             7.186949                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2             6.375204                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3             6.806314                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu4             6.399875                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu5             6.389081                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu6             6.432209                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu7             6.895475                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.711877                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0            0.006731                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1            0.007019                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2            0.006226                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3            0.006647                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu4            0.006250                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu5            0.006239                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu6            0.006281                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu7            0.006734                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.764004                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024          772                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          551                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          221                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.753906                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  1963370                       # Number of tag accesses
+system.l2c.tags.data_accesses                 1963370                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0                   10704                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1                   10790                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2                   10626                       # number of ReadReq hits
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+system.l2c.ReadReq_hits::total                  85605                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks           75955                       # number of Writeback hits
+system.l2c.Writeback_hits::total                75955                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0                  335                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1                  339                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2                  335                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu3                  336                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu4                  340                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu5                  357                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu6                  325                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu7                  325                       # number of UpgradeReq hits
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+system.l2c.overall_hits::total                 100988                       # number of overall hits
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+system.l2c.UpgradeReq_misses::cpu0               1986                       # number of UpgradeReq misses
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+system.l2c.UpgradeReq_misses::cpu4               1955                       # number of UpgradeReq misses
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+system.l2c.UpgradeReq_misses::total             15600                       # number of UpgradeReq misses
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+system.l2c.UpgradeReq_miss_latency::cpu1     55902999                       # number of UpgradeReq miss cycles
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+system.l2c.Writeback_accesses::total            75955                       # number of Writeback accesses(hits+misses)
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+system.l2c.UpgradeReq_miss_rate::cpu0        0.855666                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1        0.851316                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2        0.848485                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3        0.851262                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu4        0.851852                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu5        0.845855                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu6        0.859732                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu7        0.858264                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.852832                       # miss rate for UpgradeReq accesses
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+system.l2c.ReadExReq_miss_rate::cpu3         0.691139                       # miss rate for ReadExReq accesses
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+system.l2c.ReadExReq_miss_rate::cpu5         0.698440                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu6         0.698475                       # miss rate for ReadExReq accesses
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+system.l2c.ReadExReq_miss_rate::total        0.696234                       # miss rate for ReadExReq accesses
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+system.l2c.demand_miss_rate::cpu3            0.284999                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu4            0.288070                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu5            0.287390                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu6            0.289131                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu7            0.288388                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.287522                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0           0.288053                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1           0.286515                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2           0.287653                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3           0.284999                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu4           0.288070                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu5           0.287390                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu6           0.289131                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu7           0.288388                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.287522                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0 60808.873134                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1 62076.071932                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2 61198.879009                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3 61331.572662                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu4 60844.688060                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu5 61500.640351                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu6 62161.076119                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu7 61902.279494                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 61484.075146                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0 28751.761833                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1 28801.132921                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2 28650.052772                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu3 29156.526261                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu4 29231.968798                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu5 29527.054620                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu6 29232.680723                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu7 28763.719004                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 29016.025321                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0 54649.507751                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1 54681.148922                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2 54684.195389                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3 54775.745879                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu4 54646.875903                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu5 54716.441786                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu6 54656.417736                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu7 54569.028708                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 54672.264054                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0 55455.361062                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1 55706.373876                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2 55566.191237                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3 55675.666798                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu4 55460.779106                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu5 55631.165188                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu6 55639.817133                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu7 55592.607332                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 55590.890784                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0 55455.361062                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1 55706.373876                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2 55566.191237                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3 55675.666798                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu4 55460.779106                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu5 55631.165188                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu6 55639.817133                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu7 55592.607332                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 55590.890784                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs             10498                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                     1464                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                     1439                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      7.135246                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs      7.295344                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks                6250                       # number of writebacks
-system.l2c.writebacks::total                     6250                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0                  7                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1                  7                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu2                  4                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu3                  9                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu4                  6                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu5                  3                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu6                  7                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu7                  6                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                49                       # number of ReadReq MSHR hits
+system.l2c.writebacks::writebacks                6042                       # number of writebacks
+system.l2c.writebacks::total                     6042                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0                  8                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1                  4                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu2                  8                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu3                  4                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu4                  7                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu5                  7                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu6                  8                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu7                  5                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                51                       # number of ReadReq MSHR hits
 system.l2c.UpgradeReq_mshr_hits::cpu0               1                       # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::total              1                       # number of UpgradeReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu0                2                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu1                3                       # number of ReadExReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu3               1                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu7               1                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::total              3                       # number of UpgradeReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu0                6                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu1                5                       # number of ReadExReq MSHR hits
 system.l2c.ReadExReq_mshr_hits::cpu2                3                       # number of ReadExReq MSHR hits
 system.l2c.ReadExReq_mshr_hits::cpu3                1                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu4                2                       # number of ReadExReq MSHR hits
 system.l2c.ReadExReq_mshr_hits::cpu5                2                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu6                1                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu7                3                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::total              15                       # number of ReadExReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0                   9                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1                  10                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2                   7                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3                  10                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu4                   6                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu5                   5                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu6                   8                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu7                   9                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 64                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0                  9                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1                 10                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2                  7                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3                 10                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu4                  6                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu5                  5                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu6                  8                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu7                  9                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                64                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0              698                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1              714                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2              712                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3              676                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu4              688                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu5              687                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu6              684                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu7              709                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total            5568                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0          1951                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1          1935                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2          1970                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3          1832                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu4          1968                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu5          1954                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu6          1963                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu7          1919                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        15492                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0           4416                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1           4335                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2           4345                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3           4456                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu4           4447                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu5           4499                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu6           4406                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu7           4370                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         35274                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0              5114                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1              5049                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2              5057                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3              5132                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu4              5135                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu5              5186                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu6              5090                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu7              5079                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total            40842                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0             5114                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1             5049                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2             5057                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3             5132                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu4             5135                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu5             5186                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu6             5090                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu7             5079                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total           40842                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0     33845945                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1     35679430                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2     34970423                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3     33623934                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu4     34265930                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu5     34048934                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu6     33977929                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu7     35572914                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    275985439                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0     81779494                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1     81207491                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2     82576991                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3     76840996                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu4     82448987                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu5     81922493                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu6     82161995                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu7     80384488                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    649322935                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0    187970446                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1    184467447                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2    185588937                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3    189921941                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu4    189397436                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu5    191605943                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu6    187621956                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu7    185423942                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   1501998048                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0    221816391                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1    220146877                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2    220559360                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3    223545875                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu4    223663366                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu5    225654877                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu6    221599885                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu7    220996856                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   1777983487                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0    221816391                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1    220146877                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2    220559360                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3    223545875                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu4    223663366                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu5    225654877                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu6    221599885                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu7    220996856                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   1777983487                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    420548415                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    410318426                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    408411942                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    419559934                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    403725937                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    410458428                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    413026934                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    417703437                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   3303753453                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    230815972                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    233216955                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    233429960                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    229986451                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    230895448                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    235553969                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    233378955                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    230983963                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1858261673                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0    651364387                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1    643535381                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2    641841902                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu3    649546385                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu4    634621385                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu5    646012397                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu6    646405889                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu7    648687400                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   5162015126                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0      0.060701                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1      0.062157                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2      0.062462                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3      0.059580                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu4      0.060425                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu5      0.060470                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu6      0.059067                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu7      0.062259                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.060888                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.846421                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.856953                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.852076                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.845799                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.846816                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.855517                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.844664                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.847241                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.849435                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.707806                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.695827                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.690230                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.701732                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.695496                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.700452                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.700143                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.700770                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.699049                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0       0.288308                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1       0.284981                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2       0.285803                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3       0.290009                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu4       0.288808                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu5       0.291610                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu6       0.284787                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu7       0.288187                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.287810                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0      0.288308                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1      0.284981                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2      0.285803                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3      0.290009                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu4      0.288808                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu5      0.291610                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu6      0.284787                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu7      0.288187                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.287810                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 48489.892550                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49971.190476                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 49115.762640                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49739.547337                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49805.130814                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49561.767103                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49675.334795                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50173.362482                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 49566.350395                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41916.706304                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41967.695607                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41917.254315                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41943.775109                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41894.810467                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41925.533777                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41855.320937                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41888.737884                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41913.434999                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 42565.771286                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 42553.044291                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42713.219102                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42621.620512                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42589.933888                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42588.562569                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 42583.285520                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42431.108009                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 42580.882463                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0 43374.343176                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1 43602.075064                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2 43614.664821                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3 43559.211808                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu4 43556.643817                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu5 43512.317200                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu6 43536.323183                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu7 43511.883442                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 43533.213040                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0 43374.343176                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1 43602.075064                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2 43614.664821                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3 43559.211808                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu4 43556.643817                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu5 43512.317200                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu6 43536.323183                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu7 43511.883442                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 43533.213040                       # average overall mshr miss latency
+system.l2c.ReadExReq_mshr_hits::cpu6                2                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu7                2                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::total              23                       # number of ReadExReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0                  14                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1                   9                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2                  11                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3                   5                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu4                   9                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu5                   9                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu6                  10                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu7                   7                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 74                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0                 14                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1                  9                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2                 11                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3                  5                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu4                  9                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu5                  9                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu6                 10                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu7                  7                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                74                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0              662                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1              705                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2              678                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3              691                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu4              663                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu5              677                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu6              662                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu7              707                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total            5445                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0          1985                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1          1941                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2          1876                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3          1922                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu4          1955                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu5          1959                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu6          1992                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu7          1967                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        15597                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0           4445                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1           4400                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2           4378                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu3           4367                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu4           4430                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu5           4387                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu6           4441                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu7           4387                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         35235                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0              5107                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1              5105                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2              5056                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3              5058                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu4              5093                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu5              5064                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu6              5103                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu7              5094                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            40680                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0             5107                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1             5105                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2             5056                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3             5058                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu4             5093                       # number of overall MSHR misses
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+system.l2c.overall_mshr_misses::cpu6             5103                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu7             5094                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           40680                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0     32455941                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1     35292936                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2     33520926                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3     34166439                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu4     32539439                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu5     33571932                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu6     33370421                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu7     35357421                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total    270275455                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0     83067491                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1     81344988                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2     78653997                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3     80593493                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu4     81980984                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu5     82268488                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu6     83402478                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu7     82404992                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    653716911                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0    189131446                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1    187405945                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2    186408946                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3    186284944                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu4    188429940                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu5    186911948                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu6    188992946                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu7    186252939                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   1499819054                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0    221587387                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1    222698881                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2    219929872                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3    220451383                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu4    220969379                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu5    220483880                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu6    222363367                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu7    221610360                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   1770094509                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0    221587387                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1    222698881                       # number of overall MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::cpu4    220969379                       # number of overall MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::cpu6    222363367                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu7    221610360                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   1770094509                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    412646911                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    419015931                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    413234441                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    407408946                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    415648431                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    408376439                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    410035928                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    406831940                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   3293198967                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    229215970                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    228786954                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    227259971                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    236423452                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    233573451                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    234334469                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    233635458                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    232899980                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1856129705                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0    641862881                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1    647802885                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2    640494412                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3    643832398                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu4    649221882                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu5    642710908                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu6    643671386                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu7    639731920                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   5149328672                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0      0.058203                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1      0.061310                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2      0.059936                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3      0.060376                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu4      0.058163                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu5      0.059553                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu6      0.058465                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu7      0.062121                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.059769                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.855235                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.851316                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.848485                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.850819                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.851852                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.845855                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.859732                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.857828                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.852668                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.694097                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.692913                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.694590                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.690981                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.701838                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.698122                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.698161                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.695576                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.695780                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0       0.287265                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1       0.286010                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2       0.287028                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3       0.284717                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4       0.287561                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5       0.286880                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6       0.288566                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7       0.287992                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.287000                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0      0.287265                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1      0.286010                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2      0.287028                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3      0.284717                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4      0.287561                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5      0.286880                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu6      0.288566                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu7      0.287992                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.287000                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 49027.101208                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 50060.902128                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 49440.893805                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49444.918958                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49079.093514                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49589.264402                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 50408.490937                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50010.496464                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 49637.365473                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41847.602519                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41908.803709                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41926.437633                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41932.098335                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41934.007161                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41995.144461                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41868.713855                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41893.742755                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41912.990383                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 42549.256693                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 42592.260227                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42578.562357                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42657.417907                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42534.975169                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42605.869159                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 42556.394055                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42455.650558                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 42566.171534                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 43388.953789                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1 43623.678942                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2 43498.787975                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3 43584.694148                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu4 43386.879835                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu5 43539.470774                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu6 43575.027827                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu7 43504.193168                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 43512.647714                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0 43388.953789                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 43623.678942                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2 43498.787975                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 43584.694148                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 43386.879835                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu5 43539.470774                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 43575.027827                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu7 43504.193168                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 43512.647714                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
@@ -1624,108 +1627,109 @@
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu7          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.snoop_filter.tot_requests        123722                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       121674                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.tot_requests        123330                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       121282                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.trans_dist::ReadReq               84424                       # Transaction distribution
-system.membus.trans_dist::ReadResp              84420                       # Transaction distribution
-system.membus.trans_dist::WriteReq              43379                       # Transaction distribution
-system.membus.trans_dist::WriteResp             43377                       # Transaction distribution
-system.membus.trans_dist::Writeback              6250                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            58661                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           47649                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             50299                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3116                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       421575                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 421575                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      1077818                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 1077818                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                            58193                       # Total snoops (count)
-system.membus.snoop_fanout::samples            123722                       # Request fanout histogram
+system.membus.trans_dist::ReadReq               84079                       # Transaction distribution
+system.membus.trans_dist::ReadResp              84076                       # Transaction distribution
+system.membus.trans_dist::WriteReq              43401                       # Transaction distribution
+system.membus.trans_dist::WriteResp             43399                       # Transaction distribution
+system.membus.trans_dist::Writeback              6042                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            58662                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           47800                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             50251                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3038                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       420748                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 420748                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      1051128                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 1051128                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                            58073                       # Total snoops (count)
+system.membus.snoop_fanout::samples            123330                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  123722    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  123330    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              123722                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           350831336                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization              48.1                       # Layer utilization (%)
-system.membus.respLayer0.occupancy          312389376                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization             42.9                       # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests       560254                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests       259972                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       298234                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_fanout::total              123330                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           349185814                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization              47.8                       # Layer utilization (%)
+system.membus.respLayer0.occupancy          311191349                       # Layer occupancy (ticks)
+system.membus.respLayer0.utilization             42.6                       # Layer utilization (%)
+system.toL2Bus.snoop_filter.tot_requests       561297                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests       261699                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       297550                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
 system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq             371185                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            371180                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             43379                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            43375                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback            75598                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           29248                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          29247                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           161278                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          161272                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       120544                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       120292                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       120322                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       120320                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       120179                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       120443                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       120589                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       120366                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                963055                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1746802                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1746902                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1761658                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1751012                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1764505                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1756981                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1763838                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1750408                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               14042106                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          322707                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples           560254                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.690126                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           1.177666                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq             370588                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            370576                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadRespWithInvalidate            3                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             43402                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            43399                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback            75955                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           29152                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          29150                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           162499                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          162497                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       120510                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       120652                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       120226                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       120519                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       120569                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       120393                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       120447                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       120346                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total                963662                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1766434                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1757944                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1752931                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1758190                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1756878                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1755329                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1752897                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1753790                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               14054393                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          323559                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples           561297                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.683086                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           1.176196                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                  52995      9.46%      9.46% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 250263     44.67%     54.13% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 141259     25.21%     79.34% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                  69446     12.40%     91.74% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                  30460      5.44%     97.17% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5                  11695      2.09%     99.26% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6                   3486      0.62%     99.88% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7                    650      0.12%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                  53942      9.61%      9.61% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 251180     44.75%     54.36% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 141382     25.19%     79.55% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                  68926     12.28%     91.83% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                  30158      5.37%     97.20% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5                  11557      2.06%     99.26% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6                   3492      0.62%     99.88% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7                    660      0.12%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              7                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             560254                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          719277462                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total             561297                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          720580520                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization             98.7                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         100586935                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         100512947                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization            13.8                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         100589620                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         100775889                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization            13.8                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         100255865                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         100644932                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization            13.8                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         100593415                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         100575951                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization            13.8                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy         100466351                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.occupancy         100528413                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer4.utilization            13.8                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy         100465013                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy         100450921                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer5.utilization            13.8                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy         100397923                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy         100623449                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer6.utilization            13.8                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy         100485866                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy         100655480                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer7.utilization            13.8                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
index b29e580..e072d02 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
@@ -1,195 +1,195 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000476                       # Number of seconds simulated
-sim_ticks                                   475552000                       # Number of ticks simulated
-final_tick                                  475552000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000473                       # Number of seconds simulated
+sim_ticks                                   473250000                       # Number of ticks simulated
+final_tick                                  473250000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                              102852654                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 276856                       # Number of bytes of host memory used
-host_seconds                                     4.62                       # Real time elapsed on the host
+host_tick_rate                              101630905                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 277340                       # Number of bytes of host memory used
+host_seconds                                     4.66                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0                 82626                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1                 79372                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2                 82635                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3                 78892                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4                 79911                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5                 82560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6                 82806                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7                 80499                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               649301                       # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks       411072                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0               5529                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1               5498                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2               5527                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3               5416                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4               5415                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5               5350                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6               5500                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7               5539                       # Number of bytes written to this memory
-system.physmem.bytes_written::total            454846                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0                  10995                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1                  10954                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2                  10941                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3                  10978                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4                  11115                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5                  11118                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6                  11112                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7                  10947                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 88160                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks            6423                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0                  5529                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1                  5498                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2                  5527                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3                  5416                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4                  5415                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5                  5350                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6                  5500                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7                  5539                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                50197                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0                173747561                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1                166904986                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2                173766486                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3                165895633                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4                168038406                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5                173608775                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6                174126068                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7                169274864                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1365362778                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         864410201                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0                11626489                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1                11561301                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2                11622283                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3                11388870                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4                11386767                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5                11250084                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6                11565507                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7                11647517                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              956459020                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         864410201                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0               185374050                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1               178466288                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2               185388769                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3               177284503                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4               179425173                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5               184858859                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6               185691575                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7               180922381                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2321821799                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0                 80424                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1                 83171                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2                 80813                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3                 86214                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4                 79490                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5                 82665                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6                 85333                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7                 80902                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               659012                       # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks       419392                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0               5460                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1               5448                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2               5355                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3               5405                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4               5451                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5               5481                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6               5462                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7               5450                       # Number of bytes written to this memory
+system.physmem.bytes_written::total            462904                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0                  11061                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1                  10973                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2                  10946                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3                  11055                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4                  10883                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5                  10908                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6                  11056                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7                  10909                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 87791                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks            6553                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0                  5460                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1                  5448                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2                  5355                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3                  5405                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4                  5451                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5                  5481                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6                  5462                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7                  5450                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                50065                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0                169939778                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1                175744321                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2                170761754                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3                182174326                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4                167966191                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5                174675119                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6                180312731                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7                170949815                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1392524036                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         886195457                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0                11537242                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1                11511886                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2                11315372                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3                11421025                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4                11518225                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5                11581616                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6                11541469                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7                11516112                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              978138405                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         886195457                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0               181477021                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1               187256207                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2               182077126                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3               193595351                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4               179484416                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5               186256735                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6               191854200                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7               182465927                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2370662441                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.num_reads                          100000                       # number of read accesses completed
-system.cpu0.num_writes                          55373                       # number of write accesses completed
-system.cpu0.l1c.tags.replacements               22370                       # number of replacements
-system.cpu0.l1c.tags.tagsinuse             390.859535                       # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs                 13365                       # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs               22757                       # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs                0.587292                       # Average number of references to valid blocks.
+system.cpu0.num_reads                           98988                       # number of read accesses completed
+system.cpu0.num_writes                          54550                       # number of write accesses completed
+system.cpu0.l1c.tags.replacements               22171                       # number of replacements
+system.cpu0.l1c.tags.tagsinuse             391.248330                       # Cycle average of tags in use
+system.cpu0.l1c.tags.total_refs                 13318                       # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs               22569                       # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs                0.590101                       # Average number of references to valid blocks.
 system.cpu0.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0      390.859535                       # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0       0.763398                       # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total      0.763398                       # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_task_id_blocks::1024          387                       # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::0          381                       # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
-system.cpu0.l1c.tags.occ_task_id_percent::1024     0.755859                       # Percentage of cache occupancy per task id
-system.cpu0.l1c.tags.tag_accesses              338979                       # Number of tag accesses
-system.cpu0.l1c.tags.data_accesses             338979                       # Number of data accesses
-system.cpu0.l1c.ReadReq_hits::cpu0               8642                       # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total              8642                       # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0              1137                       # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total             1137                       # number of WriteReq hits
-system.cpu0.l1c.demand_hits::cpu0                9779                       # number of demand (read+write) hits
-system.cpu0.l1c.demand_hits::total               9779                       # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0               9779                       # number of overall hits
-system.cpu0.l1c.overall_hits::total              9779                       # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0            36791                       # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total           36791                       # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0           23910                       # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total          23910                       # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0             60701                       # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total            60701                       # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0            60701                       # number of overall misses
-system.cpu0.l1c.overall_misses::total           60701                       # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0    598271123                       # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total    598271123                       # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0    653921249                       # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total    653921249                       # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency::cpu0   1252192372                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_latency::total   1252192372                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency::cpu0   1252192372                       # number of overall miss cycles
-system.cpu0.l1c.overall_miss_latency::total   1252192372                       # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0          45433                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total         45433                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0         25047                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total        25047                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses::cpu0           70480                       # number of demand (read+write) accesses
-system.cpu0.l1c.demand_accesses::total          70480                       # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses::cpu0          70480                       # number of overall (read+write) accesses
-system.cpu0.l1c.overall_accesses::total         70480                       # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.809786                       # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total     0.809786                       # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.954605                       # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total     0.954605                       # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0       0.861251                       # miss rate for demand accesses
-system.cpu0.l1c.demand_miss_rate::total      0.861251                       # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate::cpu0      0.861251                       # miss rate for overall accesses
-system.cpu0.l1c.overall_miss_rate::total     0.861251                       # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16261.344432                       # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 16261.344432                       # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 27349.278503                       # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 27349.278503                       # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 20628.859030                       # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 20628.859030                       # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 20628.859030                       # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 20628.859030                       # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs       775639                       # number of cycles access was blocked
+system.cpu0.l1c.tags.occ_blocks::cpu0      391.248330                       # Average occupied blocks per requestor
+system.cpu0.l1c.tags.occ_percent::cpu0       0.764157                       # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_percent::total      0.764157                       # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_task_id_blocks::1024          398                       # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::0          390                       # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
+system.cpu0.l1c.tags.occ_task_id_percent::1024     0.777344                       # Percentage of cache occupancy per task id
+system.cpu0.l1c.tags.tag_accesses              335805                       # Number of tag accesses
+system.cpu0.l1c.tags.data_accesses             335805                       # Number of data accesses
+system.cpu0.l1c.ReadReq_hits::cpu0               8501                       # number of ReadReq hits
+system.cpu0.l1c.ReadReq_hits::total              8501                       # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits::cpu0              1143                       # number of WriteReq hits
+system.cpu0.l1c.WriteReq_hits::total             1143                       # number of WriteReq hits
+system.cpu0.l1c.demand_hits::cpu0                9644                       # number of demand (read+write) hits
+system.cpu0.l1c.demand_hits::total               9644                       # number of demand (read+write) hits
+system.cpu0.l1c.overall_hits::cpu0               9644                       # number of overall hits
+system.cpu0.l1c.overall_hits::total              9644                       # number of overall hits
+system.cpu0.l1c.ReadReq_misses::cpu0            36474                       # number of ReadReq misses
+system.cpu0.l1c.ReadReq_misses::total           36474                       # number of ReadReq misses
+system.cpu0.l1c.WriteReq_misses::cpu0           23719                       # number of WriteReq misses
+system.cpu0.l1c.WriteReq_misses::total          23719                       # number of WriteReq misses
+system.cpu0.l1c.demand_misses::cpu0             60193                       # number of demand (read+write) misses
+system.cpu0.l1c.demand_misses::total            60193                       # number of demand (read+write) misses
+system.cpu0.l1c.overall_misses::cpu0            60193                       # number of overall misses
+system.cpu0.l1c.overall_misses::total           60193                       # number of overall misses
+system.cpu0.l1c.ReadReq_miss_latency::cpu0    587864141                       # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_latency::total    587864141                       # number of ReadReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::cpu0    652231215                       # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::total    652231215                       # number of WriteReq miss cycles
+system.cpu0.l1c.demand_miss_latency::cpu0   1240095356                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_latency::total   1240095356                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.overall_miss_latency::cpu0   1240095356                       # number of overall miss cycles
+system.cpu0.l1c.overall_miss_latency::total   1240095356                       # number of overall miss cycles
+system.cpu0.l1c.ReadReq_accesses::cpu0          44975                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_accesses::total         44975                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::cpu0         24862                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::total        24862                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.demand_accesses::cpu0           69837                       # number of demand (read+write) accesses
+system.cpu0.l1c.demand_accesses::total          69837                       # number of demand (read+write) accesses
+system.cpu0.l1c.overall_accesses::cpu0          69837                       # number of overall (read+write) accesses
+system.cpu0.l1c.overall_accesses::total         69837                       # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.810984                       # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_miss_rate::total     0.810984                       # miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.954026                       # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::total     0.954026                       # miss rate for WriteReq accesses
+system.cpu0.l1c.demand_miss_rate::cpu0       0.861907                       # miss rate for demand accesses
+system.cpu0.l1c.demand_miss_rate::total      0.861907                       # miss rate for demand accesses
+system.cpu0.l1c.overall_miss_rate::cpu0      0.861907                       # miss rate for overall accesses
+system.cpu0.l1c.overall_miss_rate::total     0.861907                       # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16117.347727                       # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_miss_latency::total 16117.347727                       # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 27498.259412                       # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::total 27498.259412                       # average WriteReq miss latency
+system.cpu0.l1c.demand_avg_miss_latency::cpu0 20601.986211                       # average overall miss latency
+system.cpu0.l1c.demand_avg_miss_latency::total 20601.986211                       # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 20601.986211                       # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::total 20601.986211                       # average overall miss latency
+system.cpu0.l1c.blocked_cycles::no_mshrs       773904                       # number of cycles access was blocked
 system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs               66482                       # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs               66096                       # number of cycles access was blocked
 system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs    11.666902                       # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs    11.708787                       # average number of cycles each access was blocked
 system.cpu0.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks           9788                       # number of writebacks
-system.cpu0.l1c.writebacks::total                9788                       # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36791                       # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total        36791                       # number of ReadReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23910                       # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::total        23910                       # number of WriteReq MSHR misses
-system.cpu0.l1c.demand_mshr_misses::cpu0        60701                       # number of demand (read+write) MSHR misses
-system.cpu0.l1c.demand_mshr_misses::total        60701                       # number of demand (read+write) MSHR misses
-system.cpu0.l1c.overall_mshr_misses::cpu0        60701                       # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_misses::total        60701                       # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    540766367                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total    540766367                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    617095733                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total    617095733                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1157862100                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::total   1157862100                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1157862100                       # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total   1157862100                       # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    641214054                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    641214054                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0    990476120                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total    990476120                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   1631690174                       # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total   1631690174                       # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.809786                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.809786                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.954605                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.954605                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.861251                       # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_miss_rate::total     0.861251                       # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.861251                       # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total     0.861251                       # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 14698.332935                       # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 14698.332935                       # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 25809.106357                       # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 25809.106357                       # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19074.843907                       # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19074.843907                       # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19074.843907                       # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19074.843907                       # average overall mshr miss latency
+system.cpu0.l1c.writebacks::writebacks           9687                       # number of writebacks
+system.cpu0.l1c.writebacks::total                9687                       # number of writebacks
+system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36474                       # number of ReadReq MSHR misses
+system.cpu0.l1c.ReadReq_mshr_misses::total        36474                       # number of ReadReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23719                       # number of WriteReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::total        23719                       # number of WriteReq MSHR misses
+system.cpu0.l1c.demand_mshr_misses::cpu0        60193                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.demand_mshr_misses::total        60193                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.overall_mshr_misses::cpu0        60193                       # number of overall MSHR misses
+system.cpu0.l1c.overall_mshr_misses::total        60193                       # number of overall MSHR misses
+system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    531003039                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_miss_latency::total    531003039                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    615653301                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::total    615653301                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1146656340                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::total   1146656340                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1146656340                       # number of overall MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::total   1146656340                       # number of overall MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    646054384                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    646054384                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0    971060215                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total    971060215                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   1617114599                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::total   1617114599                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.810984                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.810984                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.954026                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.954026                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.861907                       # mshr miss rate for demand accesses
+system.cpu0.l1c.demand_mshr_miss_rate::total     0.861907                       # mshr miss rate for demand accesses
+system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.861907                       # mshr miss rate for overall accesses
+system.cpu0.l1c.overall_mshr_miss_rate::total     0.861907                       # mshr miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 14558.398832                       # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 14558.398832                       # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 25956.123825                       # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 25956.123825                       # average WriteReq mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19049.662585                       # average overall mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19049.662585                       # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19049.662585                       # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19049.662585                       # average overall mshr miss latency
 system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average WriteReq mshr uncacheable latency
@@ -197,119 +197,119 @@
 system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0          inf                       # average overall mshr uncacheable latency
 system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu1.num_reads                           99552                       # number of read accesses completed
-system.cpu1.num_writes                          55312                       # number of write accesses completed
-system.cpu1.l1c.tags.replacements               22247                       # number of replacements
-system.cpu1.l1c.tags.tagsinuse             391.170580                       # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs                 13534                       # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs               22643                       # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs                0.597712                       # Average number of references to valid blocks.
+system.cpu1.num_reads                           99262                       # number of read accesses completed
+system.cpu1.num_writes                          54743                       # number of write accesses completed
+system.cpu1.l1c.tags.replacements               22415                       # number of replacements
+system.cpu1.l1c.tags.tagsinuse             391.761420                       # Cycle average of tags in use
+system.cpu1.l1c.tags.total_refs                 13414                       # Total number of references to valid blocks.
+system.cpu1.l1c.tags.sampled_refs               22814                       # Sample count of references to valid blocks.
+system.cpu1.l1c.tags.avg_refs                0.587972                       # Average number of references to valid blocks.
 system.cpu1.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1      391.170580                       # Average occupied blocks per requestor
-system.cpu1.l1c.tags.occ_percent::cpu1       0.764005                       # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_percent::total      0.764005                       # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_task_id_blocks::1024          396                       # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::0          389                       # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
-system.cpu1.l1c.tags.occ_task_id_percent::1024     0.773438                       # Percentage of cache occupancy per task id
-system.cpu1.l1c.tags.tag_accesses              338702                       # Number of tag accesses
-system.cpu1.l1c.tags.data_accesses             338702                       # Number of data accesses
-system.cpu1.l1c.ReadReq_hits::cpu1               8670                       # number of ReadReq hits
-system.cpu1.l1c.ReadReq_hits::total              8670                       # number of ReadReq hits
-system.cpu1.l1c.WriteReq_hits::cpu1              1145                       # number of WriteReq hits
-system.cpu1.l1c.WriteReq_hits::total             1145                       # number of WriteReq hits
-system.cpu1.l1c.demand_hits::cpu1                9815                       # number of demand (read+write) hits
-system.cpu1.l1c.demand_hits::total               9815                       # number of demand (read+write) hits
-system.cpu1.l1c.overall_hits::cpu1               9815                       # number of overall hits
-system.cpu1.l1c.overall_hits::total              9815                       # number of overall hits
-system.cpu1.l1c.ReadReq_misses::cpu1            36464                       # number of ReadReq misses
-system.cpu1.l1c.ReadReq_misses::total           36464                       # number of ReadReq misses
-system.cpu1.l1c.WriteReq_misses::cpu1           24184                       # number of WriteReq misses
-system.cpu1.l1c.WriteReq_misses::total          24184                       # number of WriteReq misses
-system.cpu1.l1c.demand_misses::cpu1             60648                       # number of demand (read+write) misses
-system.cpu1.l1c.demand_misses::total            60648                       # number of demand (read+write) misses
-system.cpu1.l1c.overall_misses::cpu1            60648                       # number of overall misses
-system.cpu1.l1c.overall_misses::total           60648                       # number of overall misses
-system.cpu1.l1c.ReadReq_miss_latency::cpu1    591998971                       # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_latency::total    591998971                       # number of ReadReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::cpu1    660686123                       # number of WriteReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::total    660686123                       # number of WriteReq miss cycles
-system.cpu1.l1c.demand_miss_latency::cpu1   1252685094                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.demand_miss_latency::total   1252685094                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.overall_miss_latency::cpu1   1252685094                       # number of overall miss cycles
-system.cpu1.l1c.overall_miss_latency::total   1252685094                       # number of overall miss cycles
-system.cpu1.l1c.ReadReq_accesses::cpu1          45134                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_accesses::total         45134                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::cpu1         25329                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::total        25329                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.demand_accesses::cpu1           70463                       # number of demand (read+write) accesses
-system.cpu1.l1c.demand_accesses::total          70463                       # number of demand (read+write) accesses
-system.cpu1.l1c.overall_accesses::cpu1          70463                       # number of overall (read+write) accesses
-system.cpu1.l1c.overall_accesses::total         70463                       # number of overall (read+write) accesses
-system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.807905                       # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_miss_rate::total     0.807905                       # miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.954795                       # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::total     0.954795                       # miss rate for WriteReq accesses
-system.cpu1.l1c.demand_miss_rate::cpu1       0.860707                       # miss rate for demand accesses
-system.cpu1.l1c.demand_miss_rate::total      0.860707                       # miss rate for demand accesses
-system.cpu1.l1c.overall_miss_rate::cpu1      0.860707                       # miss rate for overall accesses
-system.cpu1.l1c.overall_miss_rate::total     0.860707                       # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16235.162654                       # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 16235.162654                       # average ReadReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 27319.141705                       # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::total 27319.141705                       # average WriteReq miss latency
-system.cpu1.l1c.demand_avg_miss_latency::cpu1 20655.010784                       # average overall miss latency
-system.cpu1.l1c.demand_avg_miss_latency::total 20655.010784                       # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 20655.010784                       # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 20655.010784                       # average overall miss latency
-system.cpu1.l1c.blocked_cycles::no_mshrs       776857                       # number of cycles access was blocked
+system.cpu1.l1c.tags.occ_blocks::cpu1      391.761420                       # Average occupied blocks per requestor
+system.cpu1.l1c.tags.occ_percent::cpu1       0.765159                       # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_percent::total      0.765159                       # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_task_id_blocks::1024          399                       # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::0          391                       # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
+system.cpu1.l1c.tags.occ_task_id_percent::1024     0.779297                       # Percentage of cache occupancy per task id
+system.cpu1.l1c.tags.tag_accesses              336589                       # Number of tag accesses
+system.cpu1.l1c.tags.data_accesses             336589                       # Number of data accesses
+system.cpu1.l1c.ReadReq_hits::cpu1               8598                       # number of ReadReq hits
+system.cpu1.l1c.ReadReq_hits::total              8598                       # number of ReadReq hits
+system.cpu1.l1c.WriteReq_hits::cpu1              1162                       # number of WriteReq hits
+system.cpu1.l1c.WriteReq_hits::total             1162                       # number of WriteReq hits
+system.cpu1.l1c.demand_hits::cpu1                9760                       # number of demand (read+write) hits
+system.cpu1.l1c.demand_hits::total               9760                       # number of demand (read+write) hits
+system.cpu1.l1c.overall_hits::cpu1               9760                       # number of overall hits
+system.cpu1.l1c.overall_hits::total              9760                       # number of overall hits
+system.cpu1.l1c.ReadReq_misses::cpu1            36477                       # number of ReadReq misses
+system.cpu1.l1c.ReadReq_misses::total           36477                       # number of ReadReq misses
+system.cpu1.l1c.WriteReq_misses::cpu1           23776                       # number of WriteReq misses
+system.cpu1.l1c.WriteReq_misses::total          23776                       # number of WriteReq misses
+system.cpu1.l1c.demand_misses::cpu1             60253                       # number of demand (read+write) misses
+system.cpu1.l1c.demand_misses::total            60253                       # number of demand (read+write) misses
+system.cpu1.l1c.overall_misses::cpu1            60253                       # number of overall misses
+system.cpu1.l1c.overall_misses::total           60253                       # number of overall misses
+system.cpu1.l1c.ReadReq_miss_latency::cpu1    595460828                       # number of ReadReq miss cycles
+system.cpu1.l1c.ReadReq_miss_latency::total    595460828                       # number of ReadReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::cpu1    649149772                       # number of WriteReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::total    649149772                       # number of WriteReq miss cycles
+system.cpu1.l1c.demand_miss_latency::cpu1   1244610600                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.demand_miss_latency::total   1244610600                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.overall_miss_latency::cpu1   1244610600                       # number of overall miss cycles
+system.cpu1.l1c.overall_miss_latency::total   1244610600                       # number of overall miss cycles
+system.cpu1.l1c.ReadReq_accesses::cpu1          45075                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_accesses::total         45075                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::cpu1         24938                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::total        24938                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.demand_accesses::cpu1           70013                       # number of demand (read+write) accesses
+system.cpu1.l1c.demand_accesses::total          70013                       # number of demand (read+write) accesses
+system.cpu1.l1c.overall_accesses::cpu1          70013                       # number of overall (read+write) accesses
+system.cpu1.l1c.overall_accesses::total         70013                       # number of overall (read+write) accesses
+system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.809251                       # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_miss_rate::total     0.809251                       # miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.953404                       # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::total     0.953404                       # miss rate for WriteReq accesses
+system.cpu1.l1c.demand_miss_rate::cpu1       0.860597                       # miss rate for demand accesses
+system.cpu1.l1c.demand_miss_rate::total      0.860597                       # miss rate for demand accesses
+system.cpu1.l1c.overall_miss_rate::cpu1      0.860597                       # miss rate for overall accesses
+system.cpu1.l1c.overall_miss_rate::total     0.860597                       # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16324.281821                       # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 16324.281821                       # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 27302.732672                       # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::total 27302.732672                       # average WriteReq miss latency
+system.cpu1.l1c.demand_avg_miss_latency::cpu1 20656.408810                       # average overall miss latency
+system.cpu1.l1c.demand_avg_miss_latency::total 20656.408810                       # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 20656.408810                       # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 20656.408810                       # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs       769857                       # number of cycles access was blocked
 system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs               66458                       # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs               65915                       # number of cycles access was blocked
 system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs    11.689443                       # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs    11.679542                       # average number of cycles each access was blocked
 system.cpu1.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks           9776                       # number of writebacks
-system.cpu1.l1c.writebacks::total                9776                       # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36464                       # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total        36464                       # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1        24184                       # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total        24184                       # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1        60648                       # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total        60648                       # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1        60648                       # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total        60648                       # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    534984781                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total    534984781                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    623377675                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total    623377675                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1158362456                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total   1158362456                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1158362456                       # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total   1158362456                       # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    640712682                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    640712682                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1    989782156                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total    989782156                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   1630494838                       # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total   1630494838                       # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.807905                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.807905                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.954795                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.954795                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.860707                       # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_miss_rate::total     0.860707                       # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.860707                       # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total     0.860707                       # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 14671.587895                       # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 14671.587895                       # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 25776.450339                       # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 25776.450339                       # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19099.763488                       # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19099.763488                       # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19099.763488                       # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19099.763488                       # average overall mshr miss latency
+system.cpu1.l1c.writebacks::writebacks           9826                       # number of writebacks
+system.cpu1.l1c.writebacks::total                9826                       # number of writebacks
+system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36477                       # number of ReadReq MSHR misses
+system.cpu1.l1c.ReadReq_mshr_misses::total        36477                       # number of ReadReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23776                       # number of WriteReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::total        23776                       # number of WriteReq MSHR misses
+system.cpu1.l1c.demand_mshr_misses::cpu1        60253                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.demand_mshr_misses::total        60253                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.overall_mshr_misses::cpu1        60253                       # number of overall MSHR misses
+system.cpu1.l1c.overall_mshr_misses::total        60253                       # number of overall MSHR misses
+system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    538442174                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_miss_latency::total    538442174                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    612498892                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::total    612498892                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1150941066                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::total   1150941066                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1150941066                       # number of overall MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::total   1150941066                       # number of overall MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    637533564                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    637533564                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1    980538192                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total    980538192                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   1618071756                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::total   1618071756                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.809251                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.809251                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.953404                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.953404                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.860597                       # mshr miss rate for demand accesses
+system.cpu1.l1c.demand_mshr_miss_rate::total     0.860597                       # mshr miss rate for demand accesses
+system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.860597                       # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_miss_rate::total     0.860597                       # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 14761.141925                       # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 14761.141925                       # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 25761.225269                       # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 25761.225269                       # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19101.805155                       # average overall mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19101.805155                       # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19101.805155                       # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19101.805155                       # average overall mshr miss latency
 system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average WriteReq mshr uncacheable latency
@@ -317,119 +317,119 @@
 system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1          inf                       # average overall mshr uncacheable latency
 system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu2.num_reads                           99606                       # number of read accesses completed
-system.cpu2.num_writes                          55482                       # number of write accesses completed
-system.cpu2.l1c.tags.replacements               22450                       # number of replacements
-system.cpu2.l1c.tags.tagsinuse             391.646892                       # Cycle average of tags in use
-system.cpu2.l1c.tags.total_refs                 13596                       # Total number of references to valid blocks.
-system.cpu2.l1c.tags.sampled_refs               22843                       # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs                0.595193                       # Average number of references to valid blocks.
+system.cpu2.num_reads                           99661                       # number of read accesses completed
+system.cpu2.num_writes                          54617                       # number of write accesses completed
+system.cpu2.l1c.tags.replacements               22463                       # number of replacements
+system.cpu2.l1c.tags.tagsinuse             392.489979                       # Cycle average of tags in use
+system.cpu2.l1c.tags.total_refs                 13594                       # Total number of references to valid blocks.
+system.cpu2.l1c.tags.sampled_refs               22875                       # Sample count of references to valid blocks.
+system.cpu2.l1c.tags.avg_refs                0.594273                       # Average number of references to valid blocks.
 system.cpu2.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.tags.occ_blocks::cpu2      391.646892                       # Average occupied blocks per requestor
-system.cpu2.l1c.tags.occ_percent::cpu2       0.764935                       # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_percent::total      0.764935                       # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_task_id_blocks::1024          393                       # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::0          384                       # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::1            9                       # Occupied blocks per task id
-system.cpu2.l1c.tags.occ_task_id_percent::1024     0.767578                       # Percentage of cache occupancy per task id
-system.cpu2.l1c.tags.tag_accesses              338700                       # Number of tag accesses
-system.cpu2.l1c.tags.data_accesses             338700                       # Number of data accesses
-system.cpu2.l1c.ReadReq_hits::cpu2               8761                       # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total              8761                       # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2              1179                       # number of WriteReq hits
-system.cpu2.l1c.WriteReq_hits::total             1179                       # number of WriteReq hits
-system.cpu2.l1c.demand_hits::cpu2                9940                       # number of demand (read+write) hits
-system.cpu2.l1c.demand_hits::total               9940                       # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits::cpu2               9940                       # number of overall hits
-system.cpu2.l1c.overall_hits::total              9940                       # number of overall hits
-system.cpu2.l1c.ReadReq_misses::cpu2            36421                       # number of ReadReq misses
-system.cpu2.l1c.ReadReq_misses::total           36421                       # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses::cpu2           24109                       # number of WriteReq misses
-system.cpu2.l1c.WriteReq_misses::total          24109                       # number of WriteReq misses
-system.cpu2.l1c.demand_misses::cpu2             60530                       # number of demand (read+write) misses
-system.cpu2.l1c.demand_misses::total            60530                       # number of demand (read+write) misses
-system.cpu2.l1c.overall_misses::cpu2            60530                       # number of overall misses
-system.cpu2.l1c.overall_misses::total           60530                       # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency::cpu2    592390101                       # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_latency::total    592390101                       # number of ReadReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::cpu2    664239589                       # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::total    664239589                       # number of WriteReq miss cycles
-system.cpu2.l1c.demand_miss_latency::cpu2   1256629690                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_latency::total   1256629690                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.overall_miss_latency::cpu2   1256629690                       # number of overall miss cycles
-system.cpu2.l1c.overall_miss_latency::total   1256629690                       # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2          45182                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_accesses::total         45182                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::cpu2         25288                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::total        25288                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.demand_accesses::cpu2           70470                       # number of demand (read+write) accesses
-system.cpu2.l1c.demand_accesses::total          70470                       # number of demand (read+write) accesses
-system.cpu2.l1c.overall_accesses::cpu2          70470                       # number of overall (read+write) accesses
-system.cpu2.l1c.overall_accesses::total         70470                       # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.806095                       # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_miss_rate::total     0.806095                       # miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.953377                       # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::total     0.953377                       # miss rate for WriteReq accesses
-system.cpu2.l1c.demand_miss_rate::cpu2       0.858947                       # miss rate for demand accesses
-system.cpu2.l1c.demand_miss_rate::total      0.858947                       # miss rate for demand accesses
-system.cpu2.l1c.overall_miss_rate::cpu2      0.858947                       # miss rate for overall accesses
-system.cpu2.l1c.overall_miss_rate::total     0.858947                       # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16265.069630                       # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 16265.069630                       # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27551.519723                       # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 27551.519723                       # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency::cpu2 20760.444243                       # average overall miss latency
-system.cpu2.l1c.demand_avg_miss_latency::total 20760.444243                       # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 20760.444243                       # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 20760.444243                       # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs       773028                       # number of cycles access was blocked
+system.cpu2.l1c.tags.occ_blocks::cpu2      392.489979                       # Average occupied blocks per requestor
+system.cpu2.l1c.tags.occ_percent::cpu2       0.766582                       # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_percent::total      0.766582                       # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_task_id_blocks::1024          412                       # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::0          402                       # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
+system.cpu2.l1c.tags.occ_task_id_percent::1024     0.804688                       # Percentage of cache occupancy per task id
+system.cpu2.l1c.tags.tag_accesses              338191                       # Number of tag accesses
+system.cpu2.l1c.tags.data_accesses             338191                       # Number of data accesses
+system.cpu2.l1c.ReadReq_hits::cpu2               8852                       # number of ReadReq hits
+system.cpu2.l1c.ReadReq_hits::total              8852                       # number of ReadReq hits
+system.cpu2.l1c.WriteReq_hits::cpu2              1132                       # number of WriteReq hits
+system.cpu2.l1c.WriteReq_hits::total             1132                       # number of WriteReq hits
+system.cpu2.l1c.demand_hits::cpu2                9984                       # number of demand (read+write) hits
+system.cpu2.l1c.demand_hits::total               9984                       # number of demand (read+write) hits
+system.cpu2.l1c.overall_hits::cpu2               9984                       # number of overall hits
+system.cpu2.l1c.overall_hits::total              9984                       # number of overall hits
+system.cpu2.l1c.ReadReq_misses::cpu2            36597                       # number of ReadReq misses
+system.cpu2.l1c.ReadReq_misses::total           36597                       # number of ReadReq misses
+system.cpu2.l1c.WriteReq_misses::cpu2           23791                       # number of WriteReq misses
+system.cpu2.l1c.WriteReq_misses::total          23791                       # number of WriteReq misses
+system.cpu2.l1c.demand_misses::cpu2             60388                       # number of demand (read+write) misses
+system.cpu2.l1c.demand_misses::total            60388                       # number of demand (read+write) misses
+system.cpu2.l1c.overall_misses::cpu2            60388                       # number of overall misses
+system.cpu2.l1c.overall_misses::total           60388                       # number of overall misses
+system.cpu2.l1c.ReadReq_miss_latency::cpu2    596108462                       # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_latency::total    596108462                       # number of ReadReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::cpu2    646461820                       # number of WriteReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::total    646461820                       # number of WriteReq miss cycles
+system.cpu2.l1c.demand_miss_latency::cpu2   1242570282                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.demand_miss_latency::total   1242570282                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.overall_miss_latency::cpu2   1242570282                       # number of overall miss cycles
+system.cpu2.l1c.overall_miss_latency::total   1242570282                       # number of overall miss cycles
+system.cpu2.l1c.ReadReq_accesses::cpu2          45449                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_accesses::total         45449                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::cpu2         24923                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::total        24923                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.demand_accesses::cpu2           70372                       # number of demand (read+write) accesses
+system.cpu2.l1c.demand_accesses::total          70372                       # number of demand (read+write) accesses
+system.cpu2.l1c.overall_accesses::cpu2          70372                       # number of overall (read+write) accesses
+system.cpu2.l1c.overall_accesses::total         70372                       # number of overall (read+write) accesses
+system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.805232                       # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_miss_rate::total     0.805232                       # miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.954580                       # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::total     0.954580                       # miss rate for WriteReq accesses
+system.cpu2.l1c.demand_miss_rate::cpu2       0.858125                       # miss rate for demand accesses
+system.cpu2.l1c.demand_miss_rate::total      0.858125                       # miss rate for demand accesses
+system.cpu2.l1c.overall_miss_rate::cpu2      0.858125                       # miss rate for overall accesses
+system.cpu2.l1c.overall_miss_rate::total     0.858125                       # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16288.451567                       # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_miss_latency::total 16288.451567                       # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27172.536674                       # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::total 27172.536674                       # average WriteReq miss latency
+system.cpu2.l1c.demand_avg_miss_latency::cpu2 20576.443697                       # average overall miss latency
+system.cpu2.l1c.demand_avg_miss_latency::total 20576.443697                       # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::cpu2 20576.443697                       # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::total 20576.443697                       # average overall miss latency
+system.cpu2.l1c.blocked_cycles::no_mshrs       768951                       # number of cycles access was blocked
 system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs               66120                       # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_mshrs               65985                       # number of cycles access was blocked
 system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs    11.691289                       # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs    11.653421                       # average number of cycles each access was blocked
 system.cpu2.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks           9975                       # number of writebacks
-system.cpu2.l1c.writebacks::total                9975                       # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36421                       # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total        36421                       # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2        24109                       # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total        24109                       # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses::cpu2        60530                       # number of demand (read+write) MSHR misses
-system.cpu2.l1c.demand_mshr_misses::total        60530                       # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2        60530                       # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total        60530                       # number of overall MSHR misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    535479769                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_latency::total    535479769                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    627082203                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total    627082203                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1162561972                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::total   1162561972                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1162561972                       # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total   1162561972                       # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    634925616                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    634925616                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2    991782664                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total    991782664                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   1626708280                       # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total   1626708280                       # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.806095                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.806095                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.953377                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.953377                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.858947                       # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_miss_rate::total     0.858947                       # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.858947                       # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total     0.858947                       # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 14702.500453                       # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 14702.500453                       # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 26010.295035                       # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 26010.295035                       # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19206.376541                       # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19206.376541                       # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19206.376541                       # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19206.376541                       # average overall mshr miss latency
+system.cpu2.l1c.writebacks::writebacks           9852                       # number of writebacks
+system.cpu2.l1c.writebacks::total                9852                       # number of writebacks
+system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36597                       # number of ReadReq MSHR misses
+system.cpu2.l1c.ReadReq_mshr_misses::total        36597                       # number of ReadReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::cpu2        23791                       # number of WriteReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::total        23791                       # number of WriteReq MSHR misses
+system.cpu2.l1c.demand_mshr_misses::cpu2        60388                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.demand_mshr_misses::total        60388                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.overall_mshr_misses::cpu2        60388                       # number of overall MSHR misses
+system.cpu2.l1c.overall_mshr_misses::total        60388                       # number of overall MSHR misses
+system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    538960044                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_miss_latency::total    538960044                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    609774472                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::total    609774472                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1148734516                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::total   1148734516                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1148734516                       # number of overall MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::total   1148734516                       # number of overall MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    638400628                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    638400628                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2    959722740                       # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total    959722740                       # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   1598123368                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::total   1598123368                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.805232                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.805232                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.954580                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.954580                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.858125                       # mshr miss rate for demand accesses
+system.cpu2.l1c.demand_mshr_miss_rate::total     0.858125                       # mshr miss rate for demand accesses
+system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.858125                       # mshr miss rate for overall accesses
+system.cpu2.l1c.overall_mshr_miss_rate::total     0.858125                       # mshr miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 14726.891385                       # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 14726.891385                       # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 25630.468328                       # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 25630.468328                       # average WriteReq mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19022.562695                       # average overall mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19022.562695                       # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19022.562695                       # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19022.562695                       # average overall mshr miss latency
 system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
 system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average WriteReq mshr uncacheable latency
@@ -437,119 +437,119 @@
 system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2          inf                       # average overall mshr uncacheable latency
 system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu3.num_reads                           99549                       # number of read accesses completed
-system.cpu3.num_writes                          55104                       # number of write accesses completed
-system.cpu3.l1c.tags.replacements               22310                       # number of replacements
-system.cpu3.l1c.tags.tagsinuse             391.032656                       # Cycle average of tags in use
-system.cpu3.l1c.tags.total_refs                 13513                       # Total number of references to valid blocks.
-system.cpu3.l1c.tags.sampled_refs               22709                       # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs                0.595050                       # Average number of references to valid blocks.
+system.cpu3.num_reads                          100000                       # number of read accesses completed
+system.cpu3.num_writes                          55095                       # number of write accesses completed
+system.cpu3.l1c.tags.replacements               22209                       # number of replacements
+system.cpu3.l1c.tags.tagsinuse             391.627346                       # Cycle average of tags in use
+system.cpu3.l1c.tags.total_refs                 13529                       # Total number of references to valid blocks.
+system.cpu3.l1c.tags.sampled_refs               22601                       # Sample count of references to valid blocks.
+system.cpu3.l1c.tags.avg_refs                0.598602                       # Average number of references to valid blocks.
 system.cpu3.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.tags.occ_blocks::cpu3      391.032656                       # Average occupied blocks per requestor
-system.cpu3.l1c.tags.occ_percent::cpu3       0.763736                       # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_percent::total      0.763736                       # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_task_id_blocks::1024          399                       # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::0          393                       # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
-system.cpu3.l1c.tags.occ_task_id_percent::1024     0.779297                       # Percentage of cache occupancy per task id
-system.cpu3.l1c.tags.tag_accesses              338332                       # Number of tag accesses
-system.cpu3.l1c.tags.data_accesses             338332                       # Number of data accesses
-system.cpu3.l1c.ReadReq_hits::cpu3               8654                       # number of ReadReq hits
-system.cpu3.l1c.ReadReq_hits::total              8654                       # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits::cpu3              1182                       # number of WriteReq hits
-system.cpu3.l1c.WriteReq_hits::total             1182                       # number of WriteReq hits
-system.cpu3.l1c.demand_hits::cpu3                9836                       # number of demand (read+write) hits
-system.cpu3.l1c.demand_hits::total               9836                       # number of demand (read+write) hits
-system.cpu3.l1c.overall_hits::cpu3               9836                       # number of overall hits
-system.cpu3.l1c.overall_hits::total              9836                       # number of overall hits
-system.cpu3.l1c.ReadReq_misses::cpu3            36530                       # number of ReadReq misses
-system.cpu3.l1c.ReadReq_misses::total           36530                       # number of ReadReq misses
-system.cpu3.l1c.WriteReq_misses::cpu3           24013                       # number of WriteReq misses
-system.cpu3.l1c.WriteReq_misses::total          24013                       # number of WriteReq misses
-system.cpu3.l1c.demand_misses::cpu3             60543                       # number of demand (read+write) misses
-system.cpu3.l1c.demand_misses::total            60543                       # number of demand (read+write) misses
-system.cpu3.l1c.overall_misses::cpu3            60543                       # number of overall misses
-system.cpu3.l1c.overall_misses::total           60543                       # number of overall misses
-system.cpu3.l1c.ReadReq_miss_latency::cpu3    590001438                       # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_latency::total    590001438                       # number of ReadReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::cpu3    660132360                       # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::total    660132360                       # number of WriteReq miss cycles
-system.cpu3.l1c.demand_miss_latency::cpu3   1250133798                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_latency::total   1250133798                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.overall_miss_latency::cpu3   1250133798                       # number of overall miss cycles
-system.cpu3.l1c.overall_miss_latency::total   1250133798                       # number of overall miss cycles
-system.cpu3.l1c.ReadReq_accesses::cpu3          45184                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_accesses::total         45184                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::cpu3         25195                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::total        25195                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.demand_accesses::cpu3           70379                       # number of demand (read+write) accesses
-system.cpu3.l1c.demand_accesses::total          70379                       # number of demand (read+write) accesses
-system.cpu3.l1c.overall_accesses::cpu3          70379                       # number of overall (read+write) accesses
-system.cpu3.l1c.overall_accesses::total         70379                       # number of overall (read+write) accesses
-system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.808472                       # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_miss_rate::total     0.808472                       # miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.953086                       # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::total     0.953086                       # miss rate for WriteReq accesses
-system.cpu3.l1c.demand_miss_rate::cpu3       0.860242                       # miss rate for demand accesses
-system.cpu3.l1c.demand_miss_rate::total      0.860242                       # miss rate for demand accesses
-system.cpu3.l1c.overall_miss_rate::cpu3      0.860242                       # miss rate for overall accesses
-system.cpu3.l1c.overall_miss_rate::total     0.860242                       # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16151.148043                       # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_miss_latency::total 16151.148043                       # average ReadReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 27490.624245                       # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::total 27490.624245                       # average WriteReq miss latency
-system.cpu3.l1c.demand_avg_miss_latency::cpu3 20648.692632                       # average overall miss latency
-system.cpu3.l1c.demand_avg_miss_latency::total 20648.692632                       # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 20648.692632                       # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 20648.692632                       # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs       774871                       # number of cycles access was blocked
+system.cpu3.l1c.tags.occ_blocks::cpu3      391.627346                       # Average occupied blocks per requestor
+system.cpu3.l1c.tags.occ_percent::cpu3       0.764897                       # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_percent::total      0.764897                       # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_task_id_blocks::1024          392                       # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::0          378                       # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
+system.cpu3.l1c.tags.occ_task_id_percent::1024     0.765625                       # Percentage of cache occupancy per task id
+system.cpu3.l1c.tags.tag_accesses              338542                       # Number of tag accesses
+system.cpu3.l1c.tags.data_accesses             338542                       # Number of data accesses
+system.cpu3.l1c.ReadReq_hits::cpu3               8783                       # number of ReadReq hits
+system.cpu3.l1c.ReadReq_hits::total              8783                       # number of ReadReq hits
+system.cpu3.l1c.WriteReq_hits::cpu3              1149                       # number of WriteReq hits
+system.cpu3.l1c.WriteReq_hits::total             1149                       # number of WriteReq hits
+system.cpu3.l1c.demand_hits::cpu3                9932                       # number of demand (read+write) hits
+system.cpu3.l1c.demand_hits::total               9932                       # number of demand (read+write) hits
+system.cpu3.l1c.overall_hits::cpu3               9932                       # number of overall hits
+system.cpu3.l1c.overall_hits::total              9932                       # number of overall hits
+system.cpu3.l1c.ReadReq_misses::cpu3            36678                       # number of ReadReq misses
+system.cpu3.l1c.ReadReq_misses::total           36678                       # number of ReadReq misses
+system.cpu3.l1c.WriteReq_misses::cpu3           23815                       # number of WriteReq misses
+system.cpu3.l1c.WriteReq_misses::total          23815                       # number of WriteReq misses
+system.cpu3.l1c.demand_misses::cpu3             60493                       # number of demand (read+write) misses
+system.cpu3.l1c.demand_misses::total            60493                       # number of demand (read+write) misses
+system.cpu3.l1c.overall_misses::cpu3            60493                       # number of overall misses
+system.cpu3.l1c.overall_misses::total           60493                       # number of overall misses
+system.cpu3.l1c.ReadReq_miss_latency::cpu3    595385248                       # number of ReadReq miss cycles
+system.cpu3.l1c.ReadReq_miss_latency::total    595385248                       # number of ReadReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::cpu3    651992109                       # number of WriteReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::total    651992109                       # number of WriteReq miss cycles
+system.cpu3.l1c.demand_miss_latency::cpu3   1247377357                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.demand_miss_latency::total   1247377357                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.overall_miss_latency::cpu3   1247377357                       # number of overall miss cycles
+system.cpu3.l1c.overall_miss_latency::total   1247377357                       # number of overall miss cycles
+system.cpu3.l1c.ReadReq_accesses::cpu3          45461                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_accesses::total         45461                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::cpu3         24964                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::total        24964                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.demand_accesses::cpu3           70425                       # number of demand (read+write) accesses
+system.cpu3.l1c.demand_accesses::total          70425                       # number of demand (read+write) accesses
+system.cpu3.l1c.overall_accesses::cpu3          70425                       # number of overall (read+write) accesses
+system.cpu3.l1c.overall_accesses::total         70425                       # number of overall (read+write) accesses
+system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.806801                       # miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_miss_rate::total     0.806801                       # miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.953974                       # miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::total     0.953974                       # miss rate for WriteReq accesses
+system.cpu3.l1c.demand_miss_rate::cpu3       0.858971                       # miss rate for demand accesses
+system.cpu3.l1c.demand_miss_rate::total      0.858971                       # miss rate for demand accesses
+system.cpu3.l1c.overall_miss_rate::cpu3      0.858971                       # miss rate for overall accesses
+system.cpu3.l1c.overall_miss_rate::total     0.858971                       # miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16232.762092                       # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_miss_latency::total 16232.762092                       # average ReadReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 27377.371782                       # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::total 27377.371782                       # average WriteReq miss latency
+system.cpu3.l1c.demand_avg_miss_latency::cpu3 20620.193361                       # average overall miss latency
+system.cpu3.l1c.demand_avg_miss_latency::total 20620.193361                       # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::cpu3 20620.193361                       # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::total 20620.193361                       # average overall miss latency
+system.cpu3.l1c.blocked_cycles::no_mshrs       774947                       # number of cycles access was blocked
 system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs               66332                       # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_mshrs               66468                       # number of cycles access was blocked
 system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs    11.681707                       # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_mshrs    11.658949                       # average number of cycles each access was blocked
 system.cpu3.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu3.l1c.writebacks::writebacks           9907                       # number of writebacks
-system.cpu3.l1c.writebacks::total                9907                       # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36530                       # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_misses::total        36530                       # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::cpu3        24013                       # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::total        24013                       # number of WriteReq MSHR misses
-system.cpu3.l1c.demand_mshr_misses::cpu3        60543                       # number of demand (read+write) MSHR misses
-system.cpu3.l1c.demand_mshr_misses::total        60543                       # number of demand (read+write) MSHR misses
-system.cpu3.l1c.overall_mshr_misses::cpu3        60543                       # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_misses::total        60543                       # number of overall MSHR misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    532881722                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_latency::total    532881722                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    623079094                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total    623079094                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1155960816                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::total   1155960816                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1155960816                       # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total   1155960816                       # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    642783574                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    642783574                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3    972713175                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total    972713175                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   1615496749                       # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::total   1615496749                       # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.808472                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.808472                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.953086                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.953086                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.860242                       # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_miss_rate::total     0.860242                       # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.860242                       # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total     0.860242                       # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 14587.509499                       # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 14587.509499                       # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 25947.573981                       # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 25947.573981                       # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19093.219959                       # average overall mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19093.219959                       # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19093.219959                       # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19093.219959                       # average overall mshr miss latency
+system.cpu3.l1c.writebacks::writebacks           9869                       # number of writebacks
+system.cpu3.l1c.writebacks::total                9869                       # number of writebacks
+system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36678                       # number of ReadReq MSHR misses
+system.cpu3.l1c.ReadReq_mshr_misses::total        36678                       # number of ReadReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23815                       # number of WriteReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::total        23815                       # number of WriteReq MSHR misses
+system.cpu3.l1c.demand_mshr_misses::cpu3        60493                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.demand_mshr_misses::total        60493                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.overall_mshr_misses::cpu3        60493                       # number of overall MSHR misses
+system.cpu3.l1c.overall_mshr_misses::total        60493                       # number of overall MSHR misses
+system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    538014612                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_miss_latency::total    538014612                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    615289695                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::total    615289695                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1153304307                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::total   1153304307                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1153304307                       # number of overall MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::total   1153304307                       # number of overall MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    640462998                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    640462998                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3    962755753                       # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total    962755753                       # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   1603218751                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::total   1603218751                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.806801                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.806801                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.953974                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.953974                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.858971                       # mshr miss rate for demand accesses
+system.cpu3.l1c.demand_mshr_miss_rate::total     0.858971                       # mshr miss rate for demand accesses
+system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.858971                       # mshr miss rate for overall accesses
+system.cpu3.l1c.overall_mshr_miss_rate::total     0.858971                       # mshr miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 14668.591853                       # average ReadReq mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 14668.591853                       # average ReadReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 25836.224858                       # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 25836.224858                       # average WriteReq mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19065.086985                       # average overall mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19065.086985                       # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19065.086985                       # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19065.086985                       # average overall mshr miss latency
 system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average ReadReq mshr uncacheable latency
 system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average WriteReq mshr uncacheable latency
@@ -557,119 +557,119 @@
 system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3          inf                       # average overall mshr uncacheable latency
 system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu4.num_reads                           99755                       # number of read accesses completed
-system.cpu4.num_writes                          55257                       # number of write accesses completed
-system.cpu4.l1c.tags.replacements               22302                       # number of replacements
-system.cpu4.l1c.tags.tagsinuse             391.084224                       # Cycle average of tags in use
-system.cpu4.l1c.tags.total_refs                 13540                       # Total number of references to valid blocks.
-system.cpu4.l1c.tags.sampled_refs               22693                       # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs                0.596660                       # Average number of references to valid blocks.
+system.cpu4.num_reads                           99958                       # number of read accesses completed
+system.cpu4.num_writes                          55186                       # number of write accesses completed
+system.cpu4.l1c.tags.replacements               22162                       # number of replacements
+system.cpu4.l1c.tags.tagsinuse             390.917230                       # Cycle average of tags in use
+system.cpu4.l1c.tags.total_refs                 13739                       # Total number of references to valid blocks.
+system.cpu4.l1c.tags.sampled_refs               22564                       # Sample count of references to valid blocks.
+system.cpu4.l1c.tags.avg_refs                0.608890                       # Average number of references to valid blocks.
 system.cpu4.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.tags.occ_blocks::cpu4      391.084224                       # Average occupied blocks per requestor
-system.cpu4.l1c.tags.occ_percent::cpu4       0.763836                       # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_percent::total      0.763836                       # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_task_id_blocks::1024          391                       # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::0          382                       # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::1            9                       # Occupied blocks per task id
-system.cpu4.l1c.tags.occ_task_id_percent::1024     0.763672                       # Percentage of cache occupancy per task id
-system.cpu4.l1c.tags.tag_accesses              338305                       # Number of tag accesses
-system.cpu4.l1c.tags.data_accesses             338305                       # Number of data accesses
-system.cpu4.l1c.ReadReq_hits::cpu4               8852                       # number of ReadReq hits
-system.cpu4.l1c.ReadReq_hits::total              8852                       # number of ReadReq hits
-system.cpu4.l1c.WriteReq_hits::cpu4              1084                       # number of WriteReq hits
-system.cpu4.l1c.WriteReq_hits::total             1084                       # number of WriteReq hits
-system.cpu4.l1c.demand_hits::cpu4                9936                       # number of demand (read+write) hits
-system.cpu4.l1c.demand_hits::total               9936                       # number of demand (read+write) hits
-system.cpu4.l1c.overall_hits::cpu4               9936                       # number of overall hits
-system.cpu4.l1c.overall_hits::total              9936                       # number of overall hits
-system.cpu4.l1c.ReadReq_misses::cpu4            36600                       # number of ReadReq misses
-system.cpu4.l1c.ReadReq_misses::total           36600                       # number of ReadReq misses
-system.cpu4.l1c.WriteReq_misses::cpu4           23847                       # number of WriteReq misses
-system.cpu4.l1c.WriteReq_misses::total          23847                       # number of WriteReq misses
-system.cpu4.l1c.demand_misses::cpu4             60447                       # number of demand (read+write) misses
-system.cpu4.l1c.demand_misses::total            60447                       # number of demand (read+write) misses
-system.cpu4.l1c.overall_misses::cpu4            60447                       # number of overall misses
-system.cpu4.l1c.overall_misses::total           60447                       # number of overall misses
-system.cpu4.l1c.ReadReq_miss_latency::cpu4    590829220                       # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_latency::total    590829220                       # number of ReadReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::cpu4    656323200                       # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::total    656323200                       # number of WriteReq miss cycles
-system.cpu4.l1c.demand_miss_latency::cpu4   1247152420                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_latency::total   1247152420                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.overall_miss_latency::cpu4   1247152420                       # number of overall miss cycles
-system.cpu4.l1c.overall_miss_latency::total   1247152420                       # number of overall miss cycles
-system.cpu4.l1c.ReadReq_accesses::cpu4          45452                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_accesses::total         45452                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::cpu4         24931                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::total        24931                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.demand_accesses::cpu4           70383                       # number of demand (read+write) accesses
-system.cpu4.l1c.demand_accesses::total          70383                       # number of demand (read+write) accesses
-system.cpu4.l1c.overall_accesses::cpu4          70383                       # number of overall (read+write) accesses
-system.cpu4.l1c.overall_accesses::total         70383                       # number of overall (read+write) accesses
-system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.805245                       # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_miss_rate::total     0.805245                       # miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.956520                       # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::total     0.956520                       # miss rate for WriteReq accesses
-system.cpu4.l1c.demand_miss_rate::cpu4       0.858830                       # miss rate for demand accesses
-system.cpu4.l1c.demand_miss_rate::total      0.858830                       # miss rate for demand accesses
-system.cpu4.l1c.overall_miss_rate::cpu4      0.858830                       # miss rate for overall accesses
-system.cpu4.l1c.overall_miss_rate::total     0.858830                       # miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16142.874863                       # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_miss_latency::total 16142.874863                       # average ReadReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 27522.254372                       # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::total 27522.254372                       # average WriteReq miss latency
-system.cpu4.l1c.demand_avg_miss_latency::cpu4 20632.164045                       # average overall miss latency
-system.cpu4.l1c.demand_avg_miss_latency::total 20632.164045                       # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::cpu4 20632.164045                       # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::total 20632.164045                       # average overall miss latency
-system.cpu4.l1c.blocked_cycles::no_mshrs       780817                       # number of cycles access was blocked
+system.cpu4.l1c.tags.occ_blocks::cpu4      390.917230                       # Average occupied blocks per requestor
+system.cpu4.l1c.tags.occ_percent::cpu4       0.763510                       # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_percent::total      0.763510                       # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::0          392                       # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
+system.cpu4.l1c.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
+system.cpu4.l1c.tags.tag_accesses              338274                       # Number of tag accesses
+system.cpu4.l1c.tags.data_accesses             338274                       # Number of data accesses
+system.cpu4.l1c.ReadReq_hits::cpu4               8951                       # number of ReadReq hits
+system.cpu4.l1c.ReadReq_hits::total              8951                       # number of ReadReq hits
+system.cpu4.l1c.WriteReq_hits::cpu4              1108                       # number of WriteReq hits
+system.cpu4.l1c.WriteReq_hits::total             1108                       # number of WriteReq hits
+system.cpu4.l1c.demand_hits::cpu4               10059                       # number of demand (read+write) hits
+system.cpu4.l1c.demand_hits::total              10059                       # number of demand (read+write) hits
+system.cpu4.l1c.overall_hits::cpu4              10059                       # number of overall hits
+system.cpu4.l1c.overall_hits::total             10059                       # number of overall hits
+system.cpu4.l1c.ReadReq_misses::cpu4            36463                       # number of ReadReq misses
+system.cpu4.l1c.ReadReq_misses::total           36463                       # number of ReadReq misses
+system.cpu4.l1c.WriteReq_misses::cpu4           23892                       # number of WriteReq misses
+system.cpu4.l1c.WriteReq_misses::total          23892                       # number of WriteReq misses
+system.cpu4.l1c.demand_misses::cpu4             60355                       # number of demand (read+write) misses
+system.cpu4.l1c.demand_misses::total            60355                       # number of demand (read+write) misses
+system.cpu4.l1c.overall_misses::cpu4            60355                       # number of overall misses
+system.cpu4.l1c.overall_misses::total           60355                       # number of overall misses
+system.cpu4.l1c.ReadReq_miss_latency::cpu4    590532010                       # number of ReadReq miss cycles
+system.cpu4.l1c.ReadReq_miss_latency::total    590532010                       # number of ReadReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::cpu4    657391664                       # number of WriteReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::total    657391664                       # number of WriteReq miss cycles
+system.cpu4.l1c.demand_miss_latency::cpu4   1247923674                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.demand_miss_latency::total   1247923674                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.overall_miss_latency::cpu4   1247923674                       # number of overall miss cycles
+system.cpu4.l1c.overall_miss_latency::total   1247923674                       # number of overall miss cycles
+system.cpu4.l1c.ReadReq_accesses::cpu4          45414                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.ReadReq_accesses::total         45414                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::cpu4         25000                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::total        25000                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.demand_accesses::cpu4           70414                       # number of demand (read+write) accesses
+system.cpu4.l1c.demand_accesses::total          70414                       # number of demand (read+write) accesses
+system.cpu4.l1c.overall_accesses::cpu4          70414                       # number of overall (read+write) accesses
+system.cpu4.l1c.overall_accesses::total         70414                       # number of overall (read+write) accesses
+system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.802902                       # miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_miss_rate::total     0.802902                       # miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.955680                       # miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::total     0.955680                       # miss rate for WriteReq accesses
+system.cpu4.l1c.demand_miss_rate::cpu4       0.857145                       # miss rate for demand accesses
+system.cpu4.l1c.demand_miss_rate::total      0.857145                       # miss rate for demand accesses
+system.cpu4.l1c.overall_miss_rate::cpu4      0.857145                       # miss rate for overall accesses
+system.cpu4.l1c.overall_miss_rate::total     0.857145                       # miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16195.376409                       # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_miss_latency::total 16195.376409                       # average ReadReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 27515.137452                       # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::total 27515.137452                       # average WriteReq miss latency
+system.cpu4.l1c.demand_avg_miss_latency::cpu4 20676.392577                       # average overall miss latency
+system.cpu4.l1c.demand_avg_miss_latency::total 20676.392577                       # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::cpu4 20676.392577                       # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::total 20676.392577                       # average overall miss latency
+system.cpu4.l1c.blocked_cycles::no_mshrs       772044                       # number of cycles access was blocked
 system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs               66569                       # number of cycles access was blocked
+system.cpu4.l1c.blocked::no_mshrs               66046                       # number of cycles access was blocked
 system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_mshrs    11.729439                       # average number of cycles each access was blocked
+system.cpu4.l1c.avg_blocked_cycles::no_mshrs    11.689489                       # average number of cycles each access was blocked
 system.cpu4.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu4.l1c.writebacks::writebacks           9856                       # number of writebacks
-system.cpu4.l1c.writebacks::total                9856                       # number of writebacks
-system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36600                       # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_misses::total        36600                       # number of ReadReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::cpu4        23847                       # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::total        23847                       # number of WriteReq MSHR misses
-system.cpu4.l1c.demand_mshr_misses::cpu4        60447                       # number of demand (read+write) MSHR misses
-system.cpu4.l1c.demand_mshr_misses::total        60447                       # number of demand (read+write) MSHR misses
-system.cpu4.l1c.overall_mshr_misses::cpu4        60447                       # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_misses::total        60447                       # number of overall MSHR misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    533635904                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_latency::total    533635904                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    619552810                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::total    619552810                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1153188714                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::total   1153188714                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1153188714                       # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total   1153188714                       # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    651255905                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    651255905                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4    973411350                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total    973411350                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   1624667255                       # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::total   1624667255                       # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.805245                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.805245                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.956520                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.956520                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.858830                       # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_miss_rate::total     0.858830                       # mshr miss rate for demand accesses
-system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.858830                       # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_miss_rate::total     0.858830                       # mshr miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 14580.215956                       # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 14580.215956                       # average ReadReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 25980.324988                       # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 25980.324988                       # average WriteReq mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19077.683160                       # average overall mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19077.683160                       # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19077.683160                       # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19077.683160                       # average overall mshr miss latency
+system.cpu4.l1c.writebacks::writebacks           9680                       # number of writebacks
+system.cpu4.l1c.writebacks::total                9680                       # number of writebacks
+system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36463                       # number of ReadReq MSHR misses
+system.cpu4.l1c.ReadReq_mshr_misses::total        36463                       # number of ReadReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses::cpu4        23892                       # number of WriteReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses::total        23892                       # number of WriteReq MSHR misses
+system.cpu4.l1c.demand_mshr_misses::cpu4        60355                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.demand_mshr_misses::total        60355                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.overall_mshr_misses::cpu4        60355                       # number of overall MSHR misses
+system.cpu4.l1c.overall_mshr_misses::total        60355                       # number of overall MSHR misses
+system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    533535272                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_miss_latency::total    533535272                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    620520370                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency::total    620520370                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1154055642                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency::total   1154055642                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1154055642                       # number of overall MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::total   1154055642                       # number of overall MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    636776082                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    636776082                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4    976656146                       # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total    976656146                       # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   1613432228                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency::total   1613432228                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.802902                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.802902                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.955680                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.955680                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.857145                       # mshr miss rate for demand accesses
+system.cpu4.l1c.demand_mshr_miss_rate::total     0.857145                       # mshr miss rate for demand accesses
+system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.857145                       # mshr miss rate for overall accesses
+system.cpu4.l1c.overall_mshr_miss_rate::total     0.857145                       # mshr miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 14632.237391                       # average ReadReq mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 14632.237391                       # average ReadReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 25971.888917                       # average WriteReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 25971.888917                       # average WriteReq mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19121.127363                       # average overall mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19121.127363                       # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19121.127363                       # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19121.127363                       # average overall mshr miss latency
 system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average ReadReq mshr uncacheable latency
 system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average WriteReq mshr uncacheable latency
@@ -677,119 +677,119 @@
 system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4          inf                       # average overall mshr uncacheable latency
 system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu5.num_reads                           99495                       # number of read accesses completed
-system.cpu5.num_writes                          54912                       # number of write accesses completed
-system.cpu5.l1c.tags.replacements               22132                       # number of replacements
-system.cpu5.l1c.tags.tagsinuse             389.508075                       # Cycle average of tags in use
-system.cpu5.l1c.tags.total_refs                 13369                       # Total number of references to valid blocks.
-system.cpu5.l1c.tags.sampled_refs               22545                       # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs                0.592992                       # Average number of references to valid blocks.
+system.cpu5.num_reads                           98793                       # number of read accesses completed
+system.cpu5.num_writes                          54966                       # number of write accesses completed
+system.cpu5.l1c.tags.replacements               22337                       # number of replacements
+system.cpu5.l1c.tags.tagsinuse             392.447401                       # Cycle average of tags in use
+system.cpu5.l1c.tags.total_refs                 13310                       # Total number of references to valid blocks.
+system.cpu5.l1c.tags.sampled_refs               22755                       # Sample count of references to valid blocks.
+system.cpu5.l1c.tags.avg_refs                0.584926                       # Average number of references to valid blocks.
 system.cpu5.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.tags.occ_blocks::cpu5      389.508075                       # Average occupied blocks per requestor
-system.cpu5.l1c.tags.occ_percent::cpu5       0.760758                       # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_percent::total      0.760758                       # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_task_id_blocks::1024          413                       # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::0          409                       # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
-system.cpu5.l1c.tags.occ_task_id_percent::1024     0.806641                       # Percentage of cache occupancy per task id
-system.cpu5.l1c.tags.tag_accesses              337023                       # Number of tag accesses
-system.cpu5.l1c.tags.data_accesses             337023                       # Number of data accesses
-system.cpu5.l1c.ReadReq_hits::cpu5               8615                       # number of ReadReq hits
-system.cpu5.l1c.ReadReq_hits::total              8615                       # number of ReadReq hits
-system.cpu5.l1c.WriteReq_hits::cpu5              1193                       # number of WriteReq hits
-system.cpu5.l1c.WriteReq_hits::total             1193                       # number of WriteReq hits
-system.cpu5.l1c.demand_hits::cpu5                9808                       # number of demand (read+write) hits
-system.cpu5.l1c.demand_hits::total               9808                       # number of demand (read+write) hits
-system.cpu5.l1c.overall_hits::cpu5               9808                       # number of overall hits
-system.cpu5.l1c.overall_hits::total              9808                       # number of overall hits
-system.cpu5.l1c.ReadReq_misses::cpu5            36426                       # number of ReadReq misses
-system.cpu5.l1c.ReadReq_misses::total           36426                       # number of ReadReq misses
-system.cpu5.l1c.WriteReq_misses::cpu5           23853                       # number of WriteReq misses
-system.cpu5.l1c.WriteReq_misses::total          23853                       # number of WriteReq misses
-system.cpu5.l1c.demand_misses::cpu5             60279                       # number of demand (read+write) misses
-system.cpu5.l1c.demand_misses::total            60279                       # number of demand (read+write) misses
-system.cpu5.l1c.overall_misses::cpu5            60279                       # number of overall misses
-system.cpu5.l1c.overall_misses::total           60279                       # number of overall misses
-system.cpu5.l1c.ReadReq_miss_latency::cpu5    593740716                       # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_latency::total    593740716                       # number of ReadReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::cpu5    656837719                       # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::total    656837719                       # number of WriteReq miss cycles
-system.cpu5.l1c.demand_miss_latency::cpu5   1250578435                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.demand_miss_latency::total   1250578435                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.overall_miss_latency::cpu5   1250578435                       # number of overall miss cycles
-system.cpu5.l1c.overall_miss_latency::total   1250578435                       # number of overall miss cycles
-system.cpu5.l1c.ReadReq_accesses::cpu5          45041                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_accesses::total         45041                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::cpu5         25046                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::total        25046                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.demand_accesses::cpu5           70087                       # number of demand (read+write) accesses
-system.cpu5.l1c.demand_accesses::total          70087                       # number of demand (read+write) accesses
-system.cpu5.l1c.overall_accesses::cpu5          70087                       # number of overall (read+write) accesses
-system.cpu5.l1c.overall_accesses::total         70087                       # number of overall (read+write) accesses
-system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.808730                       # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_miss_rate::total     0.808730                       # miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.952368                       # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::total     0.952368                       # miss rate for WriteReq accesses
-system.cpu5.l1c.demand_miss_rate::cpu5       0.860060                       # miss rate for demand accesses
-system.cpu5.l1c.demand_miss_rate::total      0.860060                       # miss rate for demand accesses
-system.cpu5.l1c.overall_miss_rate::cpu5      0.860060                       # miss rate for overall accesses
-system.cpu5.l1c.overall_miss_rate::total     0.860060                       # miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16299.915335                       # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_miss_latency::total 16299.915335                       # average ReadReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27536.901815                       # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::total 27536.901815                       # average WriteReq miss latency
-system.cpu5.l1c.demand_avg_miss_latency::cpu5 20746.502679                       # average overall miss latency
-system.cpu5.l1c.demand_avg_miss_latency::total 20746.502679                       # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 20746.502679                       # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 20746.502679                       # average overall miss latency
-system.cpu5.l1c.blocked_cycles::no_mshrs       781949                       # number of cycles access was blocked
+system.cpu5.l1c.tags.occ_blocks::cpu5      392.447401                       # Average occupied blocks per requestor
+system.cpu5.l1c.tags.occ_percent::cpu5       0.766499                       # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_percent::total      0.766499                       # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_task_id_blocks::1024          418                       # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::0          408                       # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
+system.cpu5.l1c.tags.occ_task_id_percent::1024     0.816406                       # Percentage of cache occupancy per task id
+system.cpu5.l1c.tags.tag_accesses              335862                       # Number of tag accesses
+system.cpu5.l1c.tags.data_accesses             335862                       # Number of data accesses
+system.cpu5.l1c.ReadReq_hits::cpu5               8554                       # number of ReadReq hits
+system.cpu5.l1c.ReadReq_hits::total              8554                       # number of ReadReq hits
+system.cpu5.l1c.WriteReq_hits::cpu5              1127                       # number of WriteReq hits
+system.cpu5.l1c.WriteReq_hits::total             1127                       # number of WriteReq hits
+system.cpu5.l1c.demand_hits::cpu5                9681                       # number of demand (read+write) hits
+system.cpu5.l1c.demand_hits::total               9681                       # number of demand (read+write) hits
+system.cpu5.l1c.overall_hits::cpu5               9681                       # number of overall hits
+system.cpu5.l1c.overall_hits::total              9681                       # number of overall hits
+system.cpu5.l1c.ReadReq_misses::cpu5            36144                       # number of ReadReq misses
+system.cpu5.l1c.ReadReq_misses::total           36144                       # number of ReadReq misses
+system.cpu5.l1c.WriteReq_misses::cpu5           24019                       # number of WriteReq misses
+system.cpu5.l1c.WriteReq_misses::total          24019                       # number of WriteReq misses
+system.cpu5.l1c.demand_misses::cpu5             60163                       # number of demand (read+write) misses
+system.cpu5.l1c.demand_misses::total            60163                       # number of demand (read+write) misses
+system.cpu5.l1c.overall_misses::cpu5            60163                       # number of overall misses
+system.cpu5.l1c.overall_misses::total           60163                       # number of overall misses
+system.cpu5.l1c.ReadReq_miss_latency::cpu5    586243376                       # number of ReadReq miss cycles
+system.cpu5.l1c.ReadReq_miss_latency::total    586243376                       # number of ReadReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::cpu5    664085386                       # number of WriteReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::total    664085386                       # number of WriteReq miss cycles
+system.cpu5.l1c.demand_miss_latency::cpu5   1250328762                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.demand_miss_latency::total   1250328762                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.overall_miss_latency::cpu5   1250328762                       # number of overall miss cycles
+system.cpu5.l1c.overall_miss_latency::total   1250328762                       # number of overall miss cycles
+system.cpu5.l1c.ReadReq_accesses::cpu5          44698                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.ReadReq_accesses::total         44698                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::cpu5         25146                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::total        25146                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.demand_accesses::cpu5           69844                       # number of demand (read+write) accesses
+system.cpu5.l1c.demand_accesses::total          69844                       # number of demand (read+write) accesses
+system.cpu5.l1c.overall_accesses::cpu5          69844                       # number of overall (read+write) accesses
+system.cpu5.l1c.overall_accesses::total         69844                       # number of overall (read+write) accesses
+system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.808627                       # miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_miss_rate::total     0.808627                       # miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.955182                       # miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::total     0.955182                       # miss rate for WriteReq accesses
+system.cpu5.l1c.demand_miss_rate::cpu5       0.861391                       # miss rate for demand accesses
+system.cpu5.l1c.demand_miss_rate::total      0.861391                       # miss rate for demand accesses
+system.cpu5.l1c.overall_miss_rate::cpu5      0.861391                       # miss rate for overall accesses
+system.cpu5.l1c.overall_miss_rate::total     0.861391                       # miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16219.659584                       # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_miss_latency::total 16219.659584                       # average ReadReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27648.336151                       # average WriteReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::total 27648.336151                       # average WriteReq miss latency
+system.cpu5.l1c.demand_avg_miss_latency::cpu5 20782.353972                       # average overall miss latency
+system.cpu5.l1c.demand_avg_miss_latency::total 20782.353972                       # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::cpu5 20782.353972                       # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::total 20782.353972                       # average overall miss latency
+system.cpu5.l1c.blocked_cycles::no_mshrs       771700                       # number of cycles access was blocked
 system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs               66475                       # number of cycles access was blocked
+system.cpu5.l1c.blocked::no_mshrs               65809                       # number of cycles access was blocked
 system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs    11.763054                       # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_mshrs    11.726360                       # average number of cycles each access was blocked
 system.cpu5.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu5.l1c.writebacks::writebacks           9742                       # number of writebacks
-system.cpu5.l1c.writebacks::total                9742                       # number of writebacks
-system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36426                       # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_misses::total        36426                       # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23853                       # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::total        23853                       # number of WriteReq MSHR misses
-system.cpu5.l1c.demand_mshr_misses::cpu5        60279                       # number of demand (read+write) MSHR misses
-system.cpu5.l1c.demand_mshr_misses::total        60279                       # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses::cpu5        60279                       # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_misses::total        60279                       # number of overall MSHR misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    536794980                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_latency::total    536794980                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    620108209                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::total    620108209                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1156903189                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::total   1156903189                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1156903189                       # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total   1156903189                       # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    648821919                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    648821919                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5    955346733                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total    955346733                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   1604168652                       # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::total   1604168652                       # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.808730                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.808730                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.952368                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.952368                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.860060                       # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_miss_rate::total     0.860060                       # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.860060                       # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_miss_rate::total     0.860060                       # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 14736.588700                       # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 14736.588700                       # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 25997.074121                       # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 25997.074121                       # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19192.474809                       # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19192.474809                       # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19192.474809                       # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19192.474809                       # average overall mshr miss latency
+system.cpu5.l1c.writebacks::writebacks           9916                       # number of writebacks
+system.cpu5.l1c.writebacks::total                9916                       # number of writebacks
+system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36144                       # number of ReadReq MSHR misses
+system.cpu5.l1c.ReadReq_mshr_misses::total        36144                       # number of ReadReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses::cpu5        24019                       # number of WriteReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses::total        24019                       # number of WriteReq MSHR misses
+system.cpu5.l1c.demand_mshr_misses::cpu5        60163                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.demand_mshr_misses::total        60163                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.overall_mshr_misses::cpu5        60163                       # number of overall MSHR misses
+system.cpu5.l1c.overall_mshr_misses::total        60163                       # number of overall MSHR misses
+system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    529678552                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_miss_latency::total    529678552                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    626959212                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency::total    626959212                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1156637764                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency::total   1156637764                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1156637764                       # number of overall MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::total   1156637764                       # number of overall MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    632837521                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    632837521                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5    970316626                       # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total    970316626                       # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   1603154147                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency::total   1603154147                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.808627                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.808627                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.955182                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.955182                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.861391                       # mshr miss rate for demand accesses
+system.cpu5.l1c.demand_mshr_miss_rate::total     0.861391                       # mshr miss rate for demand accesses
+system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.861391                       # mshr miss rate for overall accesses
+system.cpu5.l1c.overall_mshr_miss_rate::total     0.861391                       # mshr miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 14654.674413                       # average ReadReq mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 14654.674413                       # average ReadReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 26102.635913                       # average WriteReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 26102.635913                       # average WriteReq mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19225.067965                       # average overall mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19225.067965                       # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19225.067965                       # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19225.067965                       # average overall mshr miss latency
 system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average ReadReq mshr uncacheable latency
 system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average WriteReq mshr uncacheable latency
@@ -797,119 +797,119 @@
 system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5          inf                       # average overall mshr uncacheable latency
 system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu6.num_reads                           99492                       # number of read accesses completed
-system.cpu6.num_writes                          55188                       # number of write accesses completed
-system.cpu6.l1c.tags.replacements               22041                       # number of replacements
-system.cpu6.l1c.tags.tagsinuse             390.749630                       # Cycle average of tags in use
-system.cpu6.l1c.tags.total_refs                 13460                       # Total number of references to valid blocks.
-system.cpu6.l1c.tags.sampled_refs               22445                       # Sample count of references to valid blocks.
-system.cpu6.l1c.tags.avg_refs                0.599688                       # Average number of references to valid blocks.
+system.cpu6.num_reads                           99383                       # number of read accesses completed
+system.cpu6.num_writes                          54752                       # number of write accesses completed
+system.cpu6.l1c.tags.replacements               22371                       # number of replacements
+system.cpu6.l1c.tags.tagsinuse             391.299314                       # Cycle average of tags in use
+system.cpu6.l1c.tags.total_refs                 13429                       # Total number of references to valid blocks.
+system.cpu6.l1c.tags.sampled_refs               22762                       # Sample count of references to valid blocks.
+system.cpu6.l1c.tags.avg_refs                0.589975                       # Average number of references to valid blocks.
 system.cpu6.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.tags.occ_blocks::cpu6      390.749630                       # Average occupied blocks per requestor
-system.cpu6.l1c.tags.occ_percent::cpu6       0.763183                       # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_percent::total      0.763183                       # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_task_id_blocks::1024          404                       # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::0          397                       # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
-system.cpu6.l1c.tags.occ_task_id_percent::1024     0.789062                       # Percentage of cache occupancy per task id
-system.cpu6.l1c.tags.tag_accesses              337459                       # Number of tag accesses
-system.cpu6.l1c.tags.data_accesses             337459                       # Number of data accesses
-system.cpu6.l1c.ReadReq_hits::cpu6               8703                       # number of ReadReq hits
-system.cpu6.l1c.ReadReq_hits::total              8703                       # number of ReadReq hits
-system.cpu6.l1c.WriteReq_hits::cpu6              1158                       # number of WriteReq hits
-system.cpu6.l1c.WriteReq_hits::total             1158                       # number of WriteReq hits
-system.cpu6.l1c.demand_hits::cpu6                9861                       # number of demand (read+write) hits
-system.cpu6.l1c.demand_hits::total               9861                       # number of demand (read+write) hits
-system.cpu6.l1c.overall_hits::cpu6               9861                       # number of overall hits
-system.cpu6.l1c.overall_hits::total              9861                       # number of overall hits
-system.cpu6.l1c.ReadReq_misses::cpu6            36430                       # number of ReadReq misses
-system.cpu6.l1c.ReadReq_misses::total           36430                       # number of ReadReq misses
-system.cpu6.l1c.WriteReq_misses::cpu6           23907                       # number of WriteReq misses
-system.cpu6.l1c.WriteReq_misses::total          23907                       # number of WriteReq misses
-system.cpu6.l1c.demand_misses::cpu6             60337                       # number of demand (read+write) misses
-system.cpu6.l1c.demand_misses::total            60337                       # number of demand (read+write) misses
-system.cpu6.l1c.overall_misses::cpu6            60337                       # number of overall misses
-system.cpu6.l1c.overall_misses::total           60337                       # number of overall misses
-system.cpu6.l1c.ReadReq_miss_latency::cpu6    592106528                       # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_latency::total    592106528                       # number of ReadReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::cpu6    650271582                       # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::total    650271582                       # number of WriteReq miss cycles
-system.cpu6.l1c.demand_miss_latency::cpu6   1242378110                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_latency::total   1242378110                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.overall_miss_latency::cpu6   1242378110                       # number of overall miss cycles
-system.cpu6.l1c.overall_miss_latency::total   1242378110                       # number of overall miss cycles
-system.cpu6.l1c.ReadReq_accesses::cpu6          45133                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_accesses::total         45133                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::cpu6         25065                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::total        25065                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.demand_accesses::cpu6           70198                       # number of demand (read+write) accesses
-system.cpu6.l1c.demand_accesses::total          70198                       # number of demand (read+write) accesses
-system.cpu6.l1c.overall_accesses::cpu6          70198                       # number of overall (read+write) accesses
-system.cpu6.l1c.overall_accesses::total         70198                       # number of overall (read+write) accesses
-system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.807170                       # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_miss_rate::total     0.807170                       # miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.953800                       # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::total     0.953800                       # miss rate for WriteReq accesses
-system.cpu6.l1c.demand_miss_rate::cpu6       0.859526                       # miss rate for demand accesses
-system.cpu6.l1c.demand_miss_rate::total      0.859526                       # miss rate for demand accesses
-system.cpu6.l1c.overall_miss_rate::cpu6      0.859526                       # miss rate for overall accesses
-system.cpu6.l1c.overall_miss_rate::total     0.859526                       # miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16253.267307                       # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_miss_latency::total 16253.267307                       # average ReadReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 27200.049442                       # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::total 27200.049442                       # average WriteReq miss latency
-system.cpu6.l1c.demand_avg_miss_latency::cpu6 20590.651010                       # average overall miss latency
-system.cpu6.l1c.demand_avg_miss_latency::total 20590.651010                       # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 20590.651010                       # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 20590.651010                       # average overall miss latency
-system.cpu6.l1c.blocked_cycles::no_mshrs       773385                       # number of cycles access was blocked
+system.cpu6.l1c.tags.occ_blocks::cpu6      391.299314                       # Average occupied blocks per requestor
+system.cpu6.l1c.tags.occ_percent::cpu6       0.764256                       # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_percent::total      0.764256                       # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_task_id_blocks::1024          391                       # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::0          387                       # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
+system.cpu6.l1c.tags.occ_task_id_percent::1024     0.763672                       # Percentage of cache occupancy per task id
+system.cpu6.l1c.tags.tag_accesses              336995                       # Number of tag accesses
+system.cpu6.l1c.tags.data_accesses             336995                       # Number of data accesses
+system.cpu6.l1c.ReadReq_hits::cpu6               8731                       # number of ReadReq hits
+system.cpu6.l1c.ReadReq_hits::total              8731                       # number of ReadReq hits
+system.cpu6.l1c.WriteReq_hits::cpu6              1088                       # number of WriteReq hits
+system.cpu6.l1c.WriteReq_hits::total             1088                       # number of WriteReq hits
+system.cpu6.l1c.demand_hits::cpu6                9819                       # number of demand (read+write) hits
+system.cpu6.l1c.demand_hits::total               9819                       # number of demand (read+write) hits
+system.cpu6.l1c.overall_hits::cpu6               9819                       # number of overall hits
+system.cpu6.l1c.overall_hits::total              9819                       # number of overall hits
+system.cpu6.l1c.ReadReq_misses::cpu6            36545                       # number of ReadReq misses
+system.cpu6.l1c.ReadReq_misses::total           36545                       # number of ReadReq misses
+system.cpu6.l1c.WriteReq_misses::cpu6           23737                       # number of WriteReq misses
+system.cpu6.l1c.WriteReq_misses::total          23737                       # number of WriteReq misses
+system.cpu6.l1c.demand_misses::cpu6             60282                       # number of demand (read+write) misses
+system.cpu6.l1c.demand_misses::total            60282                       # number of demand (read+write) misses
+system.cpu6.l1c.overall_misses::cpu6            60282                       # number of overall misses
+system.cpu6.l1c.overall_misses::total           60282                       # number of overall misses
+system.cpu6.l1c.ReadReq_miss_latency::cpu6    590611551                       # number of ReadReq miss cycles
+system.cpu6.l1c.ReadReq_miss_latency::total    590611551                       # number of ReadReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::cpu6    651380889                       # number of WriteReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::total    651380889                       # number of WriteReq miss cycles
+system.cpu6.l1c.demand_miss_latency::cpu6   1241992440                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.demand_miss_latency::total   1241992440                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.overall_miss_latency::cpu6   1241992440                       # number of overall miss cycles
+system.cpu6.l1c.overall_miss_latency::total   1241992440                       # number of overall miss cycles
+system.cpu6.l1c.ReadReq_accesses::cpu6          45276                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.ReadReq_accesses::total         45276                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::cpu6         24825                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::total        24825                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.demand_accesses::cpu6           70101                       # number of demand (read+write) accesses
+system.cpu6.l1c.demand_accesses::total          70101                       # number of demand (read+write) accesses
+system.cpu6.l1c.overall_accesses::cpu6          70101                       # number of overall (read+write) accesses
+system.cpu6.l1c.overall_accesses::total         70101                       # number of overall (read+write) accesses
+system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.807161                       # miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_miss_rate::total     0.807161                       # miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.956173                       # miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::total     0.956173                       # miss rate for WriteReq accesses
+system.cpu6.l1c.demand_miss_rate::cpu6       0.859931                       # miss rate for demand accesses
+system.cpu6.l1c.demand_miss_rate::total      0.859931                       # miss rate for demand accesses
+system.cpu6.l1c.overall_miss_rate::cpu6      0.859931                       # miss rate for overall accesses
+system.cpu6.l1c.overall_miss_rate::total     0.859931                       # miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16161.213600                       # average ReadReq miss latency
+system.cpu6.l1c.ReadReq_avg_miss_latency::total 16161.213600                       # average ReadReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 27441.584404                       # average WriteReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::total 27441.584404                       # average WriteReq miss latency
+system.cpu6.l1c.demand_avg_miss_latency::cpu6 20603.039713                       # average overall miss latency
+system.cpu6.l1c.demand_avg_miss_latency::total 20603.039713                       # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::cpu6 20603.039713                       # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::total 20603.039713                       # average overall miss latency
+system.cpu6.l1c.blocked_cycles::no_mshrs       771561                       # number of cycles access was blocked
 system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_mshrs               66167                       # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_mshrs               66088                       # number of cycles access was blocked
 system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_mshrs    11.688379                       # average number of cycles each access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_mshrs    11.674752                       # average number of cycles each access was blocked
 system.cpu6.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu6.l1c.writebacks::writebacks           9775                       # number of writebacks
-system.cpu6.l1c.writebacks::total                9775                       # number of writebacks
-system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36430                       # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_misses::total        36430                       # number of ReadReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23907                       # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::total        23907                       # number of WriteReq MSHR misses
-system.cpu6.l1c.demand_mshr_misses::cpu6        60337                       # number of demand (read+write) MSHR misses
-system.cpu6.l1c.demand_mshr_misses::total        60337                       # number of demand (read+write) MSHR misses
-system.cpu6.l1c.overall_mshr_misses::cpu6        60337                       # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_misses::total        60337                       # number of overall MSHR misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    535158836                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_latency::total    535158836                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    613445646                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::total    613445646                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1148604482                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::total   1148604482                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1148604482                       # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::total   1148604482                       # number of overall MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    648116847                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    648116847                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6    997038722                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total    997038722                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   1645155569                       # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::total   1645155569                       # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.807170                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.807170                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.953800                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.953800                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.859526                       # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_miss_rate::total     0.859526                       # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.859526                       # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_miss_rate::total     0.859526                       # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 14690.058633                       # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 14690.058633                       # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 25659.666458                       # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 25659.666458                       # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19036.486435                       # average overall mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19036.486435                       # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19036.486435                       # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19036.486435                       # average overall mshr miss latency
+system.cpu6.l1c.writebacks::writebacks           9782                       # number of writebacks
+system.cpu6.l1c.writebacks::total                9782                       # number of writebacks
+system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36545                       # number of ReadReq MSHR misses
+system.cpu6.l1c.ReadReq_mshr_misses::total        36545                       # number of ReadReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23737                       # number of WriteReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::total        23737                       # number of WriteReq MSHR misses
+system.cpu6.l1c.demand_mshr_misses::cpu6        60282                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.demand_mshr_misses::total        60282                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.overall_mshr_misses::cpu6        60282                       # number of overall MSHR misses
+system.cpu6.l1c.overall_mshr_misses::total        60282                       # number of overall MSHR misses
+system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    533644023                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_miss_latency::total    533644023                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    614831387                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::total    614831387                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1148475410                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::total   1148475410                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1148475410                       # number of overall MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::total   1148475410                       # number of overall MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    641180935                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    641180935                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6    971245186                       # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total    971245186                       # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   1612426121                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::total   1612426121                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.807161                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.807161                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.956173                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.956173                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.859931                       # mshr miss rate for demand accesses
+system.cpu6.l1c.demand_mshr_miss_rate::total     0.859931                       # mshr miss rate for demand accesses
+system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.859931                       # mshr miss rate for overall accesses
+system.cpu6.l1c.overall_mshr_miss_rate::total     0.859931                       # mshr miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 14602.381256                       # average ReadReq mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 14602.381256                       # average ReadReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 25901.815183                       # average WriteReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 25901.815183                       # average WriteReq mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19051.713779                       # average overall mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19051.713779                       # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19051.713779                       # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19051.713779                       # average overall mshr miss latency
 system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average ReadReq mshr uncacheable latency
 system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average WriteReq mshr uncacheable latency
@@ -917,119 +917,119 @@
 system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6          inf                       # average overall mshr uncacheable latency
 system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu7.num_reads                           99953                       # number of read accesses completed
-system.cpu7.num_writes                          55743                       # number of write accesses completed
-system.cpu7.l1c.tags.replacements               22636                       # number of replacements
-system.cpu7.l1c.tags.tagsinuse             393.668569                       # Cycle average of tags in use
-system.cpu7.l1c.tags.total_refs                 13591                       # Total number of references to valid blocks.
-system.cpu7.l1c.tags.sampled_refs               23039                       # Sample count of references to valid blocks.
-system.cpu7.l1c.tags.avg_refs                0.589913                       # Average number of references to valid blocks.
+system.cpu7.num_reads                           99477                       # number of read accesses completed
+system.cpu7.num_writes                          54915                       # number of write accesses completed
+system.cpu7.l1c.tags.replacements               22352                       # number of replacements
+system.cpu7.l1c.tags.tagsinuse             391.525005                       # Cycle average of tags in use
+system.cpu7.l1c.tags.total_refs                 13561                       # Total number of references to valid blocks.
+system.cpu7.l1c.tags.sampled_refs               22758                       # Sample count of references to valid blocks.
+system.cpu7.l1c.tags.avg_refs                0.595878                       # Average number of references to valid blocks.
 system.cpu7.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.tags.occ_blocks::cpu7      393.668569                       # Average occupied blocks per requestor
-system.cpu7.l1c.tags.occ_percent::cpu7       0.768884                       # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_percent::total      0.768884                       # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_task_id_blocks::1024          403                       # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::0          397                       # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
-system.cpu7.l1c.tags.occ_task_id_percent::1024     0.787109                       # Percentage of cache occupancy per task id
-system.cpu7.l1c.tags.tag_accesses              340053                       # Number of tag accesses
-system.cpu7.l1c.tags.data_accesses             340053                       # Number of data accesses
-system.cpu7.l1c.ReadReq_hits::cpu7               8802                       # number of ReadReq hits
-system.cpu7.l1c.ReadReq_hits::total              8802                       # number of ReadReq hits
-system.cpu7.l1c.WriteReq_hits::cpu7              1188                       # number of WriteReq hits
-system.cpu7.l1c.WriteReq_hits::total             1188                       # number of WriteReq hits
-system.cpu7.l1c.demand_hits::cpu7                9990                       # number of demand (read+write) hits
-system.cpu7.l1c.demand_hits::total               9990                       # number of demand (read+write) hits
-system.cpu7.l1c.overall_hits::cpu7               9990                       # number of overall hits
-system.cpu7.l1c.overall_hits::total              9990                       # number of overall hits
-system.cpu7.l1c.ReadReq_misses::cpu7            36601                       # number of ReadReq misses
-system.cpu7.l1c.ReadReq_misses::total           36601                       # number of ReadReq misses
-system.cpu7.l1c.WriteReq_misses::cpu7           24152                       # number of WriteReq misses
-system.cpu7.l1c.WriteReq_misses::total          24152                       # number of WriteReq misses
-system.cpu7.l1c.demand_misses::cpu7             60753                       # number of demand (read+write) misses
-system.cpu7.l1c.demand_misses::total            60753                       # number of demand (read+write) misses
-system.cpu7.l1c.overall_misses::cpu7            60753                       # number of overall misses
-system.cpu7.l1c.overall_misses::total           60753                       # number of overall misses
-system.cpu7.l1c.ReadReq_miss_latency::cpu7    595212008                       # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_latency::total    595212008                       # number of ReadReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::cpu7    656742976                       # number of WriteReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::total    656742976                       # number of WriteReq miss cycles
-system.cpu7.l1c.demand_miss_latency::cpu7   1251954984                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.demand_miss_latency::total   1251954984                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.overall_miss_latency::cpu7   1251954984                       # number of overall miss cycles
-system.cpu7.l1c.overall_miss_latency::total   1251954984                       # number of overall miss cycles
-system.cpu7.l1c.ReadReq_accesses::cpu7          45403                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_accesses::total         45403                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::cpu7         25340                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::total        25340                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.demand_accesses::cpu7           70743                       # number of demand (read+write) accesses
-system.cpu7.l1c.demand_accesses::total          70743                       # number of demand (read+write) accesses
-system.cpu7.l1c.overall_accesses::cpu7          70743                       # number of overall (read+write) accesses
-system.cpu7.l1c.overall_accesses::total         70743                       # number of overall (read+write) accesses
-system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.806136                       # miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_miss_rate::total     0.806136                       # miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.953118                       # miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::total     0.953118                       # miss rate for WriteReq accesses
-system.cpu7.l1c.demand_miss_rate::cpu7       0.858785                       # miss rate for demand accesses
-system.cpu7.l1c.demand_miss_rate::total      0.858785                       # miss rate for demand accesses
-system.cpu7.l1c.overall_miss_rate::cpu7      0.858785                       # miss rate for overall accesses
-system.cpu7.l1c.overall_miss_rate::total     0.858785                       # miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16262.178848                       # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_miss_latency::total 16262.178848                       # average ReadReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 27192.074197                       # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::total 27192.074197                       # average WriteReq miss latency
-system.cpu7.l1c.demand_avg_miss_latency::cpu7 20607.294850                       # average overall miss latency
-system.cpu7.l1c.demand_avg_miss_latency::total 20607.294850                       # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::cpu7 20607.294850                       # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::total 20607.294850                       # average overall miss latency
-system.cpu7.l1c.blocked_cycles::no_mshrs       772653                       # number of cycles access was blocked
+system.cpu7.l1c.tags.occ_blocks::cpu7      391.525005                       # Average occupied blocks per requestor
+system.cpu7.l1c.tags.occ_percent::cpu7       0.764697                       # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_percent::total      0.764697                       # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_task_id_blocks::1024          406                       # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::0          391                       # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::1           15                       # Occupied blocks per task id
+system.cpu7.l1c.tags.occ_task_id_percent::1024     0.792969                       # Percentage of cache occupancy per task id
+system.cpu7.l1c.tags.tag_accesses              337629                       # Number of tag accesses
+system.cpu7.l1c.tags.data_accesses             337629                       # Number of data accesses
+system.cpu7.l1c.ReadReq_hits::cpu7               8790                       # number of ReadReq hits
+system.cpu7.l1c.ReadReq_hits::total              8790                       # number of ReadReq hits
+system.cpu7.l1c.WriteReq_hits::cpu7              1137                       # number of WriteReq hits
+system.cpu7.l1c.WriteReq_hits::total             1137                       # number of WriteReq hits
+system.cpu7.l1c.demand_hits::cpu7                9927                       # number of demand (read+write) hits
+system.cpu7.l1c.demand_hits::total               9927                       # number of demand (read+write) hits
+system.cpu7.l1c.overall_hits::cpu7               9927                       # number of overall hits
+system.cpu7.l1c.overall_hits::total              9927                       # number of overall hits
+system.cpu7.l1c.ReadReq_misses::cpu7            36477                       # number of ReadReq misses
+system.cpu7.l1c.ReadReq_misses::total           36477                       # number of ReadReq misses
+system.cpu7.l1c.WriteReq_misses::cpu7           23844                       # number of WriteReq misses
+system.cpu7.l1c.WriteReq_misses::total          23844                       # number of WriteReq misses
+system.cpu7.l1c.demand_misses::cpu7             60321                       # number of demand (read+write) misses
+system.cpu7.l1c.demand_misses::total            60321                       # number of demand (read+write) misses
+system.cpu7.l1c.overall_misses::cpu7            60321                       # number of overall misses
+system.cpu7.l1c.overall_misses::total           60321                       # number of overall misses
+system.cpu7.l1c.ReadReq_miss_latency::cpu7    593716610                       # number of ReadReq miss cycles
+system.cpu7.l1c.ReadReq_miss_latency::total    593716610                       # number of ReadReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::cpu7    651325348                       # number of WriteReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::total    651325348                       # number of WriteReq miss cycles
+system.cpu7.l1c.demand_miss_latency::cpu7   1245041958                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.demand_miss_latency::total   1245041958                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.overall_miss_latency::cpu7   1245041958                       # number of overall miss cycles
+system.cpu7.l1c.overall_miss_latency::total   1245041958                       # number of overall miss cycles
+system.cpu7.l1c.ReadReq_accesses::cpu7          45267                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.ReadReq_accesses::total         45267                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::cpu7         24981                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::total        24981                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.demand_accesses::cpu7           70248                       # number of demand (read+write) accesses
+system.cpu7.l1c.demand_accesses::total          70248                       # number of demand (read+write) accesses
+system.cpu7.l1c.overall_accesses::cpu7          70248                       # number of overall (read+write) accesses
+system.cpu7.l1c.overall_accesses::total         70248                       # number of overall (read+write) accesses
+system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.805819                       # miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_miss_rate::total     0.805819                       # miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.954485                       # miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::total     0.954485                       # miss rate for WriteReq accesses
+system.cpu7.l1c.demand_miss_rate::cpu7       0.858686                       # miss rate for demand accesses
+system.cpu7.l1c.demand_miss_rate::total      0.858686                       # miss rate for demand accesses
+system.cpu7.l1c.overall_miss_rate::cpu7      0.858686                       # miss rate for overall accesses
+system.cpu7.l1c.overall_miss_rate::total     0.858686                       # miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16276.464896                       # average ReadReq miss latency
+system.cpu7.l1c.ReadReq_avg_miss_latency::total 16276.464896                       # average ReadReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 27316.110887                       # average WriteReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::total 27316.110887                       # average WriteReq miss latency
+system.cpu7.l1c.demand_avg_miss_latency::cpu7 20640.273835                       # average overall miss latency
+system.cpu7.l1c.demand_avg_miss_latency::total 20640.273835                       # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::cpu7 20640.273835                       # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::total 20640.273835                       # average overall miss latency
+system.cpu7.l1c.blocked_cycles::no_mshrs       768557                       # number of cycles access was blocked
 system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_mshrs               66243                       # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_mshrs               65923                       # number of cycles access was blocked
 system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_mshrs    11.663919                       # average number of cycles each access was blocked
+system.cpu7.l1c.avg_blocked_cycles::no_mshrs    11.658405                       # average number of cycles each access was blocked
 system.cpu7.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu7.l1c.writebacks::writebacks           9979                       # number of writebacks
-system.cpu7.l1c.writebacks::total                9979                       # number of writebacks
-system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36601                       # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_misses::total        36601                       # number of ReadReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::cpu7        24152                       # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::total        24152                       # number of WriteReq MSHR misses
-system.cpu7.l1c.demand_mshr_misses::cpu7        60753                       # number of demand (read+write) MSHR misses
-system.cpu7.l1c.demand_mshr_misses::total        60753                       # number of demand (read+write) MSHR misses
-system.cpu7.l1c.overall_mshr_misses::cpu7        60753                       # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_misses::total        60753                       # number of overall MSHR misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    538040158                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_miss_latency::total    538040158                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    619565494                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::total    619565494                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1157605652                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::total   1157605652                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1157605652                       # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::total   1157605652                       # number of overall MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    639132078                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    639132078                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7    986824111                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total    986824111                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   1625956189                       # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::total   1625956189                       # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.806136                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.806136                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.953118                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.953118                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.858785                       # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_miss_rate::total     0.858785                       # mshr miss rate for demand accesses
-system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.858785                       # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_miss_rate::total     0.858785                       # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 14700.149122                       # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 14700.149122                       # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 25652.761428                       # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 25652.761428                       # average WriteReq mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19054.296117                       # average overall mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19054.296117                       # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19054.296117                       # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19054.296117                       # average overall mshr miss latency
+system.cpu7.l1c.writebacks::writebacks           9939                       # number of writebacks
+system.cpu7.l1c.writebacks::total                9939                       # number of writebacks
+system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36477                       # number of ReadReq MSHR misses
+system.cpu7.l1c.ReadReq_mshr_misses::total        36477                       # number of ReadReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23844                       # number of WriteReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::total        23844                       # number of WriteReq MSHR misses
+system.cpu7.l1c.demand_mshr_misses::cpu7        60321                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.demand_mshr_misses::total        60321                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.overall_mshr_misses::cpu7        60321                       # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_misses::total        60321                       # number of overall MSHR misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    536729312                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_latency::total    536729312                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    614614324                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::total    614614324                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1151343636                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::total   1151343636                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1151343636                       # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::total   1151343636                       # number of overall MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    635643033                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    635643033                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7    965131654                       # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total    965131654                       # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   1600774687                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::total   1600774687                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.805819                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.805819                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.954485                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.954485                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.858686                       # mshr miss rate for demand accesses
+system.cpu7.l1c.demand_mshr_miss_rate::total     0.858686                       # mshr miss rate for demand accesses
+system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.858686                       # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_miss_rate::total     0.858686                       # mshr miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 14714.184609                       # average ReadReq mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 14714.184609                       # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 25776.477269                       # average WriteReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 25776.477269                       # average WriteReq mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19086.945442                       # average overall mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19086.945442                       # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19086.945442                       # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19086.945442                       # average overall mshr miss latency
 system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average ReadReq mshr uncacheable latency
 system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average WriteReq mshr uncacheable latency
@@ -1037,566 +1037,567 @@
 system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7          inf                       # average overall mshr uncacheable latency
 system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                    13510                       # number of replacements
-system.l2c.tags.tagsinuse                  783.849989                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     151949                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                    14294                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    10.630264                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                    13851                       # number of replacements
+system.l2c.tags.tagsinuse                  783.697862                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     151322                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                    14625                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    10.346803                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks     725.717756                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0             7.606207                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1             7.042760                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2             7.314362                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3             7.280142                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4             6.903512                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5             7.337678                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6             7.211948                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7             7.435623                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.708709                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0            0.007428                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1            0.006878                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2            0.007143                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3            0.007110                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu4            0.006742                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu5            0.007166                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu6            0.007043                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu7            0.007261                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.765479                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024          784                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          680                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          104                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.765625                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  1986932                       # Number of tag accesses
-system.l2c.tags.data_accesses                 1986932                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0                   10772                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1                   10720                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2                   10796                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3                   10828                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu4                   10876                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu5                   10784                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu6                   10725                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu7                   10741                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                  86242                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks           77037                       # number of Writeback hits
-system.l2c.Writeback_hits::total                77037                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0                  331                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1                  373                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2                  363                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3                  353                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4                  321                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5                  363                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6                  346                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7                  366                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                2816                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0                  2031                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1                  1999                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2                  1974                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3                  2000                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu4                  1993                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu5                  1980                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu6                  1967                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu7                  1970                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                15914                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0                    12803                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1                    12719                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2                    12770                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3                    12828                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu4                    12869                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu5                    12764                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu6                    12692                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu7                    12711                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  102156                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0                   12803                       # number of overall hits
-system.l2c.overall_hits::cpu1                   12719                       # number of overall hits
-system.l2c.overall_hits::cpu2                   12770                       # number of overall hits
-system.l2c.overall_hits::cpu3                   12828                       # number of overall hits
-system.l2c.overall_hits::cpu4                   12869                       # number of overall hits
-system.l2c.overall_hits::cpu5                   12764                       # number of overall hits
-system.l2c.overall_hits::cpu6                   12692                       # number of overall hits
-system.l2c.overall_hits::cpu7                   12711                       # number of overall hits
-system.l2c.overall_hits::total                 102156                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0                   731                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1                   674                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2                   746                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3                   694                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu4                   702                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu5                   746                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu6                   722                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu7                   727                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                 5742                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0               1949                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1               2075                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2               2001                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3               2024                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu4               1976                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu5               1982                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu6               1991                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu7               1901                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             15899                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0                4373                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1                4324                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2                4508                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3                4412                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu4                4451                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu5                4429                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu6                4229                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu7                4405                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total              35131                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0                   5104                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1                   4998                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2                   5254                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3                   5106                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu4                   5153                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu5                   5175                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu6                   4951                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu7                   5132                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                 40873                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0                  5104                       # number of overall misses
-system.l2c.overall_misses::cpu1                  4998                       # number of overall misses
-system.l2c.overall_misses::cpu2                  5254                       # number of overall misses
-system.l2c.overall_misses::cpu3                  5106                       # number of overall misses
-system.l2c.overall_misses::cpu4                  5153                       # number of overall misses
-system.l2c.overall_misses::cpu5                  5175                       # number of overall misses
-system.l2c.overall_misses::cpu6                  4951                       # number of overall misses
-system.l2c.overall_misses::cpu7                  5132                       # number of overall misses
-system.l2c.overall_misses::total                40873                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0        45095926                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1        41549422                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2        46449929                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3        42922928                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu4        43252423                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu5        45919927                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu6        44260438                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu7        44979437                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total      354430430                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0     56379995                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1     59258495                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2     58685995                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu3     56511495                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu4     59771492                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu5     56753497                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu6     61514994                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu7     54850495                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    463726458                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0     240858936                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1     238452262                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2     247966448                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3     242840437                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu4     244973443                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu5     243557270                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu6     233129438                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu7     242077945                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   1933856179                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0        285954862                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1        280001684                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2        294416377                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3        285763365                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu4        288225866                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu5        289477197                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu6        277389876                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu7        287057382                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      2288286609                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0       285954862                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1       280001684                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2       294416377                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3       285763365                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu4       288225866                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu5       289477197                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu6       277389876                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu7       287057382                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     2288286609                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0               11503                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1               11394                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2               11542                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3               11522                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu4               11578                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu5               11530                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu6               11447                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu7               11468                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total              91984                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks        77037                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total            77037                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0             2280                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1             2448                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2             2364                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3             2377                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu4             2297                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu5             2345                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu6             2337                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu7             2267                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           18715                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0              6404                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1              6323                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2              6482                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3              6412                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu4              6444                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu5              6409                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu6              6196                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu7              6375                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total            51045                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0                17907                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1                17717                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2                18024                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3                17934                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu4                18022                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu5                17939                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu6                17643                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu7                17843                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              143029                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0               17907                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1               17717                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2               18024                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3               17934                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu4               18022                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu5               17939                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu6               17643                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu7               17843                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             143029                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0           0.063549                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1           0.059154                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2           0.064634                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3           0.060233                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu4           0.060632                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu5           0.064701                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu6           0.063073                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu7           0.063394                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.062424                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0        0.854825                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1        0.847631                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2        0.846447                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3        0.851493                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu4        0.860253                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu5        0.845203                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu6        0.851947                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu7        0.838553                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.849532                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0         0.682854                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1         0.683853                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2         0.695464                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3         0.688085                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu4         0.690720                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu5         0.691059                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu6         0.682537                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu7         0.690980                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.688236                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0            0.285028                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1            0.282102                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2            0.291500                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3            0.284711                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu4            0.285928                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu5            0.288478                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu6            0.280621                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu7            0.287620                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.285767                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0           0.285028                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1           0.282102                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2           0.291500                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3           0.284711                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu4           0.285928                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu5           0.288478                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu6           0.280621                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu7           0.287620                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.285767                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0 61690.733242                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1 61646.026706                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2 62265.320375                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3 61848.599424                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu4 61613.138177                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu5 61554.861930                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu6 61302.545706                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu7 61869.927098                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 61725.954371                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0 28927.652642                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1 28558.310843                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2 29328.333333                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3 27920.699111                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu4 30248.730769                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu5 28634.458628                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu6 30896.531391                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu7 28853.495529                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 29167.020442                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0 55078.649897                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1 55146.221554                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2 55005.866903                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3 55040.896872                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu4 55037.843855                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu5 54991.481147                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu6 55126.374557                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu7 54955.265607                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 55047.000626                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0 56025.639107                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1 56022.745898                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2 56036.615341                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3 55966.189777                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu4 55933.604890                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu5 55937.622609                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu6 56027.040194                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu7 55934.797740                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 55985.286350                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0 56025.639107                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1 56022.745898                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2 56036.615341                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3 55966.189777                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu4 55933.604890                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu5 55937.622609                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu6 56027.040194                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu7 55934.797740                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 55985.286350                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs             17581                       # number of cycles access was blocked
+system.l2c.tags.occ_blocks::writebacks     724.401984                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0             7.094586                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1             7.546674                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2             7.606935                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3             7.397120                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu4             7.288170                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu5             7.917650                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu6             7.470007                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu7             6.974735                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.707424                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0            0.006928                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1            0.007370                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2            0.007429                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3            0.007224                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu4            0.007117                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu5            0.007732                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu6            0.007295                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu7            0.006811                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.765330                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024          774                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          649                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          125                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.755859                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  1983958                       # Number of tag accesses
+system.l2c.tags.data_accesses                 1983958                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0                   10711                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1                   10778                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2                   10851                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3                   10748                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu4                   10782                       # number of ReadReq hits
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+system.l2c.UpgradeReq_miss_rate::cpu1        0.837288                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2        0.836332                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3        0.840573                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu4        0.841751                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu5        0.854352                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu6        0.841805                       # miss rate for UpgradeReq accesses
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+system.l2c.demand_avg_miss_latency::cpu4 56043.030853                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu5 56063.791263                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu6 56114.505537                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu7 55995.750246                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 56045.535033                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0 56121.374708                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1 56044.780135                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2 56004.128956                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3 55975.608393                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu4 56043.030853                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu5 56063.791263                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu6 56114.505537                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu7 55995.750246                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 56045.535033                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs             17878                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                     3250                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                     3319                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      5.409538                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs      5.386562                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks                6423                       # number of writebacks
-system.l2c.writebacks::total                     6423                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0                  6                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1                 13                       # number of ReadReq MSHR hits
+system.l2c.writebacks::writebacks                6553                       # number of writebacks
+system.l2c.writebacks::total                     6553                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0                  8                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1                  8                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu2                  8                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu3                  4                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu4                 10                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu5                  5                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu6                 11                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu7                  4                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                61                       # number of ReadReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::cpu1               1                       # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::cpu3               1                       # number of UpgradeReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu3                  6                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu4                  7                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu5                 11                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu6                  5                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu7                  7                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                60                       # number of ReadReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu4               1                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu7               1                       # number of UpgradeReq MSHR hits
 system.l2c.UpgradeReq_mshr_hits::total              2                       # number of UpgradeReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu0                5                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu1                7                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu2                3                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu3                6                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu4                9                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu5                6                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu7                3                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::total              39                       # number of ReadExReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0                  11                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1                  20                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2                  11                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3                  10                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu4                  19                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu5                  11                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu6                  11                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu7                   7                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                100                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0                 11                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1                 20                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2                 11                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3                 10                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu4                 19                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu5                 11                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu6                 11                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu7                  7                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               100                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0              725                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1              661                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2              738                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3              690                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu4              692                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu5              741                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu6              711                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu7              723                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total            5681                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0          1949                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1          2074                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2          2001                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3          2023                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu4          1976                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu5          1982                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu6          1991                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu7          1901                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        15897                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0           4368                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1           4317                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2           4505                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3           4406                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu4           4442                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu5           4423                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu6           4229                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu7           4402                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         35092                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0              5093                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1              4978                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2              5243                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3              5096                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu4              5134                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu5              5164                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu6              4940                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu7              5125                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total            40773                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0             5093                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1             4978                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2             5243                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3             5096                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu4             5134                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu5             5164                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu6             4940                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu7             5125                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total           40773                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0     36140918                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1     33131910                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2     37333917                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3     34463914                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu4     34507911                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu5     36862423                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu6     35293427                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu7     36098935                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    283833355                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0     82188451                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1     87682473                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2     84603955                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3     85652462                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu4     83560954                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu5     83969963                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu6     84367474                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu7     80329284                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    672355016                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0    188025870                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1    186115345                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2    193429372                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3    189404867                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu4    191140359                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu5    189945201                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu6    182082372                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu7    188836863                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   1508980249                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0    224166788                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1    219247255                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2    230763289                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3    223868781                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu4    225648270                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu5    226807624                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu6    217375799                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu7    224935798                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   1792813604                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0    224166788                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1    219247255                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2    230763289                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3    223868781                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu4    225648270                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu5    226807624                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu6    217375799                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu7    224935798                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   1792813604                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    419997297                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    420394389                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    416554764                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    421667758                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    426680271                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    424776767                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    425015068                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    419160275                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   3374246589                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    245735705                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    245037892                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    243130891                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    240328902                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    241689545                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    236933897                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    244635896                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    245230718                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1942723446                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0    665733002                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1    665432281                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2    659685655                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu3    661996660                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu4    668369816                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu5    661710664                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu6    669650964                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu7    664390993                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   5316970035                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0      0.063027                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1      0.058013                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2      0.063940                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3      0.059885                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu4      0.059769                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu5      0.064267                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu6      0.062112                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu7      0.063045                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.061761                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.854825                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.847222                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.846447                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.851073                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.860253                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.845203                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.851947                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.838553                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.849426                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.682074                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.682746                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.695002                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.687149                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.689323                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.690123                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.682537                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.690510                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.687472                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0       0.284414                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1       0.280973                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2       0.290890                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3       0.284153                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu4       0.284874                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu5       0.287864                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu6       0.279998                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu7       0.287227                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.285068                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0      0.284414                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1      0.280973                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2      0.290890                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3      0.284153                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu4      0.284874                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu5      0.287864                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu6      0.279998                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu7      0.287227                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.285068                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 49849.542069                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 50123.918306                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50587.963415                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49947.701449                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49866.923410                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49746.859649                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49639.137834                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 49929.370678                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 49961.864989                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42169.548999                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42276.987946                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 42280.837081                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 42339.328720                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42287.932186                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42366.278002                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 42374.421899                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42256.330352                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42294.459080                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 43046.215659                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 43112.194811                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42936.597558                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42987.940763                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 43030.247411                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42944.879267                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 43055.656656                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42897.969786                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 43000.691012                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0 44014.684469                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1 44043.241262                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2 44013.596986                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3 43930.294545                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu4 43951.747176                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu5 43920.918668                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu6 44003.198178                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu7 43889.911805                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 43970.608098                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0 44014.684469                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1 44043.241262                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2 44013.596986                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3 43930.294545                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu4 43951.747176                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu5 43920.918668                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu6 44003.198178                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu7 43889.911805                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 43970.608098                       # average overall mshr miss latency
+system.l2c.ReadExReq_mshr_hits::cpu0                4                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu1                6                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu2                7                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu3                7                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu4                5                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu5                9                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu6                4                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu7                6                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::total              48                       # number of ReadExReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0                  12                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1                  14                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2                  15                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3                  13                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu4                  12                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu5                  20                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu6                   9                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu7                  13                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                108                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0                 12                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1                 14                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2                 15                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3                 13                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu4                 12                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu5                 20                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu6                  9                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu7                 13                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total               108                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0              690                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1              748                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2              723                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3              759                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu4              699                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu5              748                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu6              725                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu7              711                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total            5803                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0          1969                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1          1976                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2          1906                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3          1935                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu4          1999                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu5          2012                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu6          1921                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu7          1986                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        15704                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0           4438                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1           4282                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2           4318                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu3           4399                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu4           4410                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu5           4497                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu6           4413                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu7           4365                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         35122                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0              5128                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1              5030                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2              5041                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3              5158                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu4              5109                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu5              5245                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu6              5138                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu7              5076                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            40925                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0             5128                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1             5030                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2             5041                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3             5158                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu4             5109                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu5             5245                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu6             5138                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu7             5076                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           40925                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0     35173417                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1     37031918                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2     36254417                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3     37641417                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu4     35371412                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu5     37570056                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu6     36289420                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu7     36247403                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total    291579460                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0     83090959                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1     83391451                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2     80567464                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3     81939961                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu4     84801962                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu5     85113946                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu6     81126982                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu7     83903452                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    663936177                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0    190977391                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1    184459864                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2    185520379                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3    189280870                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu4    189565364                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu5    193586876                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu6    190188358                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu7    187005383                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   1510584485                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0    226150808                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1    221491782                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2    221774796                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3    226922287                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu4    224936776                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu5    231156932                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu6    226477778                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu7    223252786                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   1802163945                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0    226150808                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1    221491782                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2    221774796                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3    226922287                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu4    224936776                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu5    231156932                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu6    226477778                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu7    223252786                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   1802163945                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    423951568                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    418494765                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    418742272                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    420173606                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    417698791                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    416045242                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    420505761                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    416931790                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   3352543795                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    241936896                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    242321875                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    237941390                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    239219888                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    241365909                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    242888399                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    243671384                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    242767880                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1932113621                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0    665888464                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1    660816640                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2    656683662                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3    659393494                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu4    659064700                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu5    658933641                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu6    664177145                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu7    659699670                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   5284657416                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0      0.060479                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1      0.064852                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2      0.062424                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3      0.065925                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu4      0.060846                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu5      0.065089                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu6      0.063652                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu7      0.060811                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.063008                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.850540                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.837288                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.836332                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.840573                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.841330                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.854352                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.841805                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.855297                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.844710                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.699890                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.682064                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.683444                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.698365                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.687344                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.686041                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.691476                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.697173                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.690698                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0       0.288901                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1       0.282394                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2       0.281620                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3       0.289580                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4       0.285355                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5       0.290630                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6       0.289106                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7       0.282738                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.286289                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0      0.288901                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1      0.282394                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2      0.281620                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3      0.289580                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4      0.285355                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5      0.290630                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu6      0.289106                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu7      0.282738                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.286289                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50975.966667                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49507.911765                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50144.421853                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49593.434783                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 50602.878398                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 50227.347594                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 50054.372414                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50980.876231                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 50246.331208                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42199.572880                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42202.151316                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 42270.442812                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 42346.233075                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42422.192096                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42303.154076                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 42231.640812                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42247.458207                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42278.156966                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 43032.309824                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 43077.969173                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42964.423113                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 43028.158672                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42985.343311                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 43048.004447                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 43097.293904                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42842.012142                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 43009.637407                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 44101.171607                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1 44034.151491                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2 43994.206705                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3 43994.239434                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu4 44027.554512                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu5 44071.865014                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu6 44078.975866                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu7 43982.030339                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 44035.771411                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0 44101.171607                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 44034.151491                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2 43994.206705                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 43994.239434                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 44027.554512                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu5 44071.865014                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 44078.975866                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu7 43982.030339                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 44035.771411                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
@@ -1625,64 +1626,64 @@
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu7          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               84922                       # Transaction distribution
-system.membus.trans_dist::ReadResp              84916                       # Transaction distribution
-system.membus.trans_dist::WriteReq              43774                       # Transaction distribution
-system.membus.trans_dist::WriteResp             43771                       # Transaction distribution
-system.membus.trans_dist::Writeback              6423                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            58524                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           47755                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             50059                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3238                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       423382                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 423382                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      1104141                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 1104141                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                            57586                       # Total snoops (count)
-system.membus.snoop_fanout::samples            124108                       # Request fanout histogram
+system.membus.trans_dist::ReadReq               84510                       # Transaction distribution
+system.membus.trans_dist::ReadResp              84504                       # Transaction distribution
+system.membus.trans_dist::WriteReq              43512                       # Transaction distribution
+system.membus.trans_dist::WriteResp             43509                       # Transaction distribution
+system.membus.trans_dist::Writeback              6553                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            58529                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           47554                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             49190                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3281                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       421142                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 421142                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      1121847                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 1121847                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                            56880                       # Total snoops (count)
+system.membus.snoop_fanout::samples            123632                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  124108    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  123632    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              124108                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           285888056                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization              60.1                       # Layer utilization (%)
-system.membus.respLayer0.occupancy          306910429                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization             64.5                       # Layer utilization (%)
-system.toL2Bus.trans_dist::ReadReq             371514                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            371497                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate            4                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             43774                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            43771                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback            77037                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           29480                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          29478                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           162492                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          162484                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       121222                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       121108                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       121316                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       121170                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       121269                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       120769                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       120825                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       121366                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                969045                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1773466                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1761542                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1792162                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1783057                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1785037                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1774053                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1756466                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1780883                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               14206666                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          322486                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples           565861                       # Request fanout histogram
+system.membus.snoop_fanout::total              123632                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           285799779                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization              60.4                       # Layer utilization (%)
+system.membus.respLayer0.occupancy          306149550                       # Layer occupancy (ticks)
+system.membus.respLayer0.utilization             64.7                       # Layer utilization (%)
+system.toL2Bus.trans_dist::ReadReq             370575                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            370557                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadRespWithInvalidate            7                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             43514                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            43509                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback            76857                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           29562                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          29559                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           161030                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          161024                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       120584                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       120575                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       120590                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       120769                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       120586                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       120766                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       120584                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       120839                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total                965293                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1758906                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1769834                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1777815                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1771618                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1766732                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1791122                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1765164                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1788112                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               14189303                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          320901                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples           563826                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::mean                   7                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::stdev                  0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
@@ -1693,29 +1694,29 @@
 system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::5                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::6                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7                 565861    100.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7                 563826    100.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              7                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              7                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             565861                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          447470354                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization             94.1                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         102002382                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total             563826                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          445759226                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization             94.2                       # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy         101149991                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization            21.4                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         101806870                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         101191512                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization            21.4                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         101634818                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         101359906                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization            21.4                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         101702738                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization            21.4                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy         101696707                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         101648274                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization            21.5                       # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy         101307289                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer4.utilization            21.4                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy         101422885                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization            21.3                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy         101516818                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization            21.3                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy         101999422                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy         101134998                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization            21.4                       # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy         101213033                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization            21.4                       # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy         101242964                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer7.utilization            21.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------