commit d8dd86d4ce94e3e10d9369c0cb4287dd402a9401
author Giacomo Travaglini <giacomo.travaglini@arm.com> Fri Dec 14 11:16:15 2018 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Fri Jan 25 12:55:27 2019 +0000
tree 8aaf104af8ee4c49f090ad41be8fb687a358b819
parent 3d15150d715521b8ff9778dbc90061dc9ab72b8e

arch: Fix VecElem Operand generation in ISA parser

Fixes include:

* Change of reg_class: VecElemClass in lieau of non-existing
  VectorElemClass.
* Removal of unused regId in operand constructor
* makeRead and makeWrite are using VecElem (which is a typedef
  of uint32_t) as a source/destination type, regardless of the real
  operand type (which is specified by ctype)

Change-Id: I4588e1120e1fc8fdb68b2b2f05d5e3692c55b2e8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15602
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

src/arch/isa_parser.py

diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index bd46216..755f966 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2014, 2016 ARM Limited
+# Copyright (c) 2014, 2016, 2019 ARM Limited
 # All rights reserved
 #
 # The license below extends only to copyright in the software and shall
@@ -807,7 +807,7 @@
             self.op_rd = self.makeReadW(predWrite) + self.op_rd
 
 class VecElemOperand(Operand):
-    reg_class = 'VectorElemClass'
+    reg_class = 'VecElemClass'
 
     def isReg(self):
         return 1
@@ -826,8 +826,6 @@
         c_dest = ''
 
         numAccessNeeded = 1
-        regId = 'RegId(%s, %s * numVecElemPerVecReg + elemIdx, %s)' % \
-                (self.reg_class, self.reg_spec)
 
         if self.is_src:
             c_src = ('\n\t_srcRegIdx[_numSrcRegs++] = RegId(%s, %s, %s);' %
@@ -840,15 +838,26 @@
         return c_src + c_dest
 
     def makeRead(self, predRead):
-        c_read = ('\n/* Elem is kept inside the operand description */' +
-                  '\n\tVecElem %s = xc->readVecElemOperand(this, %d);' %
-                  (self.base_name, self.src_reg_idx))
-        return c_read
+        c_read = 'xc->readVecElemOperand(this, %d)' % self.src_reg_idx
+
+        if self.ctype == 'float':
+            c_read = 'bitsToFloat32(%s)' % c_read
+        elif self.ctype == 'double':
+            c_read = 'bitsToFloat64(%s)' % c_read
+
+        return '\n\t%s %s = %s;\n' % (self.ctype, self.base_name, c_read)
 
     def makeWrite(self, predWrite):
-        c_write = ('\n/* Elem is kept inside the operand description */' +
-                   '\n\txc->setVecElemOperand(this, %d, %s);' %
-                   (self.dest_reg_idx, self.base_name))
+        if self.ctype == 'float':
+            c_write = 'floatToBits32(%s)' % self.base_name
+        elif self.ctype == 'double':
+            c_write = 'floatToBits64(%s)' % self.base_name
+        else:
+            c_write = self.base_name
+
+        c_write = ('\n\txc->setVecElemOperand(this, %d, %s);' %
+                  (self.dest_reg_idx, c_write))
+
         return c_write
 
 class CCRegOperand(Operand):