commit db190b8e68c1b3230ac45b75bf74da41a94c7ca2
author Gabe Black <gabeblack@google.com> Mon Nov 19 19:03:24 2018 -0800
committer Gabe Black <gabeblack@google.com> Thu Jan 24 23:44:34 2019 +0000
tree 5cd197e20e6f554ecb1d5fde921b0891f018fa47
parent d65f3f9a846b65d6a1596aa143a555bd0d4287ab

hsail: Remove the MiscReg type.

It has been replaced by the ISA agnostic RegVal.

Change-Id: I563ea3852e37b5c1cf51eb0ac9a6f2a827ba89cf
Reviewed-on: https://gem5-review.googlesource.com/c/14464
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

src/arch/hsail/gpu_isa.hh

diff --git a/src/arch/hsail/gpu_isa.hh b/src/arch/hsail/gpu_isa.hh
index fa2cde3..86af905 100644
--- a/src/arch/hsail/gpu_isa.hh
+++ b/src/arch/hsail/gpu_isa.hh
@@ -45,8 +45,6 @@
 
 namespace HsailISA
 {
-    typedef uint64_t MiscReg;
-
     class GPUISA
     {
       public:
@@ -55,12 +53,12 @@
         }
 
         void
-        writeMiscReg(int opIdx, MiscReg operandVal)
+        writeMiscReg(int opIdx, RegVal operandVal)
         {
             fatal("HSAIL does not implement misc registers yet\n");
         }
 
-        MiscReg
+        RegVal
         readMiscReg(int opIdx) const
         {
             fatal("HSAIL does not implement misc registers yet\n");