tree 6bbce775be769190455e5885029e7b592ca27c3b
parent 9181c2ea16d384c57e6bb4e757ecaf1b52b8e7f1
author Adrien Pesle <adrien.pesle@arm.com> 1539340953 +0200
committer Giacomo Travaglini <giacomo.travaglini@arm.com> 1539787634 +0000

dev-arm: Don't panic when EOIR a non active PPI

GIC architecture specification says that writing EOIR with
a not active irq it is an unpredictable behavior.
So, just warn when it happens for a PPI case, like it is
already done in SPI case.

Change-Id: Icb1b8f5690d5e87b15c3b0fe2ca0d37fdd4085ee
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13556
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>