tree 99b2cc04c0407bb48789f070a454662ec757a943
parent 9059aafbd3157f515d23b7ba5e89a2d1a8cfd41a
author Giacomo Travaglini <giacomo.travaglini@arm.com> 1552042022 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> 1553693350 +0000

dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0)

For SGIs and PPIs:
* When ARE is 1 (only value supported in gem5) for the Security state of
an interrupt, the field for that interrupt is RES0 and an implementation
is permitted to make the field RAZ/WI in this case.

Change-Id: I6da2a89b1c848d458f42540e0113e7139b910abb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17630
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>