/*
 * Copyright (c) 2012 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2008 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Gabe Black
 */

#ifndef __MEM_MPORT_HH__
#define __MEM_MPORT_HH__

#include "mem/mem_object.hh"
#include "mem/tport.hh"

/*
 * This file defines a port class which is used for sending and receiving
 * messages. These messages are atomic units which don't interact and
 * should be smaller than a cache block. This class is based on
 * the underpinnings of SimpleTimingPort, but it tweaks some of the external
 * functions.
 */
class MessageSlavePort : public SimpleTimingPort
{

  public:
    MessageSlavePort(const std::string &name, MemObject *owner) :
        SimpleTimingPort(name, owner)
    {}

    virtual ~MessageSlavePort()
    {}

  protected:

    Tick recvAtomic(PacketPtr pkt);

    virtual Tick recvMessage(PacketPtr pkt) = 0;
};

class MessageMasterPort : public QueuedMasterPort
{
  public:

    MessageMasterPort(const std::string &name, MemObject *owner) :
        QueuedMasterPort(name, owner, reqQueue, snoopRespQueue),
        reqQueue(*owner, *this), snoopRespQueue(*owner, *this)
    {}

    virtual ~MessageMasterPort()
    {}

    bool recvTimingResp(PacketPtr pkt) { recvResponse(pkt); return true; }

  protected:

    /** A packet queue for outgoing packets. */
    ReqPacketQueue reqQueue;
    SnoopRespPacketQueue snoopRespQueue;

    // Accept and ignore responses.
    virtual Tick recvResponse(PacketPtr pkt)
    {
        return 0;
    }
};

#endif