commit f7f75ad053b492897ffc76808541dc40f2239aed
author Gabe Black <gblack@eecs.umich.edu> Wed Jun 02 12:58:07 2010 -0500
committer Gabe Black <gblack@eecs.umich.edu> Wed Jun 02 12:58:07 2010 -0500
tree 68886981edd8d675aae3809519a1777f590b4fd7
parent 00baeb742d8ff3f735466131253bf457664ecc6b

ARM: Implement the ldrex instruction.

src/arch/arm/isa/insts/ldr.isa

diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index 8513529..da20cab 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -74,7 +74,8 @@
         exec_output += newExec
 
     def buildImmLoad(mnem, post, add, writeback, \
-                     size=4, sign=False, user=False, prefetch=False):
+                     size=4, sign=False, user=False, \
+                     prefetch=False, ldrex=False):
         name = mnem
         Name = loadImmClassName(post, add, writeback, \
                                 size, sign, user)
@@ -98,7 +99,11 @@
             temp = temp;
             ''' % buildMemSuffix(sign, size)
         else:
-            memFlags = []
+            if ldrex:
+                memFlags = ["Request::LLSC"]
+                Name = "%s_%s" % (mnem.upper(), Name)
+            else:
+                memFlags = []
             accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
         if writeback:
             accCode += "Base = Base %s;\n" % offset
@@ -140,7 +145,7 @@
 
         emitLoad(name, Name, False, eaCode, accCode, memFlags, [], base)
 
-    def buildDoubleImmLoad(mnem, post, add, writeback):
+    def buildDoubleImmLoad(mnem, post, add, writeback, ldrex=False):
         name = mnem
         Name = loadDoubleImmClassName(post, add, writeback)
 
@@ -159,11 +164,16 @@
         Rdo = bits(Mem.ud, 31, 0);
         Rde = bits(Mem.ud, 63, 32);
         '''
+        if ldrex:
+            memFlags = ["Request::LLSC"]
+            Name = "%s_%s" % (mnem.upper(), Name)
+        else:
+            memFlags = []
         if writeback:
             accCode += "Base = Base %s;\n" % offset
         base = buildMemBase("MemoryImm", post, writeback)
 
-        emitLoad(name, Name, True, eaCode, accCode, [], [], base)
+        emitLoad(name, Name, True, eaCode, accCode, memFlags, [], base)
 
     def buildDoubleRegLoad(mnem, post, add, writeback):
         name = mnem
@@ -241,4 +251,9 @@
     buildPrefetches("pld")
     buildPrefetches("pldw")
     buildPrefetches("pli")
+
+    buildImmLoad("ldrex", False, True, False, size=4, ldrex=True)
+    buildImmLoad("ldrexh", False, True, False, size=2, ldrex=True)
+    buildImmLoad("ldrexb", False, True, False, size=1, ldrex=True)
+    buildDoubleImmLoad("ldrexd", False, True, False, ldrex=True)
 }};