commit f838a332be4b98ddc039f388bef1e307567db37c
author Sandipan Das <sandipan@linux.ibm.com> Wed Jan 30 20:18:49 2019 +0530
committer Sandipan Das <sandipan@linux.ibm.com> Mon Mar 25 04:48:58 2019 +0000
tree 4b7dbad0f251304141c3592b943003722ee4287a
parent 4847330db3a12d08c9fe9fbfab052ff61e3365b6

arch-power: Rename program counter registers

The Power ISA specification lists the Program Counter (PC) and
the Next Program Counter (NPC) registers as Current Instruction
Address (CIA) and Next Instruction Address (NIA). This applies
the ISA naming convention for these two registers.

Change-Id: I8b9094ab1c809f4dfdb4d7330c17f360adf063e9
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16603
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

src/arch/power/isa/decoder.isa

diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index d2365bd..060d6a3 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -386,12 +386,12 @@
 
         // Conditionally branch relative to PC based on CR and CTR.
         format BranchPCRelCondCtr {
-            0: bc({{ NPC = (uint32_t)(PC + disp); }});
+            0: bc({{ NIA = (uint32_t)(CIA + disp); }});
         }
 
         // Conditionally branch to fixed address based on CR and CTR.
         format BranchNonPCRelCondCtr {
-            1: bca({{ NPC = targetAddr; }});
+            1: bca({{ NIA = targetAddr; }});
         }
     }
 
@@ -399,12 +399,12 @@
 
         // Unconditionally branch relative to PC.
         format BranchPCRel {
-            0: b({{ NPC = (uint32_t)(PC + disp); }});
+            0: b({{ NIA = (uint32_t)(CIA + disp); }});
         }
 
         // Unconditionally branch to fixed address.
         format BranchNonPCRel {
-            1: ba({{ NPC = targetAddr; }});
+            1: ba({{ NIA = targetAddr; }});
         }
     }
 
@@ -412,12 +412,12 @@
 
         // Conditionally branch to address in LR based on CR and CTR.
         format BranchLrCondCtr {
-           16: bclr({{ NPC = LR & 0xfffffffc; }});
+           16: bclr({{ NIA = LR & 0xfffffffc; }});
         }
 
         // Conditionally branch to address in CTR based on CR.
         format BranchCtrCond {
-           528: bcctr({{ NPC = CTR & 0xfffffffc; }});
+           528: bcctr({{ NIA = CTR & 0xfffffffc; }});
         }
 
         // Condition register manipulation instructions.

src/arch/power/isa/formats/branch.isa

diff --git a/src/arch/power/isa/formats/branch.isa b/src/arch/power/isa/formats/branch.isa
index d51ed5c..728f562 100644
--- a/src/arch/power/isa/formats/branch.isa
+++ b/src/arch/power/isa/formats/branch.isa
@@ -48,7 +48,7 @@
 let {{
 
 # Simple code to update link register (LR).
-updateLrCode = 'LR = PC + 4;'
+updateLrCode = 'LR = CIA + 4;'
 
 }};
 
@@ -105,7 +105,7 @@
     cond_code =  'if(condOk(CR)) {\n'
     cond_code += '    ' + br_code + '\n'
     cond_code += '} else {\n'
-    cond_code += '    NPC = NPC;\n'
+    cond_code += '    NIA = NIA;\n'
     cond_code += '}\n'
     return cond_code
 
@@ -119,7 +119,7 @@
     cond_code += 'if(ctr_ok && cond_ok) {\n'
     cond_code += '    ' + br_code + '\n'
     cond_code += '} else {\n'
-    cond_code += '    NPC = NPC;\n'
+    cond_code += '    NIA = NIA;\n'
     cond_code += '}\n'
     cond_code += 'CTR = ctr;\n'
     return cond_code

src/arch/power/isa/operands.isa

diff --git a/src/arch/power/isa/operands.isa b/src/arch/power/isa/operands.isa
index 98b91dc..a72a071 100644
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -59,8 +59,8 @@
     'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8),
 
     # Program counter and next
-    'PC': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 9),
-    'NPC': ('PCState', 'uw', 'npc', (None, None, 'IsControl'), 9),
+    'CIA': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 9),
+    'NIA': ('PCState', 'uw', 'npc', (None, None, 'IsControl'), 9),
 
     # Control registers
     'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9),